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mmc: core: rk_sdmmc: prepare for next Soc(s)

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This commit is contained in:
lintao
2014-06-24 13:25:04 +08:00
parent e8242f4e1b
commit 9e489adecc
2 changed files with 36 additions and 6 deletions
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30
drivers/mmc/host/dw_mmc-rockchip.c
View File

@@ -19,6 +19,7 @@
#include <linux/of_gpio.h>
#include <linux/slab.h>
#include <linux/rockchip/cpu.h>
#include <linux/rockchip/cru.h>
#include "rk_sdmmc.h"
#include "dw_mmc-pltfm.h"
@@ -31,7 +32,10 @@
* sdmmc,sdio0,sdio1,emmc id=0~3
* cclk_in_drv, cclk_in_sample i=0,1
*/
#define CRU_SDMMC_CON(id, tuning_type) (0x200 + ((id) * 8) + ((tuning_type) * 4))
static u32 cru_tuning_base = 0;
#define CRU_SDMMC_CON(id, tuning_type) (cru_tuning_base + ((id) * 8) + ((tuning_type) * 4))
#define MAX_DELAY_LINE (0xff)
#define FREQ_REF_150MHZ (150000000)
@@ -67,6 +71,7 @@ enum{
enum dw_mci_rockchip_type {
DW_MCI_TYPE_RK3188,
DW_MCI_TYPE_RK3288,
DW_MCI_TYPE_RK3036,
};
/* Rockchip implementation specific driver private data */
@@ -88,6 +93,9 @@ static struct dw_mci_rockchip_compatible {
},{
.compatible = "rockchip,rk32xx-sdmmc",
.ctrl_type = DW_MCI_TYPE_RK3288,
},{
.compatible = "rockchip,rk3036-sdmmc",
.ctrl_type = DW_MCI_TYPE_RK3036,
},
};
@@ -210,9 +218,16 @@ static inline u8 dw_mci_rockchip_move_next_clksmpl(struct dw_mci *host, u8 con_i
return val;
}
static void dw_mci_rockchip_load_tuning_base(void)
{
if(cpu_is_rk3288())
cru_tuning_base = RK3288_CRU_SDMMC_CON0;
/* Fixme: 3036
else if(cpu_is_rk3036())
cru_tuning_base = RK3036_CRU_SDMMC_CON0;
*/
}
static int inline __dw_mci_rockchip_execute_tuning(struct dw_mci_slot *slot, u32 opcode,
u8 *blk_test, unsigned int blksz)
@@ -273,7 +288,9 @@ static int dw_mci_rockchip_execute_tuning(struct dw_mci_slot *slot, u32 opcode,
int ref = 0;
unsigned int blksz = tuning_data->blksz;
MMC_DBG_INFO_FUNC(host->mmc,"execute tuning: [%s]", mmc_hostname(host->mmc));
MMC_DBG_INFO_FUNC(host->mmc,"execute tuning: [%s]", mmc_hostname(host->mmc));
dw_mci_rockchip_load_tuning_base();
blk_test = kmalloc(blksz, GFP_KERNEL);
if (!blk_test)
@@ -292,7 +309,10 @@ static int dw_mci_rockchip_execute_tuning(struct dw_mci_slot *slot, u32 opcode,
So we take average --- 60ps, (1.66ns/ 2) = 0.83(middle-value),TAKE 0.9
0.9 / 60ps = 15 delayline
*/
if(cpu_is_rk3288()){
if(cpu_is_rk3288()){
/*
Fixme: 3036: dose it compatitable?
*/
ref = ((FREQ_REF_150MHZ + host->bus_hz - 1) / host->bus_hz);
step = (15 * ref);

12
drivers/mmc/host/rk_sdmmc.c
View File

@@ -48,6 +48,9 @@
#include <linux/regulator/rockchip_io_vol_domain.h>
#include "../../clk/rockchip/clk-ops.h"
/*
Fixme: 3036: RK_GRF_VIRT compatitable?
*/
#define grf_writel(v, offset) do { writel_relaxed(v, RK_GRF_VIRT + offset); dsb(); } while (0)
#define RK_SDMMC_DRIVER_VERSION "Ver 1.11 2014-06-05"
@@ -1527,7 +1530,11 @@ enum{
IO_DOMAIN_33 = 3300,
};
static void dw_mci_do_grf_io_domain_switch(struct dw_mci *host, u32 voltage)
{
{
/*
Fixme: 3036: RK3288_GRF_IO_VSEL compatitable?
*/
if(cpu_is_rk3288()){
if(voltage == IO_DOMAIN_33)
voltage = 0;
@@ -3669,6 +3676,9 @@ int dw_mci_resume(struct dw_mci *host)
printk("%s: Warning : Default pinctrl setting failed!\n", mmc_hostname(host->mmc));
host->mmc->rescan_disable = 0;
if(cpu_is_rk3288()) {
/*
Fixme: 3036: RK3288_GRF_SOC_CON0 compatitable?
*/
grf_writel(((1<<12)<<16)|(0<<12), RK3288_GRF_SOC_CON0);//disable jtag
}
}