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crypto: rockchip: optimize the compatibility of ECC/PKA

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1. Ensure that the PKA and ECC modules can be switched over.
2. Improve the security of verify to prevent all zeros from
 being treated as the correct result in some exceptions.

Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: If7cdc418cb3285fa7fb905381bfea51587750ee5
This commit is contained in:
Lin Jinhan
2024-12-25 16:01:55 +08:00
committed by Tao Huang
parent 4c2e0b8915
commit 9f93757dac
3 changed files with 10 additions and 5 deletions
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4
drivers/crypto/rockchip/rk_crypto_ecc.c
View File

@@ -406,7 +406,9 @@ int rockchip_ecc_verify(int group_id, uint8_t *hash, uint32_t hash_len,
ret = rockchip_ecc_request_trigger();
exit:
if (ret || rk_word_cmp_zero(ecc_st->v, RK_ECP_MAX_WORDS)) {
if (ret ||
rk_word_cmp_zero(ecc_st->v, RK_ECP_MAX_WORDS) ||
rk_word_cmp_zero(ecc_st->r_, RK_ECP_MAX_WORDS) == 0) {
ret = -EKEYREJECTED;
dump_ecc_sram();
}

6
drivers/crypto/rockchip/rk_crypto_v2_pka.c
View File

@@ -85,11 +85,11 @@ enum pka_opcode {
#define PKA_BIGNUM_WORDS(x) (rk_bn_get_size(x) / sizeof(u32))
#define PKA_RAM_FOR_PKA() PKA_WRITE((CRYPTO_RAM_PKA_RDY << CRYPTO_WRITE_MASK_SHIFT) | \
CRYPTO_RAM_PKA_RDY, CRYPTO_RAM_CTL)
#define PKA_RAM_FOR_PKA() PKA_WRITE(CRYPTO_RAM_CTL_SEL_MASK | CRYPTO_RAM_CTL_PKA, \
CRYPTO_RAM_CTL)
#define PKA_RAM_FOR_CPU() do { \
PKA_WRITE((CRYPTO_RAM_PKA_RDY << CRYPTO_WRITE_MASK_SHIFT), CRYPTO_RAM_CTL); \
PKA_WRITE(CRYPTO_RAM_CTL_SEL_MASK | CRYPTO_RAM_CTL_CPU, CRYPTO_RAM_CTL); \
while ((PKA_READ(CRYPTO_RAM_ST) & 0x01) != CRYPTO_CLK_RAM_RDY) \
cpu_relax(); \
} while (0)

5
drivers/crypto/rockchip/rk_crypto_v2_reg.h
View File

@@ -301,7 +301,10 @@
#define CRYPTO_PKA_BASE_OFFSET 0x0480
#define CRYPTO_RAM_CTL (0x0480 - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_RAM_PKA_RDY BIT(0)
#define CRYPTO_RAM_CTL_SEL_MASK _SBF(16, 3)
#define CRYPTO_RAM_CTL_CPU _SBF(0, 0)
#define CRYPTO_RAM_CTL_PKA _SBF(0, 1)
#define CRYPTO_RAM_CTL_ECC _SBF(0, 2)
#define CRYPTO_RAM_ST (0x0484 - CRYPTO_PKA_BASE_OFFSET)
#define CRYPTO_CLK_RAM_RDY BIT(0)