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PCI: rockchip: dw: remove .link_up() hook from struct dw_pcie_ops

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[2.353901] rk-pcie 3c0000000.pcie Link up. LTSSM is 0x1
[2.354036] rk-pcie 3c0000000.pcie: PCI host bridge to bus 0000 :00
[2.354058] pci_bus 0000:00: root bus resource [bus 00-0f]
[2.354074] pci_bus 0000:00: root bus resource [??? 0x4000000-0xf40fffff flags 0x0]
...

The original link event is checking LTSSM and ensure it's in L0. However
enabling ASPM will make accessing config space failed. So commit
824c99261a ("PCI: rockchip: dw: Update link up check state") remove the LTSSM
check. But it introduce a situation that if link still in training and host
bridge tries to enumerate slot, it will fail unexpectedly. Fix this by removing
rk_pcie_link_up and let dwc core use its own port logic to decide the link state.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I41f05a8aa89ac33782d569ffa7d466cf95981c68
This commit is contained in:
Shawn Lin
2023-10-11 08:58:14 +08:00
committed by Tao Huang
parent ccaa5a7183
commit a095b98601
1 changed files with 0 additions and 19 deletions
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19
drivers/pci/controller/dwc/pcie-dw-rockchip.c
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@@ -702,24 +702,6 @@ static inline void rk_pcie_enable_ltssm(struct rk_pcie *rk_pcie)
rk_pcie_writel_apb(rk_pcie, 0x0, 0xC000C);
}
static int rk_pcie_link_up(struct dw_pcie *pci)
{
struct rk_pcie *rk_pcie = to_rk_pcie(pci);
u32 val;
if (rk_pcie->is_rk1808) {
val = rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_GENERAL_DEBUG);
if ((val & (PCIE_PHY_LINKUP | PCIE_DATA_LINKUP)) == 0x3)
return 1;
} else {
val = rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS);
if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000)
return 1;
}
return 0;
}
static void rk_pcie_enable_debug(struct rk_pcie *rk_pcie)
{
if (!IS_ENABLED(CONFIG_DEBUG_FS))
@@ -1601,7 +1583,6 @@ MODULE_DEVICE_TABLE(of, rk_pcie_of_match);
static const struct dw_pcie_ops dw_pcie_ops = {
.start_link = rk_pcie_establish_link,
.link_up = rk_pcie_link_up,
};
static int rk1808_pcie_fixup(struct rk_pcie *rk_pcie, struct device_node *np)