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media: i2c: rk628: update driver for dsi mode

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Change-Id: I895e49a64f5164d3665db6d7d7562a5f579ef725
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
This commit is contained in:
Jianwei Fan
2023-12-05 11:50:34 +00:00
committed by Tao Huang
parent a671b1e8c8
commit a09738071d
9 changed files with 272 additions and 138 deletions
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3
drivers/media/i2c/rk628/rk628.h
View File

@@ -49,6 +49,8 @@
#define GRF_GPIO_RXDDC_SCL_SEL(x) UPDATE(x, 5, 5)
#define GRF_DPHY_CH1_EN_MASK BIT(1)
#define GRF_DPHY_CH1_EN(x) UPDATE(x, 1, 1)
#define GRF_AS_DSIPHY_MASK BIT(0)
#define GRF_AS_DSIPHY(x) UPDATE(x, 0, 0)
#define GRF_SCALER_CON0 0x0010
#define SCL_VER_DOWN_MODE(x) HIWORD_UPDATE(x, 8, 8)
#define SCL_HOR_DOWN_MODE(x) HIWORD_UPDATE(x, 7, 7)
@@ -290,6 +292,7 @@ struct rk628 {
bool dual_mipi;
struct mipi_timing mipi_timing[2];
struct mutex rst_lock;
int tx_mode;
};
static inline int rk628_i2c_write(struct rk628 *rk628, u32 reg, u32 val)

5
drivers/media/i2c/rk628/rk628_combtxphy.c
View File

@@ -51,6 +51,9 @@ static void rk628_combtxphy_dsi_power_on(struct rk628 *rk628)
rk628_i2c_update_bits(rk628, COMBTXPHY_CON9, SW_DSI_FSET_EN_MASK |
SW_DSI_RCAL_EN_MASK | SW_LPTX_SR_TRIM_MASK, SW_DSI_FSET_EN |
SW_DSI_RCAL_EN | SW_LPTX_SR_TRIM(7));
if (rk628->tx_mode && rk628->dual_mipi)
rk628_i2c_update_bits(rk628, COMBTXPHY_CON6, SW_PLL_CTRL0_MASK, SW_PLL_CTRL0(1));
usleep_range(100, 200);
}
@@ -111,7 +114,7 @@ void rk628_txphy_set_mode(struct rk628 *rk628, enum phy_mode mode)
unsigned int flags = bus_width & 0xff;
fhsc = fin * (fhsc / fin);
if (fhsc < 80 || fhsc > 1500)
if (fhsc < 80 || fhsc > 1800)
return;
else if (fhsc < 375)
txphy->rate_div = 4;

8
drivers/media/i2c/rk628/rk628_combtxphy.h
View File

@@ -41,6 +41,8 @@
#define SW_PLL_FB_DIV(x) UPDATE(x, 14, 10)
#define SW_PLL_FRAC_DIV(x) UPDATE(x, 9, 0)
#define COMBTXPHY_CON6 COMBTXPHY_REG(0x0018)
#define SW_PLL_CTRL0_MASK GENMASK(2, 0)
#define SW_PLL_CTRL0(x) UPDATE(x, 2, 0)
#define COMBTXPHY_CON7 COMBTXPHY_REG(0x001c)
#define SW_TX_RTERM_MASK GENMASK(22, 20)
#define SW_TX_RTERM(x) UPDATE(x, 22, 20)
@@ -52,8 +54,14 @@
#define SW_TX_CTL_CON4(x) UPDATE(x, 9, 8)
#define COMBTXPHY_CON8 COMBTXPHY_REG(0x0020)
#define COMBTXPHY_CON9 COMBTXPHY_REG(0x0024)
#define SW_HSTX_AMP_TRIM_MASK GENMASK(2, 0)
#define SW_HSTX_AMP_TRIM(x) UPDATE(x, 2, 0)
#define SW_LPTX_SR_TRIM_MASK GENMASK(6, 4)
#define SW_LPTX_SR_TRIM(x) UPDATE(x, 6, 4)
#define SW_DSI_RCAL_CTRL_MASK GENMASK(23, 16)
#define SW_DSI_RCAL_CTRL(x) UPDATE(x, 23, 16)
#define SW_DSI_RCAL_TRIM_MASK GENMASK(27, 24)
#define SW_DSI_RCAL_TRIM(x) UPDATE(x, 27, 24)
#define SW_DSI_FSET_EN_MASK BIT(29)
#define SW_DSI_FSET_EN BIT(29)
#define SW_DSI_RCAL_EN_MASK BIT(28)

153
drivers/media/i2c/rk628/rk628_csi_v4l2.c
View File

@@ -134,6 +134,7 @@ struct rk628_csi_mode {
static const s64 link_freq_menu_items[] = {
RK628_CSI_LINK_FREQ_LOW,
RK628_CSI_LINK_FREQ_HIGH,
RK628_CSI_LINK_FREQ_925M,
};
static const struct v4l2_dv_timings_cap rk628_csi_timings_cap = {
@@ -233,6 +234,10 @@ static const struct mipi_timing rk628f_csi1_mipi = {
0x4a, 0xf, 0x66, 0x3a, 0x3a, 0x5a, 0x1f
};
static const struct mipi_timing rk628f_dsi0_mipi = {
0x70, 0x1c, 0x7f, 0x70, 0x3f, 0x7f, 0x1f
};
static struct rkmodule_csi_dphy_param rk3588_dcphy_param = {
.vendor = PHY_VENDOR_SAMSUNG,
.lp_vol_ref = 0,
@@ -425,7 +430,8 @@ static int rk628_csi_get_detected_timings(struct v4l2_subdev *sd,
if (ret)
return ret;
if (bt->pixelclock > 300000000 && csi->rk628->version >= RK628F_VERSION) {
if ((bt->pixelclock > 300000000 && csi->rk628->version >= RK628F_VERSION) ||
(bt->width > 2048 && csi->plat_data->tx_mode == DSI_MODE)) {
v4l2_info(sd, "rk628f detect pixclk more than 300M, use dual mipi mode\n");
csi->rk628->dual_mipi = true;
} else {
@@ -506,8 +512,6 @@ static void rk628_csi_delayed_work_enable_hotplug(struct work_struct *work)
rk628_hdmirx_plugout(sd);
}
mutex_unlock(&csi->confctl_mutex);
if (csi->plat_data->tx_mode == DSI_MODE && plugin)
enable_stream(sd, true);
}
static int rk628_check_resulotion_change(struct v4l2_subdev *sd)
@@ -583,8 +587,6 @@ static void rk628_delayed_work_res_change(struct work_struct *work)
}
}
mutex_unlock(&csi->confctl_mutex);
if (csi->plat_data->tx_mode == DSI_MODE && plugin)
rk628_dsi_enable(sd);
}
static void rk628_hdmirx_hpd_ctrl(struct v4l2_subdev *sd, bool en)
@@ -749,20 +751,25 @@ static void rk628_dsi_set_scs(struct rk628_csi *csi)
video_fmt = (val & VIDEO_FORMAT_MASK) >> 5;
v4l2_info(&csi->sd, "%s PDEC_AVI_PB:%#x, video format:%d\n",
__func__, val, video_fmt);
if (video_fmt) {
if (csi->dsi.vid_mode == VIDEO_MODE)
rk628_i2c_write(csi->rk628, GRF_CSC_CTRL_CON,
SW_Y2R_EN(1) | SW_YUV2VYU_SWP(1));
else
rk628_i2c_write(csi->rk628, GRF_CSC_CTRL_CON,
SW_Y2R_EN(1) | SW_YUV2VYU_SWP(0));
if (csi->rk628->version == RK628D_VERSION) {
if (video_fmt) {
if (csi->dsi.vid_mode == VIDEO_MODE)
rk628_i2c_write(csi->rk628, GRF_CSC_CTRL_CON,
SW_Y2R_EN(1) | SW_YUV2VYU_SWP(1));
else
rk628_i2c_write(csi->rk628, GRF_CSC_CTRL_CON,
SW_Y2R_EN(1) | SW_YUV2VYU_SWP(0));
} else {
if (csi->dsi.vid_mode == VIDEO_MODE)
rk628_i2c_write(csi->rk628, GRF_CSC_CTRL_CON,
SW_Y2R_EN(0) | SW_YUV2VYU_SWP(1));
else
rk628_i2c_write(csi->rk628, GRF_CSC_CTRL_CON,
SW_Y2R_EN(0) | SW_YUV2VYU_SWP(0));
}
} else {
if (csi->dsi.vid_mode == VIDEO_MODE)
rk628_i2c_write(csi->rk628, GRF_CSC_CTRL_CON,
SW_Y2R_EN(0) | SW_YUV2VYU_SWP(1));
else
rk628_i2c_write(csi->rk628, GRF_CSC_CTRL_CON,
SW_Y2R_EN(0) | SW_YUV2VYU_SWP(0));
rk628_i2c_write(csi->rk628, GRF_CSC_CTRL_CON, SW_YUV2VYU_SWP(0));
rk628_post_process_csc_en(csi->rk628);
}
/* if avi packet is not stable, reset ctrl*/
@@ -801,9 +808,15 @@ static void enable_dsitx(struct v4l2_subdev *sd)
/* rst for dsi0 */
rk628_control_assert(csi->rk628, RGU_DSI0);
usleep_range(20, 40);
udelay(20);
rk628_control_deassert(csi->rk628, RGU_DSI0);
usleep_range(20, 40);
udelay(20);
/* rst for dsi1 */
rk628_control_assert(csi->rk628, RGU_DSI1);
udelay(20);
rk628_control_deassert(csi->rk628, RGU_DSI1);
udelay(20);
rk628_dsi_enable(sd);
}
@@ -821,6 +834,7 @@ static void rk628_dsi_enable_stream(struct v4l2_subdev *sd, bool en)
rk628_hdmirx_vid_enable(sd, false);
rk628_i2c_write(csi->rk628, GRF_SCALER_CON0, SCL_EN(0));
rk628_dsi_disable_stream(&csi->dsi);
}
static void rk628_csi_disable_stream(struct v4l2_subdev *sd)
@@ -1344,6 +1358,11 @@ static void rk628_csi_initial_setup(struct v4l2_subdev *sd)
csi->rk628->mipi_timing[0] = rk628d_csi_mipi;
}
if (csi->plat_data->tx_mode == DSI_MODE) {
csi->rk628->mipi_timing[0] = rk628f_dsi0_mipi;
csi->rk628->mipi_timing[1] = rk628f_dsi0_mipi;
}
csi->rk628->dphy_lane_en = 0x1f;
if (csi->plat_data->tx_mode == CSI_MODE) {
rk628_mipi_dphy_reset(csi->rk628);
@@ -1691,14 +1710,25 @@ static int rk628_csi_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
return 0;
}
static inline unsigned int fps_calc(const struct v4l2_bt_timings *t)
{
if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
return 0;
return DIV_ROUND_CLOSEST((unsigned int)t->pixelclock,
V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
}
static int rk628_csi_s_stream(struct v4l2_subdev *sd, int enable)
{
struct rk628_csi *csi = to_csi(sd);
if (csi->plat_data->tx_mode == CSI_MODE)
enable_stream(sd, enable);
else
rk628_dsi_enable_stream(sd, enable);
enable_stream(sd, enable);
v4l2_info(sd, "%s: on: %d, %dx%d@%d\n", __func__, enable,
csi->timings.bt.width,
csi->timings.bt.height,
fps_calc(&csi->timings.bt));
return 0;
}
@@ -1772,22 +1802,46 @@ static int rk628_csi_get_fmt(struct v4l2_subdev *sd,
V4L2_FIELD_INTERLACED : V4L2_FIELD_NONE;
mutex_unlock(&csi->confctl_mutex);
if (csi->timings.bt.pixelclock > 150000000 || csi->csi_lanes_in_use <= 2) {
v4l2_dbg(1, debug, sd,
"%s res wxh:%dx%d, link freq:%llu, pixrate:%u\n",
__func__, csi->timings.bt.width, csi->timings.bt.height,
link_freq_menu_items[1], RK628_CSI_PIXEL_RATE_HIGH);
__v4l2_ctrl_s_ctrl(csi->link_freq, 1);
__v4l2_ctrl_s_ctrl_int64(csi->pixel_rate,
RK628_CSI_PIXEL_RATE_HIGH);
if (csi->plat_data->tx_mode == CSI_MODE) {
if (csi->timings.bt.pixelclock > 150000000 || csi->csi_lanes_in_use <= 2) {
v4l2_dbg(1, debug, sd,
"%s res wxh:%dx%d, link freq:%llu, pixrate:%u\n",
__func__, csi->timings.bt.width, csi->timings.bt.height,
link_freq_menu_items[1], RK628_CSI_PIXEL_RATE_HIGH);
__v4l2_ctrl_s_ctrl(csi->link_freq, 1);
__v4l2_ctrl_s_ctrl_int64(csi->pixel_rate,
RK628_CSI_PIXEL_RATE_HIGH);
} else {
v4l2_dbg(1, debug, sd,
"%s res wxh:%dx%d, link freq:%llu, pixrate:%u\n",
__func__, csi->timings.bt.width, csi->timings.bt.height,
link_freq_menu_items[0], RK628_CSI_PIXEL_RATE_LOW);
__v4l2_ctrl_s_ctrl(csi->link_freq, 0);
__v4l2_ctrl_s_ctrl_int64(csi->pixel_rate,
RK628_CSI_PIXEL_RATE_LOW);
}
} else {
v4l2_dbg(1, debug, sd,
"%s res wxh:%dx%d, link freq:%llu, pixrate:%u\n",
__func__, csi->timings.bt.width, csi->timings.bt.height,
link_freq_menu_items[0], RK628_CSI_PIXEL_RATE_LOW);
__v4l2_ctrl_s_ctrl(csi->link_freq, 0);
__v4l2_ctrl_s_ctrl_int64(csi->pixel_rate,
RK628_CSI_PIXEL_RATE_LOW);
u32 rate;
csi->dsi.rk628 = csi->rk628;
csi->dsi.timings = csi->timings;
rate = rk628_dsi_get_lane_rate_mbps(&csi->dsi);
v4l2_dbg(1, debug, sd, "%s mipi bitrate:%u mbps\n", __func__, rate);
if (rate > 1300) {
csi->rk628->mipi_timing[0] = rk628f_dsi0_mipi;
csi->rk628->mipi_timing[1] = rk628f_dsi0_mipi;
__v4l2_ctrl_s_ctrl(csi->link_freq, 2);
} else if (rate <= 1300 && rate > 700) {
csi->rk628->mipi_timing[0] = rk628f_csi0_mipi;
csi->rk628->mipi_timing[1] = rk628f_csi0_mipi;
__v4l2_ctrl_s_ctrl(csi->link_freq, 1);
} else {
csi->rk628->mipi_timing[0] = rk628f_csi0_mipi;
csi->rk628->mipi_timing[1] = rk628f_csi0_mipi;
__v4l2_ctrl_s_ctrl(csi->link_freq, 0);
}
__v4l2_ctrl_s_ctrl_int64(csi->pixel_rate, RK628_CSI_PIXEL_RATE_HIGH);
}
v4l2_dbg(1, debug, sd, "%s: fmt code:%d, w:%d, h:%d, field code:%d\n",
@@ -2042,6 +2096,12 @@ static long rk628_csi_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
capture_info->mode = 0;
}
break;
case RKMODULE_GET_CSI_DSI_INFO:
if (csi->plat_data->tx_mode == DSI_MODE)
*(int *)arg = RKMODULE_DSI_INPUT;
else
*(int *)arg = RKMODULE_CSI_INPUT;
break;
default:
ret = -ENOIOCTLCMD;
break;
@@ -2200,6 +2260,20 @@ static long rk628_csi_compat_ioctl32(struct v4l2_subdev *sd,
}
kfree(capture_info);
break;
case RKMODULE_GET_CSI_DSI_INFO:
seq = kzalloc(sizeof(*seq), GFP_KERNEL);
if (!seq) {
ret = -ENOMEM;
return ret;
}
ret = rk628_csi_ioctl(sd, cmd, seq);
if (!ret) {
ret = copy_to_user(up, seq, sizeof(*seq));
if (ret)
ret = -EFAULT;
}
kfree(seq);
break;
default:
ret = -ENOIOCTLCMD;
break;
@@ -2552,6 +2626,7 @@ static int rk628_csi_probe(struct i2c_client *client,
match = of_match_node(rk628_csi_of_match, dev->of_node);
csi->plat_data = match->data;
rk628->tx_mode = csi->plat_data->tx_mode;
csi->rk628 = rk628;
csi->dsi.rk628 = rk628;
csi->cur_mode = &supported_modes[0];

196
drivers/media/i2c/rk628/rk628_dsi.c
View File

@@ -58,7 +58,7 @@ static inline int dsi_update_bits(struct rk628 *rk628, int id,
return rk628_i2c_update_bits(rk628, dsi_base + reg, mask, val);
}
static void mipi_dphy_power_on_dsi(struct rk628_dsi *dsi)
static void mipi_dphy_power_on_dsi(struct rk628_dsi *dsi, uint8_t mipi_id)
{
int dev_id;
unsigned int dsi_base;
@@ -66,29 +66,38 @@ static void mipi_dphy_power_on_dsi(struct rk628_dsi *dsi)
int ret;
struct rk628 *rk628 = dsi->rk628;
dev_id = RK628_DEV_DSI0;
dsi_base = DSI0_BASE;
dev_id = mipi_id ? RK628_DEV_DSI1 : RK628_DEV_DSI0;
dsi_base = mipi_id ? DSI1_BASE : DSI0_BASE;
dsi_update_bits(rk628, 0, DSI_PHY_RSTZ, PHY_ENABLECLK, 0);
dsi_update_bits(rk628, 0, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0);
dsi_update_bits(rk628, 0, DSI_PHY_RSTZ, PHY_RSTZ, 0);
rk628_testif_testclr_assert(dsi->rk628, 0);
dsi_update_bits(rk628, mipi_id, DSI_PHY_RSTZ, PHY_ENABLECLK, 0);
dsi_update_bits(rk628, mipi_id, DSI_PHY_RSTZ, PHY_SHUTDOWNZ, 0);
dsi_update_bits(rk628, mipi_id, DSI_PHY_RSTZ, PHY_RSTZ, 0);
rk628_testif_testclr_assert(dsi->rk628, mipi_id);
/* Set all REQUEST inputs to zero */
rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON,
FORCERXMODE_MASK | FORCETXSTOPMODE_MASK,
FORCETXSTOPMODE(0) | FORCERXMODE(0));
if (mipi_id)
rk628_i2c_update_bits(rk628, GRF_MIPI_TX1_CON,
FORCERXMODE_MASK | FORCETXSTOPMODE_MASK,
FORCETXSTOPMODE(0) | FORCERXMODE(0));
else
rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON,
FORCERXMODE_MASK | FORCETXSTOPMODE_MASK,
FORCETXSTOPMODE(0) | FORCERXMODE(0));
udelay(1);
rk628_testif_testclr_deassert(dsi->rk628, 0);
rk628_testif_testclr_deassert(dsi->rk628, mipi_id);
rk628_mipi_dphy_init_hsfreqrange(dsi->rk628, dsi->lane_mbps, mipi_id);
rk628_mipi_dphy_init_hsfreqrange(dsi->rk628, dsi->lane_mbps, 0);
if (dsi->lane_mbps > 1100)
rk628_mipi_dphy_init_hsmanual(dsi->rk628, true, mipi_id);
else
rk628_mipi_dphy_init_hsmanual(dsi->rk628, false, mipi_id);
dsi_update_bits(rk628, 0, DSI_PHY_RSTZ,
dsi_update_bits(rk628, mipi_id, DSI_PHY_RSTZ,
PHY_ENABLECLK, PHY_ENABLECLK);
dsi_update_bits(rk628, 0, DSI_PHY_RSTZ,
dsi_update_bits(rk628, mipi_id, DSI_PHY_RSTZ,
PHY_SHUTDOWNZ, PHY_SHUTDOWNZ);
dsi_update_bits(rk628, 0, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ);
dsi_update_bits(rk628, mipi_id, DSI_PHY_RSTZ, PHY_RSTZ, PHY_RSTZ);
usleep_range(1500, 2000);
rk628_txphy_power_on(rk628);
@@ -112,42 +121,42 @@ static void mipi_dphy_power_on_dsi(struct rk628_dsi *dsi)
udelay(10);
}
static void rk628_dsi_pre_enable(struct rk628_dsi *dsi)
static void rk628_dsi_pre_enable(struct rk628_dsi *dsi, uint8_t mipi_id)
{
u32 val;
struct rk628 *rk628 = dsi->rk628;
u32 lane_mbps = dsi->lane_mbps;
dsi_write(rk628, 0, DSI_PWR_UP, RESET);
dsi_write(rk628, 0, DSI_MODE_CFG, CMD_VIDEO_MODE(COMMAND_MODE));
dsi_write(rk628, mipi_id, DSI_PWR_UP, RESET);
dsi_write(rk628, mipi_id, DSI_MODE_CFG, CMD_VIDEO_MODE(COMMAND_MODE));
val = DIV_ROUND_UP(lane_mbps >> 3, 20);
dsi_write(rk628, 0, DSI_CLKMGR_CFG,
dsi_write(rk628, mipi_id, DSI_CLKMGR_CFG,
TO_CLK_DIVISION(10) | TX_ESC_CLK_DIVISION(val));
val = CRC_RX_EN | ECC_RX_EN | BTA_EN | EOTP_TX_EN;
if (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)
val &= ~EOTP_TX_EN;
dsi_write(rk628, 0, DSI_PCKHDL_CFG, val);
dsi_write(rk628, mipi_id, DSI_PCKHDL_CFG, val);
dsi_write(rk628, 0, DSI_TO_CNT_CFG,
dsi_write(rk628, mipi_id, DSI_TO_CNT_CFG,
HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
dsi_write(rk628, 0, DSI_BTA_TO_CNT, 0xd00);
dsi_write(rk628, 0, DSI_PHY_TMR_CFG,
dsi_write(rk628, mipi_id, DSI_BTA_TO_CNT, 0xd00);
dsi_write(rk628, mipi_id, DSI_PHY_TMR_CFG,
PHY_HS2LP_TIME(0x14) | PHY_LP2HS_TIME(0x10) |
MAX_RD_TIME(10000));
dsi_write(rk628, 0, DSI_PHY_TMR_LPCLK_CFG,
dsi_write(rk628, mipi_id, DSI_PHY_TMR_LPCLK_CFG,
PHY_CLKHS2LP_TIME(0x40) | PHY_CLKLP2HS_TIME(0x40));
dsi_write(rk628, 0, DSI_PHY_IF_CFG,
dsi_write(rk628, mipi_id, DSI_PHY_IF_CFG,
PHY_STOP_WAIT_TIME(0x20) | N_LANES(4 - 1));
mipi_dphy_power_on_dsi(dsi);
mipi_dphy_power_on_dsi(dsi, mipi_id);
dsi_write(rk628, 0, DSI_PWR_UP, POWER_UP);
dsi_write(rk628, mipi_id, DSI_PWR_UP, POWER_UP);
}
static void rk628_dsi_set_vid_mode(struct rk628_dsi *dsi)
static void rk628_dsi_set_vid_mode(struct rk628_dsi *dsi, uint8_t mipi_id)
{
unsigned int lanebyteclk = (dsi->lane_mbps * 1000L) >> 3;
u64 dpipclk;
@@ -176,16 +185,16 @@ static void rk628_dsi_set_vid_mode(struct rk628_dsi *dsi)
else
val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
dsi_write(rk628, 0, DSI_VID_MODE_CFG, val);
dsi_write(rk628, mipi_id, DSI_VID_MODE_CFG, val);
if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
dsi_update_bits(rk628, 0, DSI_LPCLK_CTRL,
dsi_update_bits(rk628, mipi_id, DSI_LPCLK_CTRL,
AUTO_CLKLANE_CTRL, AUTO_CLKLANE_CTRL);
pkt_size = VID_PKT_SIZE(bt->width);
pkt_size = rk628->dual_mipi ? VID_PKT_SIZE(bt->width) / 2 : VID_PKT_SIZE(bt->width);
dsi_write(rk628, 0, DSI_VID_PKT_SIZE, pkt_size);
dsi_write(rk628, mipi_id, DSI_VID_PKT_SIZE, pkt_size);
vactive = bt->height;
vs = bt->vsync;
@@ -202,43 +211,47 @@ static void rk628_dsi_set_vid_mode(struct rk628_dsi *dsi)
//hline_time = hline * lanebyteclk / dpipclk;
hline_time = DIV_ROUND_CLOSEST_ULL(hline * lanebyteclk, dpipclk);
dsi_write(rk628, 0, DSI_VID_HLINE_TIME,
dsi_write(rk628, mipi_id, DSI_VID_HLINE_TIME,
VID_HLINE_TIME(hline_time));
//hs_time = hs * lanebyteclk / dpipclk;
hs_time = DIV_ROUND_CLOSEST_ULL(hs * lanebyteclk, dpipclk);
dsi_write(rk628, 0, DSI_VID_HSA_TIME, VID_HSA_TIME(hs_time));
dsi_write(rk628, mipi_id, DSI_VID_HSA_TIME, VID_HSA_TIME(hs_time));
//hbp_time = hbp * lanebyteclk / dpipclk;
hbp_time = DIV_ROUND_CLOSEST_ULL(hbp * lanebyteclk, dpipclk);
dsi_write(rk628, 0, DSI_VID_HBP_TIME, VID_HBP_TIME(hbp_time));
dsi_write(rk628, mipi_id, DSI_VID_HBP_TIME, VID_HBP_TIME(hbp_time));
dsi_write(rk628, 0, DSI_VID_VACTIVE_LINES, vactive);
dsi_write(rk628, 0, DSI_VID_VSA_LINES, vs);
dsi_write(rk628, 0, DSI_VID_VFP_LINES, vfp);
dsi_write(rk628, 0, DSI_VID_VBP_LINES, vbp);
dsi_write(rk628, mipi_id, DSI_VID_VACTIVE_LINES, vactive);
dsi_write(rk628, mipi_id, DSI_VID_VSA_LINES, vs);
dsi_write(rk628, mipi_id, DSI_VID_VFP_LINES, vfp);
dsi_write(rk628, mipi_id, DSI_VID_VBP_LINES, vbp);
dsi_write(rk628, 0, DSI_MODE_CFG, CMD_VIDEO_MODE(VIDEO_MODE));
dsi_write(rk628, mipi_id, DSI_MODE_CFG, CMD_VIDEO_MODE(VIDEO_MODE));
}
static void rk628_dsi_set_cmd_mode(struct rk628_dsi *dsi)
static void rk628_dsi_set_cmd_mode(struct rk628_dsi *dsi, uint8_t mipi_id)
{
struct rk628 *rk628 = dsi->rk628;
dsi_update_bits(rk628, 0, DSI_CMD_MODE_CFG, DCS_LW_TX, 0);
dsi_write(rk628, 0, DSI_EDPI_CMD_SIZE,
EDPI_ALLOWED_CMD_SIZE(dsi->timings.bt.width));
dsi_write(rk628, 0, DSI_MODE_CFG, CMD_VIDEO_MODE(COMMAND_MODE));
dsi_update_bits(rk628, mipi_id, DSI_CMD_MODE_CFG, DCS_LW_TX, 0);
if (rk628->dual_mipi)
dsi_write(rk628, mipi_id, DSI_EDPI_CMD_SIZE,
EDPI_ALLOWED_CMD_SIZE(dsi->timings.bt.width / 2));
else
dsi_write(rk628, mipi_id, DSI_EDPI_CMD_SIZE,
EDPI_ALLOWED_CMD_SIZE(dsi->timings.bt.width));
dsi_write(rk628, mipi_id, DSI_MODE_CFG, CMD_VIDEO_MODE(COMMAND_MODE));
}
static void rk628_dsi_enable(struct rk628_dsi *dsi)
static void rk628_dsi_enable(struct rk628_dsi *dsi, uint8_t mipi_id)
{
u32 val;
struct rk628 *rk628 = dsi->rk628;
dsi_write(rk628, 0, DSI_PWR_UP, RESET);
dsi_write(rk628, mipi_id, DSI_PWR_UP, RESET);
val = DPI_COLOR_CODING(5);
dsi_write(rk628, 0, DSI_DPI_COLOR_CODING, val);
dsi_write(rk628, mipi_id, DSI_DPI_COLOR_CODING, val);
val = 0;
@@ -249,26 +262,27 @@ static void rk628_dsi_enable(struct rk628_dsi *dsi)
* val |= HSYNC_ACTIVE_LOW;
*/
dsi_write(rk628, 0, DSI_DPI_CFG_POL, val);
dsi_write(rk628, mipi_id, DSI_DPI_CFG_POL, val);
dsi_write(rk628, 0, DSI_DPI_VCID, DPI_VID(0));
dsi_write(rk628, 0, DSI_DPI_LP_CMD_TIM,
dsi_write(rk628, mipi_id, DSI_DPI_VCID, DPI_VID(0));
dsi_write(rk628, mipi_id, DSI_DPI_LP_CMD_TIM,
OUTVACT_LPCMD_TIME(4) | INVACT_LPCMD_TIME(4));
dsi_update_bits(rk628, 0, DSI_LPCLK_CTRL,
PHY_TXREQUESTCLKHS | AUTO_CLKLANE_CTRL,
PHY_TXREQUESTCLKHS | AUTO_CLKLANE_CTRL);
dsi_update_bits(rk628, mipi_id, DSI_LPCLK_CTRL,
PHY_TXREQUESTCLKHS,
PHY_TXREQUESTCLKHS);
if (dsi->vid_mode == VIDEO_MODE)
rk628_dsi_set_vid_mode(dsi);
rk628_dsi_set_vid_mode(dsi, mipi_id);
else
rk628_dsi_set_cmd_mode(dsi);
rk628_dsi_set_cmd_mode(dsi, mipi_id);
dsi_write(rk628, 0, DSI_PWR_UP, POWER_UP);
dsi_write(rk628, mipi_id, DSI_PWR_UP, POWER_UP);
}
static u32 rk628_dsi_get_lane_rate(struct rk628_dsi *dsi)
u32 rk628_dsi_get_lane_rate_mbps(struct rk628_dsi *dsi)
{
struct rk628 *rk628 = dsi->rk628;
u32 lane_rate;
u32 max_lane_rate = 1500;
u32 max_lane_rate = 1800;
u8 bpp, lanes;
u64 pixelclock = dsi->timings.bt.pixelclock;
@@ -278,33 +292,81 @@ static u32 rk628_dsi_get_lane_rate(struct rk628_dsi *dsi)
lane_rate = pixelclock * bpp;
lane_rate = div_u64(lane_rate, lanes);
lane_rate = DIV_ROUND_UP(lane_rate * 5, 4);
if (rk628->dual_mipi)
lane_rate /= 2;
if (lane_rate > max_lane_rate)
if (lane_rate > 1300)
lane_rate = max_lane_rate;
else if (lane_rate > 700 && lane_rate <= 1300)
lane_rate = 1300;
else
lane_rate = 700;
return lane_rate;
}
EXPORT_SYMBOL(rk628_dsi_get_lane_rate_mbps);
void rk628_mipi_dsi_power_on(struct rk628_dsi *dsi)
{
struct rk628 *rk628 = dsi->rk628;
u32 rate = rk628_dsi_get_lane_rate(dsi);
u32 rate = rk628_dsi_get_lane_rate_mbps(dsi);
int bus_width;
u32 mask = SW_OUTPUT_MODE_MASK;
u32 val = SW_OUTPUT_MODE(OUTPUT_MODE_DSI);
rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0, SW_OUTPUT_MODE_MASK,
SW_OUTPUT_MODE(OUTPUT_MODE_DSI));
rk628_i2c_update_bits(rk628, GRF_POST_PROC_CON, SW_SPLIT_EN, 0);
if (rk628->version == RK628F_VERSION) {
mask = SW_OUTPUT_COMBTX_MODE_MASK;
val = SW_OUTPUT_COMBTX_MODE(OUTPUT_MODE_DSI - 2);
rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON3,
GRF_AS_DSIPHY_MASK,
GRF_AS_DSIPHY(1));
}
rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0, mask, val);
dev_info(dsi->rk628->dev, "%s mipi mode, %sable dphy1 and split en\n",
rk628->dual_mipi ? "dual" : "single", rk628->dual_mipi ? "en" : "dis");
rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON3, GRF_DPHY_CH1_EN_MASK,
rk628->dual_mipi ? GRF_DPHY_CH1_EN(1) : GRF_DPHY_CH1_EN(0));
rk628_i2c_update_bits(rk628, GRF_POST_PROC_CON, SW_SPLIT_EN,
rk628->dual_mipi ? 1 : 0);
bus_width = rate << 8;
bus_width |= COMBTXPHY_MODULEA_EN;
if (rk628->dual_mipi)
bus_width |= COMBTXPHY_MODULEB_EN;
rk628_txphy_set_bus_width(dsi->rk628, bus_width);
rk628_txphy_set_mode(dsi->rk628, PHY_MODE_VIDEO_MIPI);
dsi->lane_mbps = rk628_txphy_get_bus_width(dsi->rk628);
dev_dbg(dsi->rk628->dev, "%s mipi bitrate:%llu mbps\n", __func__,
dev_info(dsi->rk628->dev, "%s mipi bitrate:%llu mbps\n", __func__,
dsi->lane_mbps);
rk628_dsi_pre_enable(dsi);
rk628_dsi_pre_enable(dsi, 0);
if (rk628->dual_mipi)
rk628_dsi_pre_enable(dsi, 1);
rk628_dsi_enable(dsi);
rk628_dsi_enable(dsi, 0);
if (rk628->dual_mipi)
rk628_dsi_enable(dsi, 1);
}
EXPORT_SYMBOL(rk628_mipi_dsi_power_on);
void rk628_dsi_disable_stream(struct rk628_dsi *dsi)
{
struct rk628 *rk628 = dsi->rk628;
dsi_write(rk628, 0, DSI_PWR_UP, RESET);
dsi_write(rk628, 0, DSI_LPCLK_CTRL, 0);
dsi_write(rk628, 0, DSI_EDPI_CMD_SIZE, 0);
dsi_write(rk628, 0, DSI_MODE_CFG, CMD_VIDEO_MODE(COMMAND_MODE));
dsi_write(rk628, 0, DSI_PWR_UP, POWER_UP);
dsi_write(rk628, 1, DSI_PWR_UP, RESET);
dsi_write(rk628, 1, DSI_LPCLK_CTRL, 0);
dsi_write(rk628, 1, DSI_EDPI_CMD_SIZE, 0);
dsi_write(rk628, 1, DSI_MODE_CFG, CMD_VIDEO_MODE(COMMAND_MODE));
dsi_write(rk628, 1, DSI_PWR_UP, POWER_UP);
rk628_txphy_power_off(rk628);
}
EXPORT_SYMBOL(rk628_dsi_disable_stream);

3
drivers/media/i2c/rk628/rk628_dsi.h
View File

@@ -166,8 +166,11 @@ struct rk628_dsi {
u64 lane_mbps;
int vid_mode;
int mode_flags;
uint8_t id;
};
void rk628_mipi_dsi_power_on(struct rk628_dsi *dsi);
void rk628_dsi_disable_stream(struct rk628_dsi *dsi);
u32 rk628_dsi_get_lane_rate_mbps(struct rk628_dsi *dsi);
#endif

10
drivers/media/i2c/rk628/rk628_hdmirx.c
View File

@@ -760,7 +760,7 @@ static void hdmirxphy_write(struct rk628 *rk628, u32 offset, u32 val)
rk628_i2c_write(rk628, HDMI_RX_I2CM_PHYG3_OPERATION, 1);
}
u32 hdmirxphy_read(struct rk628 *rk628, u32 offset)
static __maybe_unused u32 hdmirxphy_read(struct rk628 *rk628, u32 offset)
{
u32 val;
@@ -900,8 +900,12 @@ EXPORT_SYMBOL(rk628_hdmirx_get_format);
void rk628_set_bg_enable(struct rk628 *rk628, bool en)
{
if (en) {
rk628_i2c_write(rk628, GRF_BG_CTRL,
BG_R_OR_V(512) | BG_B_OR_U(512) | BG_G_OR_Y(64) | BG_ENABLE(1));
if (rk628->tx_mode)
rk628_i2c_write(rk628, GRF_BG_CTRL,
BG_R_OR_V(0) | BG_B_OR_U(0) | BG_G_OR_Y(0) | BG_ENABLE(1));
else
rk628_i2c_write(rk628, GRF_BG_CTRL,
BG_R_OR_V(512) | BG_B_OR_U(512) | BG_G_OR_Y(64) | BG_ENABLE(1));
return;
}
rk628_i2c_write(rk628, GRF_BG_CTRL, BG_ENABLE(0));

1
drivers/media/i2c/rk628/rk628_hdmirx.h
View File

@@ -389,6 +389,7 @@
#define RK628_CSI_LINK_FREQ_LOW 350000000
#define RK628_CSI_LINK_FREQ_HIGH 650000000
#define RK628_CSI_LINK_FREQ_925M 925000000
#define RK628_CSI_PIXEL_RATE_LOW 400000000
#define RK628_CSI_PIXEL_RATE_HIGH 600000000
#define MIPI_DATARATE_MBPS_LOW 700

31
drivers/media/i2c/rk628/rk628_post_process.c
View File

@@ -6,6 +6,7 @@
#include "rk628.h"
#include "rk628_cru.h"
#include "rk628_hdmirx.h"
#include "rk628_post_process.h"
#include <linux/videodev2.h>
#define PQ_CSC_HUE_TABLE_NUM 256
@@ -1023,30 +1024,6 @@ static const struct csc_mapping csc_mapping_table[] = {
},
};
static const struct rk_pq_csc_coef r2y_for_y2y = {
306, 601, 117,
-151, -296, 446,
630, -527, -102,
};
static const struct rk_pq_csc_coef y2r_for_y2y = {
1024, -0, 1167,
1024, -404, -594,
1024, 2081, -1,
};
static const struct rk_pq_csc_coef rgb_input_swap_matrix = {
0, 0, 1,
1, 0, 0,
0, 1, 0,
};
static const struct rk_pq_csc_coef yuv_output_swap_matrix = {
0, 0, 1,
1, 0, 0,
0, 1, 0,
};
static bool is_rgb_format(u64 format)
{
switch (format) {
@@ -1108,10 +1085,8 @@ static int csc_get_mode_index(int post_csc_mode, bool is_input_yuv, bool is_outp
if (colorspace_info->input_color_space == input_color_space &&
colorspace_info->output_color_space == output_color_space &&
colorspace_info->in_full_range == is_input_full_range &&
colorspace_info->out_full_range == is_output_full_range) {
pr_info("RK628 find CSC mode: %s\n", g_mode_csc_coef[i].c_csc_comment);
colorspace_info->out_full_range == is_output_full_range)
return i;
}
}
return -EINVAL;
@@ -1327,7 +1302,7 @@ static void rk628_post_process_csc(struct rk628 *rk628)
int color_range;
in_fmt = rk628_hdmirx_get_format(rk628);
out_fmt = BUS_FMT_YUV422;
out_fmt = rk628->tx_mode ? BUS_FMT_RGB : BUS_FMT_YUV422;
if (rk628->version == RK628D_VERSION) {
if (in_fmt == BUS_FMT_RGB)