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drm/rockchip: add support vop3

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Rockchip VOP3 is new VOP architecture base on VOP2, compared to the
VOP2, the biggest change is VOP overlay and post process module.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I19ee4e91aa430ec8b80095702c697d08a696d52b
This commit is contained in:
Sandy Huang
2022-10-20 10:43:38 +08:00
committed by Tao Huang
parent fa0690beb7
commit a1be106ef0
3 changed files with 879 additions and 140 deletions
Download Patch File Download Diff File Expand all files Collapse all files

92
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -10,16 +10,24 @@
#include <drm/drm_plane.h>
#include <drm/drm_modes.h>
#include "rockchip_drm_drv.h"
/*
* major: IP major version, used for IP structure
* minor: big feature change under same structure
* build: RTL current SVN number
*/
#define VOP_VERSION(major, minor) ((major) << 8 | (minor))
#define VOP_MAJOR(version) ((version) >> 8)
#define VOP_MINOR(version) ((version) & 0xff)
#define VOP_VERSION_RK3568 VOP_VERSION(0x40, 0x15)
#define VOP_VERSION_RK3588 VOP_VERSION(0x40, 0x17)
#define VOP2_VERSION(major, minor, build) ((major) << 24 | (minor) << 16 | (build))
#define VOP2_MAJOR(version) (((version) >> 24) & 0xff)
#define VOP2_MINOR(version) (((version) >> 16) & 0xff)
#define VOP2_BUILD(version) ((version) & 0xffff)
#define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023)
#define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786)
#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0)
#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1)
@@ -60,6 +68,7 @@
*/
#define WIN_FEATURE_MIRROR BIT(6)
#define WIN_FEATURE_MULTI_AREA BIT(7)
#define WIN_FEATURE_Y2R_13BIT_DEPTH BIT(8)
#define VOP2_SOC_VARIANT 4
@@ -109,6 +118,13 @@ enum vop2_win_dly_mode {
VOP2_DLY_MODE_MAX,
};
enum vop3_esmart_lb_mode {
VOP3_ESMART_ONE_8K_MODE,
VOP3_ESMART_TWO_4K_MODE,
VOP3_ESMART_ONE_4K_AND_TWO_2K_MODE,
VOP3_ESMART_FOUR_2K_MODE,
};
/*
* vop2 dsc id
*/
@@ -147,11 +163,18 @@ enum vop2_win_dly_mode {
#define DSP_RG_SWAP 0x4
#define DSP_DELTA_SWAP 0x8
#define V4L2_COLORSPACE_BT709F 0xfe
#define V4L2_COLORSPACE_BT2020F 0xff
enum vop_csc_format {
CSC_BT601L,
CSC_BT709L,
CSC_BT601F,
CSC_BT2020,
CSC_BT709L_13BIT,
CSC_BT709F_13BIT,
CSC_BT2020L_13BIT,
CSC_BT2020F_13BIT,
};
enum vop_csc_mode {
@@ -159,6 +182,11 @@ enum vop_csc_mode {
CSC_YUV,
};
enum vop_csc_bit_depth {
CSC_10BIT_DEPTH,
CSC_13BIT_DEPTH,
};
enum vop_data_format {
VOP_FMT_ARGB8888 = 0,
VOP_FMT_RGB888,
@@ -585,6 +613,11 @@ struct vop2_scl_regs {
struct vop_reg vsd_yrgb_gt2;
struct vop_reg vsd_yrgb_gt4;
struct vop_reg bic_coe_sel;
struct vop_reg xavg_en; /* supported from vop3 */
struct vop_reg xgt_en;
struct vop_reg xgt_mode;
struct vop_reg vsd_avg2;
struct vop_reg vsd_avg4;
};
struct vop2_win_regs {
@@ -595,7 +628,9 @@ struct vop2_win_regs {
struct vop_reg gate;
struct vop_reg enable;
struct vop_reg format;
struct vop_reg tile_mode;
struct vop_reg csc_mode;
struct vop_reg csc_13bit_en;
struct vop_reg xmirror;
struct vop_reg ymirror;
struct vop_reg rb_swap;
@@ -623,6 +658,7 @@ struct vop2_win_regs {
struct vop_reg axi_id;
struct vop_reg axi_yrgb_id;
struct vop_reg axi_uv_id;
struct vop_reg scale_engine_num;
};
struct vop2_video_port_regs {
@@ -697,6 +733,7 @@ struct vop2_video_port_regs {
struct vop_reg hdr_src_alpha_ctrl;
struct vop_reg hdr_dst_alpha_ctrl;
struct vop_reg bg_mix_ctrl;
struct vop_reg layer_sel;
/* BCSH */
struct vop_reg bcsh_brightness;
@@ -728,6 +765,20 @@ struct vop2_video_port_regs {
struct vop_reg edpi_wms_fs;
struct vop_reg gamma_update_en;
struct vop_reg lut_dma_rid;
/* MCU output */
struct vop_reg mcu_pix_total;
struct vop_reg mcu_cs_pst;
struct vop_reg mcu_cs_pend;
struct vop_reg mcu_rw_pst;
struct vop_reg mcu_rw_pend;
struct vop_reg mcu_clk_sel;
struct vop_reg mcu_hold_mode;
struct vop_reg mcu_frame_st;
struct vop_reg mcu_rs;
struct vop_reg mcu_bypass;
struct vop_reg mcu_type;
struct vop_reg mcu_rw_bypass_port;
};
struct vop2_power_domain_regs {
@@ -830,6 +881,8 @@ struct vop2_win_data {
uint8_t axi_id;
uint8_t axi_yrgb_id;
uint8_t axi_uv_id;
uint8_t scale_engine_num;
uint8_t possible_crtcs;
uint32_t base;
enum drm_plane_type type;
@@ -850,10 +903,12 @@ struct vop2_win_data {
const u8 hsd_filter_mode;
const u8 vsu_filter_mode;
const u8 vsd_filter_mode;
const u8 hsd_pre_filter_mode;
const u8 vsd_pre_filter_mode;
/**
* @layer_sel_id: defined by register OVERLAY_LAYER_SEL of VOP2
*/
int layer_sel_id;
const uint8_t layer_sel_id[ROCKCHIP_MAX_CRTC];
uint64_t feature;
unsigned int max_upscale_factor;
@@ -887,6 +942,18 @@ struct vop2_wb_data {
uint32_t fifo_depth;
};
struct vop3_ovl_mix_regs {
struct vop_reg src_color_ctrl;
struct vop_reg dst_color_ctrl;
struct vop_reg src_alpha_ctrl;
struct vop_reg dst_alpha_ctrl;
};
struct vop3_ovl_regs {
const struct vop3_ovl_mix_regs *layer_mix_regs;
const struct vop3_ovl_mix_regs *hdr_mix_regs;
};
struct vop2_video_port_data {
char id;
uint8_t splice_vp_id;
@@ -901,6 +968,7 @@ struct vop2_video_port_data {
const struct vop_intr *intr;
const struct vop_hdr_table *hdr_table;
const struct vop2_video_port_regs *regs;
const struct vop3_ovl_regs *ovl_regs;
};
struct vop2_layer_regs {
@@ -972,6 +1040,7 @@ struct vop2_ctrl {
struct vop_reg cfg_done_en;
struct vop_reg wb_cfg_done;
struct vop_reg auto_gating_en;
struct vop_reg aclk_pre_auto_gating_en;
struct vop_reg ovl_cfg_done_port;
struct vop_reg ovl_port_mux_cfg_done_imd;
struct vop_reg ovl_port_mux_cfg;
@@ -996,6 +1065,8 @@ struct vop2_ctrl {
struct vop_reg lvds1_en;
struct vop_reg bt656_en;
struct vop_reg bt1120_en;
struct vop_reg bt656_dclk_pol;
struct vop_reg bt1120_dclk_pol;
struct vop_reg dclk_pol;
struct vop_reg pin_pol;
struct vop_reg rgb_dclk_pol;
@@ -1065,10 +1136,16 @@ struct vop2_ctrl {
struct vop_reg pd_off_imd;
struct vop_reg otp_en;
struct vop_reg esmart_lb_mode;
struct vop_reg reg_done_frm;
struct vop_reg cfg_done;
};
struct vop_dump_regs {
uint32_t offset;
const char *name;
};
/**
* VOP2 data structe
*
@@ -1089,6 +1166,7 @@ struct vop2_data {
uint8_t nr_conns;
uint8_t nr_pds;
uint8_t nr_mem_pgs;
uint8_t esmart_lb_mode;
bool delayed_pd;
const struct vop_intr *axi_intr;
const struct vop2_ctrl *ctrl;
@@ -1108,6 +1186,8 @@ struct vop2_data {
const struct vop_grf_ctrl *grf;
const struct vop_grf_ctrl *vo0_grf;
const struct vop_grf_ctrl *vo1_grf;
const struct vop_dump_regs *dump_regs;
uint32_t dump_regs_size;
struct vop_rect max_input;
struct vop_rect max_output;
@@ -1279,6 +1359,12 @@ enum vop2_scale_down_mode {
VOP2_SCALE_DOWN_AVG,
};
enum vop3_pre_scale_down_mode {
VOP3_PRE_SCALE_UNSPPORT,
VOP3_PRE_SCALE_DOWN_GT,
VOP3_PRE_SCALE_DOWN_AVG,
};
enum dither_down_mode {
RGB888_TO_RGB565 = 0x0,
RGB888_TO_RGB666 = 0x1

849
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

File diff suppressed because it is too large Load Diff

78
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View File

@@ -1896,7 +1896,7 @@ static const struct vop2_win_data rk3568_vop_win_data[] = {
.formats = formats_for_smart,
.nformats = ARRAY_SIZE(formats_for_smart),
.format_modifiers = format_modifiers,
.layer_sel_id = 3,
.layer_sel_id = { 3, 3, 3, 0xff },
.supported_rotations = DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
@@ -1919,7 +1919,7 @@ static const struct vop2_win_data rk3568_vop_win_data[] = {
.nformats = ARRAY_SIZE(formats_for_smart),
.format_modifiers = format_modifiers,
.base = 0x600,
.layer_sel_id = 7,
.layer_sel_id = { 7, 7, 7, 0xff },
.supported_rotations = DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
@@ -1942,7 +1942,7 @@ static const struct vop2_win_data rk3568_vop_win_data[] = {
.nformats = ARRAY_SIZE(formats_for_rk356x_esmart),
.format_modifiers = format_modifiers,
.base = 0x200,
.layer_sel_id = 6,
.layer_sel_id = { 6, 6, 6, 0xff },
.supported_rotations = DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
@@ -1965,7 +1965,7 @@ static const struct vop2_win_data rk3568_vop_win_data[] = {
.nformats = ARRAY_SIZE(formats_for_rk356x_esmart),
.format_modifiers = format_modifiers,
.base = 0x0,
.layer_sel_id = 2,
.layer_sel_id = { 2, 2, 2, 0xff },
.supported_rotations = DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
@@ -1988,7 +1988,7 @@ static const struct vop2_win_data rk3568_vop_win_data[] = {
.formats = formats_for_cluster,
.nformats = ARRAY_SIZE(formats_for_cluster),
.format_modifiers = format_modifiers_afbc_no_linear_mode,
.layer_sel_id = 0,
.layer_sel_id = { 0, 0, 0, 0xff },
.supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
@@ -2007,7 +2007,7 @@ static const struct vop2_win_data rk3568_vop_win_data[] = {
.name = "Cluster0-win1",
.phys_id = ROCKCHIP_VOP2_CLUSTER0,
.base = 0x80,
.layer_sel_id = -1,
.layer_sel_id = { 0xff, 0xff, 0xff, 0xff },
.formats = formats_for_cluster,
.nformats = ARRAY_SIZE(formats_for_cluster),
.format_modifiers = format_modifiers_afbc_no_linear_mode,
@@ -2030,7 +2030,7 @@ static const struct vop2_win_data rk3568_vop_win_data[] = {
.formats = formats_for_cluster,
.nformats = ARRAY_SIZE(formats_for_cluster),
.format_modifiers = format_modifiers_afbc_no_linear_mode,
.layer_sel_id = 1,
.layer_sel_id = { 1, 1, 1, 0xff },
.supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
@@ -2048,7 +2048,7 @@ static const struct vop2_win_data rk3568_vop_win_data[] = {
{
.name = "Cluster1-win1",
.phys_id = ROCKCHIP_VOP2_CLUSTER1,
.layer_sel_id = -1,
.layer_sel_id = { 0xff, 0xff, 0xff, 0xff },
.formats = formats_for_cluster,
.nformats = ARRAY_SIZE(formats_for_cluster),
.format_modifiers = format_modifiers_afbc_no_linear_mode,
@@ -2304,7 +2304,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.formats = formats_for_cluster,
.nformats = ARRAY_SIZE(formats_for_cluster),
.format_modifiers = format_modifiers_afbc,
.layer_sel_id = 0,
.layer_sel_id = { 0, 0, 0, 0 },
.supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
@@ -2327,7 +2327,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.name = "Cluster0-win1",
.phys_id = ROCKCHIP_VOP2_CLUSTER0,
.base = 0x80,
.layer_sel_id = -1,
.layer_sel_id = { 0xff, 0xff, 0xff, 0xff },
.formats = formats_for_cluster,
.nformats = ARRAY_SIZE(formats_for_cluster),
.format_modifiers = format_modifiers_afbc,
@@ -2353,7 +2353,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.formats = formats_for_cluster,
.nformats = ARRAY_SIZE(formats_for_cluster),
.format_modifiers = format_modifiers_afbc,
.layer_sel_id = 1,
.layer_sel_id = { 1, 1, 1, 1 },
.supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
@@ -2375,7 +2375,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
{
.name = "Cluster1-win1",
.phys_id = ROCKCHIP_VOP2_CLUSTER1,
.layer_sel_id = -1,
.layer_sel_id = { 0xff, 0xff, 0xff, 0xff },
.formats = formats_for_cluster,
.nformats = ARRAY_SIZE(formats_for_cluster),
.format_modifiers = format_modifiers_afbc,
@@ -2404,7 +2404,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.formats = formats_for_cluster,
.nformats = ARRAY_SIZE(formats_for_cluster),
.format_modifiers = format_modifiers_afbc,
.layer_sel_id = 4,
.layer_sel_id = { 4, 4, 4, 4 },
.supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
@@ -2425,7 +2425,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
{
.name = "Cluster2-win1",
.phys_id = ROCKCHIP_VOP2_CLUSTER2,
.layer_sel_id = -1,
.layer_sel_id = { 0xff, 0xff, 0xff, 0xff },
.formats = formats_for_cluster,
.nformats = ARRAY_SIZE(formats_for_cluster),
.format_modifiers = format_modifiers_afbc,
@@ -2453,7 +2453,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.formats = formats_for_cluster,
.nformats = ARRAY_SIZE(formats_for_cluster),
.format_modifiers = format_modifiers_afbc,
.layer_sel_id = 5,
.layer_sel_id = { 5, 5, 5, 5 },
.supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
@@ -2474,7 +2474,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
{
.name = "Cluster3-win1",
.phys_id = ROCKCHIP_VOP2_CLUSTER3,
.layer_sel_id = -1,
.layer_sel_id = { 0xff, 0xff, 0xff, 0xff },
.formats = formats_for_cluster,
.nformats = ARRAY_SIZE(formats_for_cluster),
.format_modifiers = format_modifiers_afbc,
@@ -2502,7 +2502,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.nformats = ARRAY_SIZE(formats_for_esmart),
.format_modifiers = format_modifiers,
.base = 0x0,
.layer_sel_id = 2,
.layer_sel_id = { 2, 2, 2, 2 },
.supported_rotations = DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
@@ -2530,7 +2530,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.formats = formats_for_esmart,
.nformats = ARRAY_SIZE(formats_for_esmart),
.format_modifiers = format_modifiers,
.layer_sel_id = 6,
.layer_sel_id = { 6, 6, 6, 6 },
.supported_rotations = DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
@@ -2557,7 +2557,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.nformats = ARRAY_SIZE(formats_for_esmart),
.format_modifiers = format_modifiers,
.base = 0x200,
.layer_sel_id = 3,
.layer_sel_id = { 3, 3, 3, 3 },
.supported_rotations = DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
@@ -2584,7 +2584,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.nformats = ARRAY_SIZE(formats_for_esmart),
.format_modifiers = format_modifiers,
.base = 0x600,
.layer_sel_id = 7,
.layer_sel_id = { 7, 7, 7, 7 },
.supported_rotations = DRM_MODE_REFLECT_Y,
.hsu_filter_mode = VOP2_SCALE_UP_BIC,
.hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
@@ -2769,6 +2769,40 @@ static const struct vop2_ctrl rk3588_vop_ctrl = {
.win_dly[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 24),
};
static const struct vop_dump_regs rk3568_dump_regs[] = {
{ RK3568_REG_CFG_DONE, "SYS" },
{ RK3568_OVL_CTRL, "OVL" },
{ RK3568_VP0_DSP_CTRL, "VP0" },
{ RK3568_VP1_DSP_CTRL, "VP1" },
{ RK3568_VP2_DSP_CTRL, "VP2" },
{ RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0" },
{ RK3568_CLUSTER1_WIN0_CTRL0, "Cluster1" },
{ RK3568_ESMART0_CTRL0, "Esmart0" },
{ RK3568_ESMART1_CTRL0, "Esmart1" },
{ RK3568_SMART0_CTRL0, "Smart0" },
{ RK3568_SMART1_CTRL0, "Smart1" },
{ RK3568_HDR_LUT_CTRL, "HDR" },
};
static const struct vop_dump_regs rk3588_dump_regs[] = {
{ RK3568_REG_CFG_DONE, "SYS" },
{ RK3568_OVL_CTRL, "OVL" },
{ RK3568_VP0_DSP_CTRL, "VP0" },
{ RK3568_VP1_DSP_CTRL, "VP1" },
{ RK3568_VP2_DSP_CTRL, "VP2" },
{ RK3588_VP3_DSP_CTRL, "VP3" },
{ RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0" },
{ RK3568_CLUSTER1_WIN0_CTRL0, "Cluster1" },
{ RK3588_CLUSTER2_WIN0_CTRL0, "Cluster2" },
{ RK3588_CLUSTER3_WIN0_CTRL0, "Cluster3" },
{ RK3568_ESMART0_CTRL0, "Esmart0" },
{ RK3568_ESMART1_CTRL0, "Esmart1" },
{ RK3568_SMART0_CTRL0, "Esmart2" },
{ RK3568_SMART1_CTRL0, "Esmart3" },
{ RK3568_HDR_LUT_CTRL, "HDR" },
};
static const struct vop2_data rk3568_vop = {
.version = VOP_VERSION_RK3568,
.nr_vps = 3,
@@ -2786,6 +2820,8 @@ static const struct vop2_data rk3568_vop = {
.layer = rk3568_vop_layers,
.win = rk3568_vop_win_data,
.win_size = ARRAY_SIZE(rk3568_vop_win_data),
.dump_regs = rk3568_dump_regs,
.dump_regs_size = ARRAY_SIZE(rk3568_dump_regs),
};
static const struct vop2_data rk3588_vop = {
@@ -2821,6 +2857,8 @@ static const struct vop2_data rk3588_vop = {
.nr_pds = ARRAY_SIZE(rk3588_vop_pd_data),
.mem_pg = rk3588_vop_mem_pg_data,
.nr_mem_pgs = ARRAY_SIZE(rk3588_vop_mem_pg_data),
.dump_regs = rk3588_dump_regs,
.dump_regs_size = ARRAY_SIZE(rk3588_dump_regs),
};
static const struct of_device_id vop2_dt_match[] = {