arm64: dts: ti: k3-j721s2-main: Add DSS node

Add DSS node for J721S2 SoC. DSS IP in J721S2 is
same as DSS IP in J721E, so same compatible is used.

Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com>
Link: https://lore.kernel.org/r/20230803081800.368582-2-j-choudhary@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Jayesh Choudhary
2023-08-03 13:47:59 +05:30
committed by Nishanth Menon
parent f6a5b65114
commit a1f62d114c

View File

@@ -1642,4 +1642,50 @@
clocks = <&k3_clks 346 1>;
status = "disabled";
};
dss: dss@4a00000 {
compatible = "ti,j721e-dss";
reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
<0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
<0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
<0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
<0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
<0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
<0x00 0x04a50000 0x00 0x10000>, /* vid1 */
<0x00 0x04a60000 0x00 0x10000>, /* vid2 */
<0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
<0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
<0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
<0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
<0x00 0x04a80000 0x00 0x10000>, /* vp1 */
<0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
<0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
<0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
<0x00 0x04af0000 0x00 0x10000>; /* wb */
reg-names = "common_m", "common_s0",
"common_s1", "common_s2",
"vidl1", "vidl2","vid1","vid2",
"ovr1", "ovr2", "ovr3", "ovr4",
"vp1", "vp2", "vp3", "vp4",
"wb";
clocks = <&k3_clks 158 0>,
<&k3_clks 158 2>,
<&k3_clks 158 5>,
<&k3_clks 158 14>,
<&k3_clks 158 18>;
clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common_m",
"common_s0",
"common_s1",
"common_s2";
status = "disabled";
dss_ports: ports {
};
};
};