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rk3128-box: arm->1.2g, gpu=480M.

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This commit is contained in:
li bing
2014-09-01 19:57:51 +08:00
parent b8f51762c6
commit a252597701
1 changed files with 64 additions and 62 deletions
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126
arch/arm/boot/dts/rk3128-box.dts
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@@ -53,75 +53,77 @@
};
&clk_core_dvfs_table {
operating-points = <
/* KHz uV */
/*408000 1250000
600000 1250000
696000 1250000
*/
816000 1250000
1008000 1250000
>;
status="okay";
};
&clk_core_dvfs_table {
operating-points = <
/* KHz uV */
/*408000 1250000
600000 1250000
696000 1250000
*/
816000 1250000
1008000 1250000
1200000 1320000
>;
status="okay";
};
&clk_gpu_dvfs_table {
operating-points = <
/* KHz uV */
200000 1250000
300000 1250000
>;
status="okay";
};
&clk_gpu_dvfs_table {
operating-points = <
/* KHz uV */
200000 1250000
300000 1250000
480000 1250000
>;
status="okay";
};
&clk_ddr_dvfs_table {
operating-points = <
/* KHz uV */
200000 950000
300000 950000
400000 1000000
533000 1050000
>;
&clk_ddr_dvfs_table {
operating-points = <
/* KHz uV */
200000 950000
300000 950000
400000 1000000
533000 1050000
>;
freq-table = <
/*status freq(KHz)*/
SYS_STATUS_NORMAL 533000
SYS_STATUS_SUSPEND 200000
/*
SYS_STATUS_VIDEO_1080P 240000
SYS_STATUS_VIDEO_4K 400000
SYS_STATUS_PERFORMANCE 528000
SYS_STATUS_DUALVIEW 400000
SYS_STATUS_BOOST 324000
SYS_STATUS_ISP 533000
*/
>;
auto-freq-table = <
240000
324000
396000
528000
>;
auto-freq=<0>;
status="okay";
};
freq-table = <
/*status freq(KHz)*/
SYS_STATUS_NORMAL 533000
SYS_STATUS_SUSPEND 200000
/*
SYS_STATUS_VIDEO_1080P 240000
SYS_STATUS_VIDEO_4K 400000
SYS_STATUS_PERFORMANCE 528000
SYS_STATUS_DUALVIEW 400000
SYS_STATUS_BOOST 324000
SYS_STATUS_ISP 533000
*/
>;
auto-freq-table = <
240000
324000
396000
528000
>;
auto-freq=<0>;
status="okay";
};
&pwm_regulator1 {
status = "okay";
};
&pwm_regulator1 {
status = "okay";
};
&pwm_regulator2 {
status = "okay";
};
&pwm_regulator2 {
status = "okay";
};
&pwm1 {
status = "okay";
};
&pwm1 {
status = "okay";
};
&uart1{
status = "okay";
dma-names = "!tx", "!rx";
&uart1{
status = "okay";
dma-names = "!tx", "!rx";
pinctrl-0 = <&uart1_xfer &uart1_cts>;
};