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ARM: dts: rk3366: add smart card reader controller's resource define.

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Change-Id: Icb21dc6b529e2791414f19a915085437332736df
Signed-off-by: Aiyoujun <ayj@rock-chips.com>
This commit is contained in:
Aiyoujun
2016-03-18 17:04:15 +08:00
committed by Huang, Tao
parent 1834384898
commit a26bf0123e
1 changed files with 35 additions and 0 deletions
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35
arch/arm64/boot/dts/rockchip/rk3366.dtsi
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@@ -227,6 +227,19 @@
status = "disabled";
};
scr: rkscr@ff1d0000 {
compatible = "rockchip-scr";
reg = <0x0 0xff1d0000 0x0 0x10000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>;
clocks = <&cru PCLK_SIM>;
clock-names = "g_pclk_sim_card";
status = "disabled";
};
sdmmc: rksdmmc@ff400000 {
compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
@@ -1245,6 +1258,28 @@
};
};
scr {
scr_clk: scr-clk {
rockchip,pins =
<5 8 RK_FUNC_2 &pcfg_pull_none>;
};
scr_io: scr-io {
rockchip,pins =
<5 9 RK_FUNC_2 &pcfg_pull_up>;
};
scr_rst: scr-rst {
rockchip,pins =
<5 10 RK_FUNC_1 &pcfg_pull_none>;
};
scr_detect: scr-detect {
rockchip,pins =
<5 11 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins =