shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 19:30:30 +09:00
Code Issues Packages Projects Releases Wiki Activity

Merge tag 'v5.17-next-soc.2' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers

Browse Source 
mmsys: fix compilation by adding SW reset infrastructure

* tag 'v5.17-next-soc.2' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data

Link: https://lore.kernel.org/r/e1b90372-a041-db6e-f35a-d17b26069e40@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2022-03-07 23:47:47 +01:00
parent 4d558d4d88 62dc30150c
commit a2d266a8f1
3 changed files with 7 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/soc/mediatek/mt8183-mmsys.h
View File

@@ -25,6 +25,8 @@
#define MT8183_RDMA0_SOUT_COLOR0 0x1
#define MT8183_RDMA1_SOUT_DSI0 0x1
#define MT8183_MMSYS_SW0_RST_B 0x140
static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,

6
drivers/soc/mediatek/mtk-mmsys.c
View File

@@ -49,12 +49,14 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.clk_driver = "clk-mt8173-mm",
.routes = mmsys_default_routing_table,
.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
.routes = mmsys_mt8183_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
};
static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
@@ -129,14 +131,14 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
spin_lock_irqsave(&mmsys->lock, flags);
reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B);
reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset);
if (assert)
reg &= ~BIT(id);
else
reg |= BIT(id);
writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B);
writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset);
spin_unlock_irqrestore(&mmsys->lock, flags);

3
drivers/soc/mediatek/mtk-mmsys.h
View File

@@ -78,8 +78,6 @@
#define DSI_SEL_IN_RDMA 0x1
#define DSI_SEL_IN_MASK 0x1
#define MMSYS_SW0_RST_B 0x140
struct mtk_mmsys_routes {
u32 from_comp;
u32 to_comp;
@@ -92,6 +90,7 @@ struct mtk_mmsys_driver_data {
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
const u16 sw0_rst_offset;
};
/*