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Merge commit '542f25b9ec2f03cf1f4ea5f0556430ab26934924'
* commit '542f25b9ec2f03cf1f4ea5f0556430ab26934924': Revert "dt-bindings: add binding document for Rockchip cpu avs" drm/rockchip: vop: correct RK3288/RK3399 VOP WIN register fields arm64: dts: rockchip: px30-android: add debug support spi: rockchip: Support DMA burst 16 arm64: configs: rockchip_defconfig: enable CONFIG_SND_SOC_ROCKCHIP_SPI_CODEC arm64: dts: rockchip: rk3588-vehicle-evb: use a spi-codec driver for the remote adsp Change-Id: I6d23398ae8c2ef4bee13b1b7f2965405d393193a
This commit is contained in:
@@ -1,50 +0,0 @@
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Rockchip cpu avs device tree bindings
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-------------------------------------
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Under the same frequency, the operating voltage tends to decrease with
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increasing leakage. so it is necessary to adjust opp's voltage according
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to leakage for power.
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Required properties:
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- cluster-id: At runtime, the platform can find a cpu's cluster_id
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according to it's cpu_id and match cluster-id property.
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- min-volt: The minimum voltage in uV. Even though opp's voltage will be
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adjusted, it must be bigger than or equal to the minimum.
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- min-freq: The minimum frequency in KHz. If an opp's frequency is bigger
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than or equal to the minimum, its volatge will be adjusted.
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- leakage-adjust-volt: The property is an array of 3-tuples items, and
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each item consists of leakage and voltage like
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<min-leakage-mA max-leakage-mA volt-uV>.
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min-leakage: minimum leakage in mA, ranges from 0 to 254.
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max-leakage: maximum leakage in mA, ranges from 0 to 254.
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volt: voltage offset in uV to apply to the opp table entries.
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- nvmem-cells: A phandle to the leakage data provided by efuse.
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- nvmem-cell-names: Should be "cpu_leakage".
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Example:
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cpu_avs: cpu-avs {
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cluster0-avs {
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cluster-id = <0>;
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min-volt = <800000>; /* uV */
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min-freq = <408000>; /* KHz */
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leakage-adjust-volt = <
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/* mA mA uV */
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0 254 0
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>;
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nvmem-cells = <&cpul_leakage>;
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nvmem-cell-names = "cpu_leakage";
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};
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cluster1-avs {
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cluster-id = <1>;
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min-volt = <800000>; /* uV */
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min-freq = <408000>; /* KHz */
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leakage-adjust-volt = <
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/* mA mA uV */
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0 254 0
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>;
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nvmem-cells = <&cpub_leakage>;
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nvmem-cell-names = "cpu_leakage";
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};
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};
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@@ -9,6 +9,14 @@
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bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 init=/init kpti=0";
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};
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debug: debug@ff690000 {
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compatible = "rockchip,debug";
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reg = <0x0 0xff690000 0x0 0x1000>,
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<0x0 0xff692000 0x0 0x1000>,
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<0x0 0xff694000 0x0 0x1000>,
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<0x0 0xff696000 0x0 0x1000>;
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};
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fiq-debugger {
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compatible = "rockchip,fiq-debugger";
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rockchip,serial-id = <2>;
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@@ -118,14 +118,6 @@
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status = "okay";
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};
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dummy_codec: dummy-codec {
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status = "okay";
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compatible = "rockchip,dummy-codec";
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#sound-dai-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&rk3308_reset>;
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};
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car_rk3308_sound: car-rk3308-sound {
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status = "okay";
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compatible = "simple-audio-card";
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@@ -140,7 +132,7 @@
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dai-tdm-slot-width = <32>;
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};
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codec_master: simple-audio-card,codec {
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sound-dai = <&dummy_codec>;
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sound-dai = <&spi_codec>;
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};
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};
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};
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@@ -326,6 +318,23 @@
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status = "disabled";
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};
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&spi4 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&spi4m0_cs1 &spi4m0_pins>;
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spi_codec: spi-codec@1 {
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compatible ="rockchip,spi-codec";
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reg = <1>;
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spi-lsb-first;
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spi-max-frequency = <5000000>;
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#sound-dai-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&rk3308_reset>;
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status = "okay";
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};
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};
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&uart9 {
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status = "okay";
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pinctrl-names = "default";
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@@ -130,14 +130,6 @@
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status = "okay";
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};
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dummy_codec: dummy-codec {
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status = "okay";
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compatible = "rockchip,dummy-codec";
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#sound-dai-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&rk3308_reset>;
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};
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car_rk3308_sound: car-rk3308-sound {
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status = "okay";
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compatible = "simple-audio-card";
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@@ -152,7 +144,7 @@
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dai-tdm-slot-width = <32>;
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};
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codec_master: simple-audio-card,codec {
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sound-dai = <&dummy_codec>;
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sound-dai = <&spi_codec>;
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};
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};
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};
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@@ -339,6 +331,23 @@
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status = "disabled";
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};
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&spi4 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&spi4m0_cs1 &spi4m0_pins>;
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spi_codec: spi-codec@1 {
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compatible ="rockchip,spi-codec";
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reg = <1>;
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spi-lsb-first;
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spi-max-frequency = <5000000>;
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#sound-dai-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&rk3308_reset>;
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status = "okay";
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};
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};
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&uart7 {
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/delete-property/ dmas;
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status = "okay";
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@@ -725,6 +725,7 @@ CONFIG_SND_SOC_RK3528=y
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CONFIG_SND_SOC_RK817=y
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CONFIG_SND_SOC_RK_CODEC_DIGITAL=y
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CONFIG_SND_SOC_RK_DSM=y
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CONFIG_SND_SOC_ROCKCHIP_SPI_CODEC=y
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CONFIG_SND_SOC_RT5640=y
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CONFIG_SND_SOC_RT5651=y
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CONFIG_SND_SOC_SPDIF=y
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@@ -194,7 +194,7 @@ static const struct vop_win_phy rk3288_win01_data = {
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.nformats = ARRAY_SIZE(formats_win_full_10bit),
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.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
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.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
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.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 4),
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.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
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.csc_mode = VOP_REG_VER(RK3288_WIN0_CTRL0, 0x3, 10, 3, 2, -1),
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.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
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.xmirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 21, 3, 2, -1),
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@@ -678,7 +678,7 @@ static const struct vop_win_phy rk3399_win01_data = {
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.nformats = ARRAY_SIZE(formats_win_full_10bit_yuyv),
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.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
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.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
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.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 4),
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.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
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.fmt_yuyv = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 17),
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.csc_mode = VOP_REG_VER(RK3288_WIN0_CTRL0, 0x3, 10, 3, 2, -1),
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.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
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@@ -478,8 +478,8 @@ static u32 rockchip_spi_calc_burst_size(u32 data_len)
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{
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u32 i;
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/* burst size: 1, 2, 4, 8 */
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for (i = 1; i < 8; i <<= 1) {
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/* burst size: 1, 2, 4, 8, 16 */
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for (i = 1; i < 16; i <<= 1) {
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if (data_len & i)
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break;
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}
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