Merge commit '542f25b9ec2f03cf1f4ea5f0556430ab26934924'

* commit '542f25b9ec2f03cf1f4ea5f0556430ab26934924':
  Revert "dt-bindings: add binding document for Rockchip cpu avs"
  drm/rockchip: vop: correct RK3288/RK3399 VOP WIN register fields
  arm64: dts: rockchip: px30-android: add debug support
  spi: rockchip: Support DMA burst 16
  arm64: configs: rockchip_defconfig: enable CONFIG_SND_SOC_ROCKCHIP_SPI_CODEC
  arm64: dts: rockchip: rk3588-vehicle-evb: use a spi-codec driver for the remote adsp

Change-Id: I6d23398ae8c2ef4bee13b1b7f2965405d393193a
This commit is contained in:
Tao Huang
2023-12-12 17:07:58 +08:00
7 changed files with 49 additions and 72 deletions

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@@ -1,50 +0,0 @@
Rockchip cpu avs device tree bindings
-------------------------------------
Under the same frequency, the operating voltage tends to decrease with
increasing leakage. so it is necessary to adjust opp's voltage according
to leakage for power.
Required properties:
- cluster-id: At runtime, the platform can find a cpu's cluster_id
according to it's cpu_id and match cluster-id property.
- min-volt: The minimum voltage in uV. Even though opp's voltage will be
adjusted, it must be bigger than or equal to the minimum.
- min-freq: The minimum frequency in KHz. If an opp's frequency is bigger
than or equal to the minimum, its volatge will be adjusted.
- leakage-adjust-volt: The property is an array of 3-tuples items, and
each item consists of leakage and voltage like
<min-leakage-mA max-leakage-mA volt-uV>.
min-leakage: minimum leakage in mA, ranges from 0 to 254.
max-leakage: maximum leakage in mA, ranges from 0 to 254.
volt: voltage offset in uV to apply to the opp table entries.
- nvmem-cells: A phandle to the leakage data provided by efuse.
- nvmem-cell-names: Should be "cpu_leakage".
Example:
cpu_avs: cpu-avs {
cluster0-avs {
cluster-id = <0>;
min-volt = <800000>; /* uV */
min-freq = <408000>; /* KHz */
leakage-adjust-volt = <
/* mA mA uV */
0 254 0
>;
nvmem-cells = <&cpul_leakage>;
nvmem-cell-names = "cpu_leakage";
};
cluster1-avs {
cluster-id = <1>;
min-volt = <800000>; /* uV */
min-freq = <408000>; /* KHz */
leakage-adjust-volt = <
/* mA mA uV */
0 254 0
>;
nvmem-cells = <&cpub_leakage>;
nvmem-cell-names = "cpu_leakage";
};
};

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@@ -9,6 +9,14 @@
bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 init=/init kpti=0";
};
debug: debug@ff690000 {
compatible = "rockchip,debug";
reg = <0x0 0xff690000 0x0 0x1000>,
<0x0 0xff692000 0x0 0x1000>,
<0x0 0xff694000 0x0 0x1000>,
<0x0 0xff696000 0x0 0x1000>;
};
fiq-debugger {
compatible = "rockchip,fiq-debugger";
rockchip,serial-id = <2>;

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@@ -118,14 +118,6 @@
status = "okay";
};
dummy_codec: dummy-codec {
status = "okay";
compatible = "rockchip,dummy-codec";
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&rk3308_reset>;
};
car_rk3308_sound: car-rk3308-sound {
status = "okay";
compatible = "simple-audio-card";
@@ -140,7 +132,7 @@
dai-tdm-slot-width = <32>;
};
codec_master: simple-audio-card,codec {
sound-dai = <&dummy_codec>;
sound-dai = <&spi_codec>;
};
};
};
@@ -326,6 +318,23 @@
status = "disabled";
};
&spi4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi4m0_cs1 &spi4m0_pins>;
spi_codec: spi-codec@1 {
compatible ="rockchip,spi-codec";
reg = <1>;
spi-lsb-first;
spi-max-frequency = <5000000>;
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&rk3308_reset>;
status = "okay";
};
};
&uart9 {
status = "okay";
pinctrl-names = "default";

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@@ -130,14 +130,6 @@
status = "okay";
};
dummy_codec: dummy-codec {
status = "okay";
compatible = "rockchip,dummy-codec";
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&rk3308_reset>;
};
car_rk3308_sound: car-rk3308-sound {
status = "okay";
compatible = "simple-audio-card";
@@ -152,7 +144,7 @@
dai-tdm-slot-width = <32>;
};
codec_master: simple-audio-card,codec {
sound-dai = <&dummy_codec>;
sound-dai = <&spi_codec>;
};
};
};
@@ -339,6 +331,23 @@
status = "disabled";
};
&spi4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi4m0_cs1 &spi4m0_pins>;
spi_codec: spi-codec@1 {
compatible ="rockchip,spi-codec";
reg = <1>;
spi-lsb-first;
spi-max-frequency = <5000000>;
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&rk3308_reset>;
status = "okay";
};
};
&uart7 {
/delete-property/ dmas;
status = "okay";

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@@ -725,6 +725,7 @@ CONFIG_SND_SOC_RK3528=y
CONFIG_SND_SOC_RK817=y
CONFIG_SND_SOC_RK_CODEC_DIGITAL=y
CONFIG_SND_SOC_RK_DSM=y
CONFIG_SND_SOC_ROCKCHIP_SPI_CODEC=y
CONFIG_SND_SOC_RT5640=y
CONFIG_SND_SOC_RT5651=y
CONFIG_SND_SOC_SPDIF=y

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@@ -194,7 +194,7 @@ static const struct vop_win_phy rk3288_win01_data = {
.nformats = ARRAY_SIZE(formats_win_full_10bit),
.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 4),
.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
.csc_mode = VOP_REG_VER(RK3288_WIN0_CTRL0, 0x3, 10, 3, 2, -1),
.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
.xmirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 21, 3, 2, -1),
@@ -678,7 +678,7 @@ static const struct vop_win_phy rk3399_win01_data = {
.nformats = ARRAY_SIZE(formats_win_full_10bit_yuyv),
.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 4),
.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
.fmt_yuyv = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 17),
.csc_mode = VOP_REG_VER(RK3288_WIN0_CTRL0, 0x3, 10, 3, 2, -1),
.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),

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@@ -478,8 +478,8 @@ static u32 rockchip_spi_calc_burst_size(u32 data_len)
{
u32 i;
/* burst size: 1, 2, 4, 8 */
for (i = 1; i < 8; i <<= 1) {
/* burst size: 1, 2, 4, 8, 16 */
for (i = 1; i < 16; i <<= 1) {
if (data_len & i)
break;
}