shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-06 19:08:57 +09:00
Code Issues Packages Projects Releases Wiki Activity

arm64: dts: rk3308: enable mclk calibration for i2s_8ch

Browse Source 
Change-Id: I16db1649523cc2132664c5f00c3bf8246a2d8800
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This commit is contained in:
Xing Zheng
2018-05-08 11:33:11 +08:00
committed by Tao Huang
parent d0b882b30f
commit a40cd969de
1 changed files with 36 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

44
arch/arm64/boot/dts/rockchip/rk3308.dtsi
View File

@@ -730,13 +730,20 @@
compatible = "rockchip,rk3308-i2s-tdm";
reg = <0x0 0xff300000 0x0 0x1000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_I2S0_8CH_TX>, <&cru SCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
clocks = <&cru SCLK_I2S0_8CH_TX>, <&cru SCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>,
<&cru SCLK_I2S0_8CH_TX_SRC>,
<&cru SCLK_I2S0_8CH_RX_SRC>,
<&cru PLL_VPLL0>,
<&cru PLL_VPLL1>;
clock-names = "mclk_tx", "mclk_rx", "hclk",
"mclk_tx_src", "mclk_rx_src",
"mclk_root0", "mclk_root1";
dmas = <&dmac1 0>, <&dmac1 1>;
dma-names = "tx", "rx";
resets = <&cru SRST_I2S0_8CH_TX_M>, <&cru SRST_I2S0_8CH_RX_M>;
reset-names = "tx-m", "rx-m";
rockchip,cru = <&cru>;
rockchip,mclk-calibrate;
pinctrl-names = "default";
pinctrl-0 = <&i2s_8ch_0_sclktx
&i2s_8ch_0_sclkrx
@@ -758,13 +765,20 @@
compatible = "rockchip,rk3308-i2s-tdm";
reg = <0x0 0xff310000 0x0 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_I2S1_8CH_TX>, <&cru SCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
clocks = <&cru SCLK_I2S1_8CH_TX>, <&cru SCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>,
<&cru SCLK_I2S1_8CH_TX_SRC>,
<&cru SCLK_I2S1_8CH_RX_SRC>,
<&cru PLL_VPLL0>,
<&cru PLL_VPLL1>;
clock-names = "mclk_tx", "mclk_rx", "hclk",
"mclk_tx_src", "mclk_rx_src",
"mclk_root0", "mclk_root1";
dmas = <&dmac1 2>, <&dmac1 3>;
dma-names = "tx", "rx";
resets = <&cru SRST_I2S1_8CH_TX_M>, <&cru SRST_I2S1_8CH_RX_M>;
reset-names = "tx-m", "rx-m";
rockchip,cru = <&cru>;
rockchip,mclk-calibrate;
status = "disabled";
};
@@ -772,13 +786,20 @@
compatible = "rockchip,rk3308-i2s-tdm";
reg = <0x0 0xff320000 0x0 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_I2S2_8CH_TX>, <&cru SCLK_I2S2_8CH_RX>, <&cru HCLK_I2S2_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
clocks = <&cru SCLK_I2S2_8CH_TX>, <&cru SCLK_I2S2_8CH_RX>, <&cru HCLK_I2S2_8CH>,
<&cru SCLK_I2S2_8CH_TX_SRC>,
<&cru SCLK_I2S2_8CH_RX_SRC>,
<&cru PLL_VPLL0>,
<&cru PLL_VPLL1>;
clock-names = "mclk_tx", "mclk_rx", "hclk",
"mclk_tx_src", "mclk_rx_src",
"mclk_root0", "mclk_root1";
dmas = <&dmac1 4>, <&dmac1 5>;
dma-names = "tx", "rx";
resets = <&cru SRST_I2S2_8CH_TX_M>, <&cru SRST_I2S2_8CH_RX_M>;
reset-names = "tx-m", "rx-m";
rockchip,cru = <&cru>;
rockchip,mclk-calibrate;
status = "disabled";
};
@@ -786,13 +807,20 @@
compatible = "rockchip,rk3308-i2s-tdm";
reg = <0x0 0xff330000 0x0 0x1000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_I2S3_8CH_TX>, <&cru SCLK_I2S3_8CH_RX>, <&cru HCLK_I2S3_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
clocks = <&cru SCLK_I2S3_8CH_TX>, <&cru SCLK_I2S3_8CH_RX>, <&cru HCLK_I2S3_8CH>,
<&cru SCLK_I2S3_8CH_TX_SRC>,
<&cru SCLK_I2S3_8CH_RX_SRC>,
<&cru PLL_VPLL0>,
<&cru PLL_VPLL1>;
clock-names = "mclk_tx", "mclk_rx", "hclk",
"mclk_tx_src", "mclk_rx_src",
"mclk_root0", "mclk_root1";
dmas = <&dmac1 7>;
dma-names = "rx";
resets = <&cru SRST_I2S3_8CH_TX_M>, <&cru SRST_I2S3_8CH_RX_M>;
reset-names = "tx-m", "rx-m";
rockchip,cru = <&cru>;
rockchip,mclk-calibrate;
status = "disabled";
};