arm64: dts: rockchip: rk3588: Add pcie1ln setting for comboPHY

The controller must route to the comboPHY when it works.

pcie1l0_sel
Select the signal form PHY to PCIe1l0
1'b0: Select comb PHY
1'b1: Select PCIE3 PHY

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I5e7faf71fdd22958c757f884f75ec9a00aeb2fb9
This commit is contained in:
Kever Yang
2021-11-14 21:29:43 +08:00
committed by Tao Huang
parent e984bc2a96
commit a44f986d11
2 changed files with 2 additions and 0 deletions

View File

@@ -687,6 +687,7 @@
reset-names = "combphy-apb", "combphy";
rockchip,pipe-grf = <&php_grf>;
rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
rockchip,pcie1ln-sel-bits = <0x100 1 1 0>;
status = "disabled";
};

View File

@@ -3846,6 +3846,7 @@
reset-names = "combphy-apb", "combphy";
rockchip,pipe-grf = <&php_grf>;
rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
rockchip,pcie1ln-sel-bits = <0x100 0 0 0>;
status = "disabled";
};