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ASoC: rk1000_codec: fix coding style
Change-Id: I90bde35e48da9cba0d750866099491a9047d8972 Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This commit is contained in:
Sugar Zhang
@@ -1,85 +1,88 @@
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/*
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* rk1000_codec.h -- rk1000 ALSA Soc Audio driver
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*
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* Copyright (C) 2009 rockchip lhh
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* Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd All rights reserved.
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*
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* Based on WM8750.h
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#ifndef _RK1000_CODEC_H
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#define _RK1000_CODEC_H
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/* RK1000 register space */
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/* ADC High Pass Filter / DSM */
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#define ACCELCODEC_R00 0x00
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#define ACCELCODEC_R00 0x00
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/* DITHER power */
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#define ACCELCODEC_R01 0x01
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#define ACCELCODEC_R01 0x01
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/* DITHER power */
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#define ACCELCODEC_R02 0x02
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#define ACCELCODEC_R02 0x02
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/* DITHER power */
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#define ACCELCODEC_R03 0x03
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#define ACCELCODEC_R03 0x03
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/* Soft mute / sidetone gain control */
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#define ACCELCODEC_R04 0x04
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#define ACCELCODEC_R04 0x04
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/* Right interpolate filter volume control (MSB) */
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#define ACCELCODEC_R05 0x05
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#define ACCELCODEC_R05 0x05
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/* Right interpolate filter volume control (LSB) */
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#define ACCELCODEC_R06 0x06
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#define ACCELCODEC_R06 0x06
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/* Left interpolate filter volume control (MSB) */
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#define ACCELCODEC_R07 0x07
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#define ACCELCODEC_R07 0x07
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/* Left interpolate filter volume control (LSB) */
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#define ACCELCODEC_R08 0x08
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#define ACCELCODEC_R08 0x08
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/* Audio interface control */
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#define ACCELCODEC_R09 0x09
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#define ACCELCODEC_R09 0x09
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/* Sample Rate / CLK control */
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#define ACCELCODEC_R0A 0x0A
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#define ACCELCODEC_R0A 0x0A
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/* Decimation filter / Interpolate filter enable */
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#define ACCELCODEC_R0B 0x0B
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#define ACCELCODEC_R0B 0x0B
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/* LIN volume */
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#define ACCELCODEC_R0C 0x0C
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#define ACCELCODEC_R0C 0x0C
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/* LIP volume */
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#define ACCELCODEC_R0D 0x0D
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#define ACCELCODEC_R0D 0x0D
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/* AL volume */
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#define ACCELCODEC_R0E 0x0E
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#define ACCELCODEC_R0E 0x0E
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/* Input volume */
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#define ACCELCODEC_R12 0x12
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#define ACCELCODEC_R12 0x12
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/* Left out mix */
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#define ACCELCODEC_R13 0x13
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#define ACCELCODEC_R13 0x13
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/* Right out mix */
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#define ACCELCODEC_R14 0x14
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#define ACCELCODEC_R14 0x14
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/* LPF out mix / SCF */
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#define ACCELCODEC_R15 0x15
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#define ACCELCODEC_R15 0x15
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/* SCF control */
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#define ACCELCODEC_R16 0x16
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#define ACCELCODEC_R16 0x16
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/* LOUT (AOL) volume */
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#define ACCELCODEC_R17 0x17
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#define ACCELCODEC_R17 0x17
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/* ROUT (AOR) volume */
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#define ACCELCODEC_R18 0x18
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#define ACCELCODEC_R18 0x18
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/* MONOOUT (AOM) volume */
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#define ACCELCODEC_R19 0x19
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#define ACCELCODEC_R19 0x19
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/* MONOOUT / Reference control */
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#define ACCELCODEC_R1A 0x1A
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#define ACCELCODEC_R1A 0x1A
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/* Bias Current control */
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#define ACCELCODEC_R1B 0x1B
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#define ACCELCODEC_R1B 0x1B
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/* ADC control */
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#define ACCELCODEC_R1C 0x1C
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#define ACCELCODEC_R1C 0x1C
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/* Power Mrg 1 */
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#define ACCELCODEC_R1D 0x1D
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#define ACCELCODEC_R1D 0x1D
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/* Power Mrg 2 */
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#define ACCELCODEC_R1E 0x1E
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#define ACCELCODEC_R1E 0x1E
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/* Power Mrg 3 */
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#define ACCELCODEC_R1F 0x1F
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#define RK1000_CACHE_REGNUM 0x1F
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#define ACCELCODEC_R1F 0x1F
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/* ACCELCODEC_R00 */
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/* high_pass filter */
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#define ASC_HPF_ENABLE (0x1)
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#define ASC_HPF_DISABLE (0x0)
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#define ASC_HPF_ENABLE (0x1)
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#define ASC_HPF_DISABLE (0x0)
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#define ASC_DSM_MODE_ENABLE (0x1 << 1)
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#define ASC_DSM_MODE_DISABLE (0x0 << 1)
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@@ -90,14 +93,14 @@
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#define ASC_DITHER_ENABLE (0x1 << 3)
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#define ASC_DITHER_DISABLE (0x0 << 3)
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#define ASC_BCLKDIV_4 (0x1 << 4)
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#define ASC_BCLKDIV_8 (0x2 << 4)
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#define ASC_BCLKDIV_16 (0x3 << 4)
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#define ASC_BCLKDIV_4 (0x1 << 4)
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#define ASC_BCLKDIV_8 (0x2 << 4)
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#define ASC_BCLKDIV_16 (0x3 << 4)
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/* ACCECODEC_R04 */
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#define ASC_INT_MUTE_L (0x1)
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#define ASC_INT_MUTE_L (0x1)
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#define ASC_INT_ACTIVE_L (0x0)
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#define ASC_INT_MUTE_R (0x1 << 1)
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#define ASC_INT_MUTE_R (0x1 << 1)
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#define ASC_INT_ACTIVE_R (0x0 << 1)
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#define ASC_SIDETONE_L_OFF (0x0 << 2)
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@@ -105,21 +108,19 @@
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#define ASC_SIDETONE_R_OFF (0x0 << 5)
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#define ASC_SIDETONE_R_GAIN_MAX (0x1 << 5)
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/* ACCELCODEC_R05 */
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#define ASC_INT_VOL_0DB (0x0)
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#define ASC_INT_VOL_0DB (0x0)
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/* ACCELCODEC_R09 */
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#define ASC_DSP_MODE (0x3)
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#define ASC_I2S_MODE (0x2)
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#define ASC_LEFT_MODE (0x1)
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#define ASC_RIGHT_MODE (0x0)
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#define ASC_DSP_MODE (0x3)
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#define ASC_I2S_MODE (0x2)
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#define ASC_LEFT_MODE (0x1)
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#define ASC_RIGHT_MODE (0x0)
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#define ASC_32BIT_MODE (0x3 << 2)
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#define ASC_24BIT_MODE (0x2 << 2)
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#define ASC_20BIT_MODE (0x1 << 2)
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#define ASC_16BIT_MODE (0x0 << 2)
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#define ASC_32BIT_MODE (0x3 << 2)
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#define ASC_24BIT_MODE (0x2 << 2)
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#define ASC_20BIT_MODE (0x1 << 2)
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#define ASC_16BIT_MODE (0x0 << 2)
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#define ASC_INVERT_LRCLK (0x1 << 4)
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#define ASC_NORMAL_LRCLK (0x0 << 4)
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@@ -127,46 +128,35 @@
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#define ASC_LRSWAP_ENABLE (0x1 << 5)
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#define ASC_LRSWAP_DISABLE (0x0 << 5)
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#define ASC_MASTER_MODE (0x1 << 6)
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#define ASC_SLAVE_MODE (0x0 << 6)
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#define ASC_MASTER_MODE (0x1 << 6)
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#define ASC_SLAVE_MODE (0x0 << 6)
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#define ASC_INVERT_BCLK (0x1 << 7)
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#define ASC_NORMAL_BCLK (0x0 << 7)
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#define ASC_INVERT_BCLK (0x1 << 7)
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#define ASC_NORMAL_BCLK (0x0 << 7)
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/* ACCELCODEC_R0A */
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#define ASC_USB_MODE (0x1)
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#define ASC_NORMAL_MODE (0x0)
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#define ASC_USB_MODE (0x1)
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#define ASC_NORMAL_MODE (0x0)
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#define FREQ96kHz (0x0e << 1)
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#define FREQ48kHz (0x00 << 1)
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#define FREQ441kHz (0x11 << 1)
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#define FREQ32kHz (0x0c << 1)
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#define FREQ24kHz (0x1c << 1)
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#define FREQ2205kHz (0x1B << 1)
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#define FREQ16kHz (0x0a << 1)
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#define FREQ12kHz (0x08 << 1)
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#define FREQ11025kHz (0x19 << 1)
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#define FREQ8kHz (0x06<<1)
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#define ASC_CLKDIV2 (0x1 << 6)
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#define ASC_CLKNODIV (0x0 << 6)
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#define ASC_CLKDIV2 (0x1 << 6)
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#define ASC_CLKNODIV (0x0 << 6)
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#define ASC_CLK_ENABLE (0x1 << 7)
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#define ASC_CLK_DISABLE (0x0 << 7)
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#define ASC_CLK_ENABLE (0x1 << 7)
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#define ASC_CLK_DISABLE (0x0 << 7)
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/* ACCELCODEC_R0B */
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#define ASC_DEC_ENABLE (0x1)
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#define ASC_DEC_DISABLE (0x0)
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#define ASC_INT_ENABLE (0x1 << 1)
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#define ASC_INT_DISABLE (0x0 << 1)
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#define ASC_DEC_ENABLE (0x1)
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#define ASC_DEC_DISABLE (0x0)
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#define ASC_INT_ENABLE (0x1 << 1)
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#define ASC_INT_DISABLE (0x0 << 1)
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#define ASC_INPUT_MUTE (0x1 << 7)
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#define ASC_INPUT_MUTE (0x1 << 7)
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#define ASC_INPUT_ACTIVE (0x0 << 7)
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#define ASC_INPUT_VOL_0DB (0x0)
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/* ACCELCODEC_R12 */
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#define ASC_LINE_INPUT (0)
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#define ASC_MIC_INPUT (1 << 7)
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#define ASC_LINE_INPUT (0)
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#define ASC_MIC_INPUT (1 << 7)
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#define ASC_MIC_BOOST_0DB (0)
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#define ASC_MIC_BOOST_20DB (1 << 5)
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@@ -176,9 +166,9 @@
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/* the left channel PGA output is directly fed into the left mixer */
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#define ASC_LPGAMX_ENABLE (0x1 << 3)
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#define ASC_LPGAMX_DISABLE (0x0 << 3)
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#define ASC_ALMXVOL_0DB (0x5 << 4)
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#define ASC_ALMXVOL_0DB (0x5 << 4)
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/* the left second line input is directly fed into the left mixer */
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#define ASC_ALMX_ENABLE (0x1 << 7)
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#define ASC_ALMX_ENABLE (0x1 << 7)
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#define ASC_ALMX_DISABLE (0x0 << 7)
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/* ACCELCODEC_R14 */
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@@ -186,25 +176,24 @@
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/* the right channel PGA output is directly fed into the right mixer */
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#define ASC_RPGAMX_ENABLE (0x1 << 3)
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#define ASC_RPGAMX_DISABLE (0x0 << 3)
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#define ASC_ARMXVOL_0DB (0x5 << 4)
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#define ASC_ARMXVOL_0DB (0x5 << 4)
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/* the right second line input is directly fed into the right mixer */
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#define ASC_ARMX_ENABLE (0x1 << 7)
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#define ASC_ARMX_ENABLE (0x1 << 7)
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#define ASC_ARMX_DISABLE (0x0 << 7)
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/*ACCELCODEC_R15 */
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/*the left differential signal from DAC is directly fed into the left mixer*/
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#define ASC_LDAMX_ENABLE (0x1 << 2)
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#define ASC_LDAMX_DISABLE (0x0 << 2)
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/* the right differential signal from DAC is *
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* directly fed into the right mixer */
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/* the right differential signal --> the right mixer */
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#define ASC_RDAMX_ENABLE (0x1 << 3)
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#define ASC_RDAMX_DISABLE (0x0 << 3)
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/* the left channel LPF is mute */
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#define ASC_LSCF_MUTE (0x1 << 4)
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#define ASC_LSCF_ACTIVE (0x0 << 4)
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#define ASC_LSCF_MUTE (0x1 << 4)
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#define ASC_LSCF_ACTIVE (0x0 << 4)
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/* the right channel LPF is mute */
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#define ASC_RSCF_MUTE (0x1 << 5)
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#define ASC_RSCF_ACTIVE (0x0 << 5)
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#define ASC_RSCF_MUTE (0x1 << 5)
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#define ASC_RSCF_ACTIVE (0x0 << 5)
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/* the left channel LPF output is fed into the left into the mixer */
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#define ASC_LLPFMX_ENABLE (0x1 << 6)
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#define ASC_LLPFMX_DISABLE (0x0 << 6)
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@@ -213,7 +202,7 @@
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#define ASC_RLPFMX_DISABLE (0x0 << 7)
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/* ACCELCODEC_R17/R18 */
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#define ASC_OUTPUT_MUTE (0x1 << 6)
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#define ASC_OUTPUT_MUTE (0x1 << 6)
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#define ASC_OUTPUT_ACTIVE (0x0 << 6)
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#define ASC_CROSSZERO_EN (0x1 << 7)
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#define ASC_OUTPUT_VOL_0DB (0x0F)
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@@ -224,37 +213,37 @@
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/* ACCELCODEC_R1A */
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#define ASC_VMDSCL_SLOWEST (0x0 << 2)
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#define ASC_VMDSCL_SLOW (0x1 << 2)
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#define ASC_VMDSCL_FAST (0x2 << 2)
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#define ASC_VMDSCL_SLOW (0x1 << 2)
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#define ASC_VMDSCL_FAST (0x2 << 2)
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#define ASC_VMDSCL_FASTEST (0x3 << 2)
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#define ASC_MICBIAS_09 (0x1 << 4)
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#define ASC_MICBIAS_06 (0x0 << 4)
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#define ASC_MICBIAS_09 (0x1 << 4)
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#define ASC_MICBIAS_06 (0x0 << 4)
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/* the right channel LPF output is fed to mono PA */
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#define ASC_L2M_ENABLE (0x1 << 5)
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#define ASC_L2M_DISABLE (0x0 << 5)
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#define ASC_L2M_ENABLE (0x1 << 5)
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#define ASC_L2M_DISABLE (0x0 << 5)
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/* the left channel LPF output is fed to mono PA */
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#define ASC_R2M_ENABLE (0x1 << 6)
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#define ASC_R2M_DISABLE (0x0 << 6)
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#define ASC_R2M_ENABLE (0x1 << 6)
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#define ASC_R2M_DISABLE (0x0 << 6)
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/* the capless connection is enable */
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#define ASC_CAPLESS_ENABLE (0x1 << 7)
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#define ASC_CAPLESS_DISABLE (0x0 << 7)
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/* ACCELCODEC_R1C */
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/* the amplitude setting of the ASDM dither(div=vdd/48) */
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#define ASC_DITH_0_DIV (0x0 << 3)
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#define ASC_DITH_2_DIV (0x1 << 3)
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#define ASC_DITH_4_DIV (0x2 << 3)
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#define ASC_DITH_8_DIV (0x3 << 3)
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#define ASC_DITH_0_DIV (0x0 << 3)
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#define ASC_DITH_2_DIV (0x1 << 3)
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#define ASC_DITH_4_DIV (0x2 << 3)
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#define ASC_DITH_8_DIV (0x3 << 3)
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/* the ASDM dither is enabled */
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#define ASC_DITH_ENABLE (0x1 << 5)
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#define ASC_DITH_ENABLE (0x1 << 5)
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#define ASC_DITH_DISABLE (0x0 << 5)
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/* the ASDM DEM is enabled */
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#define ASC_DEM_ENABLE (0x1 << 7)
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#define ASC_DEM_DISABLE (0x0 << 7)
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#define ASC_DEM_ENABLE (0x1 << 7)
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#define ASC_DEM_DISABLE (0x0 << 7)
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/* ACCELCODEC_R1D */
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/* the VMID reference is powered down. VMID is connected to GND */
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@@ -307,7 +296,7 @@
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#define ASC_PDMICB_ENABLE (0x1 << 4)
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#define ASC_PDMICB_DISABLE (0x0 << 4)
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/* the left channel LPF is power down */
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#define ASC_PDIB_ENABLE (0x1 << 5)
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#define ASC_PDIB_ENABLE (0x1 << 5)
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#define ASC_PDIB_DISABLE (0x0 << 5)
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/* the mon mixer is power down */
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#define ASC_PDMIXM_ENABLE (0x1 << 6)
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@@ -320,12 +309,12 @@
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#define LINE_2_MIXER_GAIN (0x5)
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#define RK1000_CODEC_NUM_REG 0x20
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#define GPIO_HIGH 1
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#define GPIO_LOW 0
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#define GPIO_HIGH 1
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#define GPIO_LOW 0
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/* rk1000 ctl register */
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#define CODEC_CON 0x01
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#define CODEC_ON 0X00
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#define CODEC_OFF 0x0d
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#define CODEC_CON 0x01
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#define CODEC_ON 0X00
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#define CODEC_OFF 0x0d
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#endif
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