clk: rockchip: Fix up the pll setting to support px30 SoC.

add px30 registers offset.
add new pll type pll_px30 for px30 soc APLL.

Change-Id: I321ba0d8dd45b90260cc7f22030ce905949ff762
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

drivers/clk/rockchip/Makefile

@@ -12,6 +12,7 @@ obj-y	+= clk-muxgrf.o
 obj-y	+= clk-ddr.o
 obj-$(CONFIG_RESET_CONTROLLER)	+= softrst.o
 
+obj-y	+= clk-px30.o
 obj-y	+= clk-rk3036.o
 obj-y	+= clk-rk3128.o
 obj-y	+= clk-rk3188.o

drivers/clk/rockchip/clk-pll.c

@@ -421,12 +421,32 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
 	rockchip_rk3036_pll_get_params(pll, &cur);
 	cur.rate = 0;
 
+	if (pll->type == pll_px30) {
+		writel_relaxed(HIWORD_UPDATE(1, PX30_BOOST_RECOVERY_MASK,
+					     PX30_BOOST_RECOVERY_SHIFT),
+			       pll->reg_base + PX30_BOOST_BOOST_CON);
+		do {
+			ret = readl_relaxed(pll->reg_base +
+					    PX30_BOOST_FSM_STATUS);
+		} while (ret & PX30_BOOST_BUSY_STATE);
+		writel_relaxed(HIWORD_UPDATE(1, PX30_BOOST_SW_CTRL_MASK,
+					     PX30_BOOST_SW_CTRL_SHIFT) |
+			       HIWORD_UPDATE(1, PX30_BOOST_LOW_FREQ_EN_MASK,
+					     PX30_BOOST_LOW_FREQ_EN_SHIFT),
+			       pll->reg_base + PX30_BOOST_BOOST_CON);
+	}
+
 	cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
 	if (cur_parent == PLL_MODE_NORM) {
 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
 		rate_change_remuxed = 1;
 	}
 
+	/* set pll power down */
+	writel(HIWORD_UPDATE(1,
+			     RK3036_PLLCON1_PWRDOWN, 13),
+	       pll->reg_base + RK3036_PLLCON(1));
+
 	/* update pll values */
 	writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
 					  RK3036_PLLCON0_FBDIV_SHIFT) |
@@ -448,6 +468,16 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
 	pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT;
 	writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
 
+	if (pll->type == pll_px30) {
+		writel_relaxed(HIWORD_UPDATE(0, PX30_BOOST_LOW_FREQ_EN_MASK,
+					     PX30_BOOST_LOW_FREQ_EN_SHIFT),
+			       pll->reg_base + PX30_BOOST_BOOST_CON);
+	}
+
+	/* set pll power up */
+	writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 13),
+	       pll->reg_base + RK3036_PLLCON(1));
+
 	/* wait for the pll to lock */
 	ret = rockchip_pll_wait_lock(pll);
 	if (ret) {
@@ -459,6 +489,15 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
 	if (rate_change_remuxed)
 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 
+	if (pll->type == pll_px30) {
+		writel_relaxed(HIWORD_UPDATE(0, PX30_BOOST_RECOVERY_MASK,
+					     PX30_BOOST_RECOVERY_SHIFT),
+			       pll->reg_base + PX30_BOOST_BOOST_CON);
+		writel_relaxed(HIWORD_UPDATE(0, PX30_BOOST_SW_CTRL_MASK,
+					     PX30_BOOST_SW_CTRL_SHIFT),
+			       pll->reg_base + PX30_BOOST_BOOST_CON);
+	}
+
 	return ret;
 }
 
@@ -1303,7 +1342,8 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
 	pll_mux->lock = &ctx->lock;
 	pll_mux->hw.init = &init;
 
-	if (pll_type == pll_rk3036 ||
+	if (pll_type == pll_px30 ||
+	    pll_type == pll_rk3036 ||
 	    pll_type == pll_rk3066 ||
 	    pll_type == pll_rk3328 ||
 	    pll_type == pll_rk3366 ||
@@ -1355,6 +1395,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
 	}
 
 	switch (pll_type) {
+	case pll_px30:
 	case pll_rk3036:
 	case pll_rk3328:
 		if (!pll->rate_table)

drivers/clk/rockchip/clk.h

@@ -34,6 +34,45 @@ struct clk;
 #define HIWORD_UPDATE(val, mask, shift) \
 		((val) << (shift) | (mask) << ((shift) + 16))
 
+#define PX30_PLL_CON(x)			((x) * 0x4)
+#define PX30_CLKSEL_CON(x)		((x) * 0x4 + 0x100)
+#define PX30_CLKGATE_CON(x)		((x) * 0x4 + 0x200)
+#define PX30_GLB_SRST_FST		0xb8
+#define PX30_GLB_SRST_SND		0xbc
+#define PX30_SOFTRST_CON(x)		((x) * 0x4 + 0x300)
+#define PX30_MODE_CON			0xa0
+#define PX30_MISC_CON			0xa4
+#define PX30_SDMMC_CON0			0x380
+#define PX30_SDMMC_CON1			0x384
+#define PX30_SDIO_CON0			0x388
+#define PX30_SDIO_CON1			0x38c
+#define PX30_EMMC_CON0			0x390
+#define PX30_EMMC_CON1			0x394
+
+#define PX30_PMU_PLL_CON(x)		((x) * 0x4)
+#define PX30_PMU_CLKSEL_CON(x)		((x) * 0x4 + 0x40)
+#define PX30_PMU_CLKGATE_CON(x)		((x) * 0x4 + 0x58)
+#define PX30_PMU_MODE			0x0020
+
+#define PX30_BOOST_PLL_H_CON(x)		((x) * 0x4 + 0x8000)
+#define PX30_BOOST_CLK_CON		0x8008
+#define PX30_BOOST_BOOST_CON		0x800c
+#define PX30_BOOST_SWITCH_CNT		0x8010
+#define PX30_BOOST_HIGH_PERF_CNT0	0x8014
+#define PX30_BOOST_HIGH_PERF_CNT1	0x8018
+#define PX30_BOOST_STATIS_THRESHOLD	0x801c
+#define PX30_BOOST_SHORT_SWITCH_CNT	0x8020
+#define PX30_BOOST_SWITCH_THRESHOLD	0x8024
+#define PX30_BOOST_FSM_STATUS		0x8028
+#define PX30_BOOST_PLL_L_CON(x)		((x) * 0x4 + 0x802c)
+#define PX30_BOOST_RECOVERY_MASK	0x2
+#define PX30_BOOST_RECOVERY_SHIFT	1
+#define PX30_BOOST_SW_CTRL_MASK		0x4
+#define PX30_BOOST_SW_CTRL_SHIFT	2
+#define PX30_BOOST_LOW_FREQ_EN_MASK	0x8
+#define PX30_BOOST_LOW_FREQ_EN_SHIFT	3
+#define PX30_BOOST_BUSY_STATE		BIT(8)
+
 /* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */
 #define RK2928_PLL_CON(x)		((x) * 0x4)
 #define RK2928_MODE_CON		0x40
@@ -134,6 +173,7 @@ struct clk;
 #define RK3399_PMU_GATEDIS_CON(x)	((x) * 0x4 + 0x130)
 
 enum rockchip_pll_type {
+	pll_px30,
 	pll_rk3036,
 	pll_rk3066,
 	pll_rk3328,