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dt-bindings: usb: dwc3-xilinx: Convert USB DWC3 bindings
Convert USB DWC3 bindings to DT schema format using json-schema. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Manish Narani <manish.narani@xilinx.com> Link: https://lore.kernel.org/r/1638808021-26921-1-git-send-email-manish.narani@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Manish Narani
committed by
Greg Kroah-Hartman
Greg Kroah-Hartman
parent
856d362448
commit
a5b5b45fce
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Xilinx SuperSpeed DWC3 USB SoC controller
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Required properties:
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- compatible: May contain "xlnx,zynqmp-dwc3" or "xlnx,versal-dwc3"
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- reg: Base address and length of the register control block
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- clocks: A list of phandles for the clocks listed in clock-names
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- clock-names: Should contain the following:
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"bus_clk" Master/Core clock, have to be >= 125 MHz for SS
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operation and >= 60MHz for HS operation
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"ref_clk" Clock source to core during PHY power down
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- resets: A list of phandles for resets listed in reset-names
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- reset-names:
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"usb_crst" USB core reset
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"usb_hibrst" USB hibernation reset
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"usb_apbrst" USB APB reset
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Required child node:
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A child node must exist to represent the core DWC3 IP block. The name of
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the node is not important. The content of the node is defined in dwc3.txt.
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Optional properties for snps,dwc3:
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- dma-coherent: Enable this flag if CCI is enabled in design. Adding this
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flag configures Global SoC bus Configuration Register and
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Xilinx USB 3.0 IP - USB coherency register to enable CCI.
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- interrupt-names: Should contain the following:
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"dwc_usb3" USB gadget mode interrupts
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"otg" USB OTG mode interrupts
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"hiber" USB hibernation interrupts
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Example device node:
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usb@0 {
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#address-cells = <0x2>;
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#size-cells = <0x1>;
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compatible = "xlnx,zynqmp-dwc3";
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reg = <0x0 0xff9d0000 0x0 0x100>;
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clock-names = "bus_clk", "ref_clk";
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clocks = <&clk125>, <&clk125>;
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resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
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<&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
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<&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
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reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
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ranges;
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dwc3@fe200000 {
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compatible = "snps,dwc3";
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reg = <0x0 0xfe200000 0x40000>;
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interrupt-names = "dwc_usb3", "otg", "hiber";
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interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
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phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
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phy-names = "usb3-phy";
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dr_mode = "host";
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dma-coherent;
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};
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};
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131
Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
Normal file
131
Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx SuperSpeed DWC3 USB SoC controller
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maintainers:
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- Manish Narani <manish.narani@xilinx.com>
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properties:
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compatible:
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items:
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- enum:
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- xlnx,zynqmp-dwc3
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- xlnx,versal-dwc3
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reg:
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maxItems: 1
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"#address-cells":
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enum: [ 1, 2 ]
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"#size-cells":
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enum: [ 1, 2 ]
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ranges: true
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power-domains:
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description: specifies a phandle to PM domain provider node
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maxItems: 1
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clocks:
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description:
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A list of phandle and clock-specifier pairs for the clocks
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listed in clock-names.
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items:
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- description: Master/Core clock, has to be >= 125 MHz
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for SS operation and >= 60MHz for HS operation.
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- description: Clock source to core during PHY power down.
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clock-names:
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items:
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- const: bus_clk
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- const: ref_clk
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resets:
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description:
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A list of phandles for resets listed in reset-names.
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items:
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- description: USB core reset
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- description: USB hibernation reset
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- description: USB APB reset
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reset-names:
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items:
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- const: usb_crst
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- const: usb_hibrst
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- const: usb_apbrst
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phys:
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minItems: 1
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maxItems: 2
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phy-names:
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minItems: 1
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maxItems: 2
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items:
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enum:
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- usb2-phy
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- usb3-phy
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# Required child node:
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patternProperties:
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"^usb@[0-9a-f]+$":
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$ref: snps,dwc3.yaml#
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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- ranges
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- power-domains
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- clocks
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- clock-names
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- resets
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- reset-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
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#include <dt-bindings/power/xlnx-zynqmp-power.h>
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#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
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#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
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#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
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#include <dt-bindings/phy/phy.h>
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axi {
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#address-cells = <2>;
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#size-cells = <2>;
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usb@0 {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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compatible = "xlnx,zynqmp-dwc3";
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reg = <0x0 0xff9d0000 0x0 0x100>;
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clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
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clock-names = "bus_clk", "ref_clk";
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power-domains = <&zynqmp_firmware PD_USB_0>;
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resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
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<&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
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<&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
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reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
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phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
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phy-names = "usb3-phy";
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ranges;
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usb@fe200000 {
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compatible = "snps,dwc3";
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reg = <0x0 0xfe200000 0x0 0x40000>;
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interrupt-names = "host", "otg";
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interrupts = <0 65 4>, <0 69 4>;
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dr_mode = "host";
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dma-coherent;
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};
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};
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};
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