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clk: rockchip: add clock controller for rk1808

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Add the clock tree definition for the new rk1808 SoC.

Change-Id: I86e502b27e0695c77e9937dfd7cffa14b5711954
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2018-07-03 08:51:37 +08:00
committed by Tao Huang
parent b7a15f8858
commit a651a11d16
3 changed files with 28 additions and 3 deletions
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1
drivers/clk/rockchip/Makefile
View File

@@ -16,6 +16,7 @@ obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
obj-$(CONFIG_CPU_PX30) += clk-px30.o
obj-$(CONFIG_CPU_RV1108) += clk-rv1108.o
obj-$(CONFIG_CPU_RK1808) += clk-rk1808.o
obj-$(CONFIG_CPU_RK3036) += clk-rk3036.o
obj-$(CONFIG_CPU_RK312X) += clk-rk3128.o
obj-$(CONFIG_CPU_RK3188) += clk-rk3188.o

5
drivers/clk/rockchip/clk-rk1808.c
View File

@@ -122,7 +122,6 @@ static const struct rockchip_cpuclk_reg_data rk1808_cpuclk_data = {
.mux_core_main = 0,
.mux_core_shift = 6,
.mux_core_mask = 0x3,
.pll_name = "pll_apll",
};
PNAME(mux_pll_p) = { "xin24m", "xin32k"};
@@ -335,9 +334,9 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = {
/*
* Clock-Architecture Diagram 4
*/
COMPOSITE_NOGATE(0, "clk_npu_div", mux_gpll_cpll_p, CLK_KEEP_REQ_RATE,
COMPOSITE_NOGATE(0, "clk_npu_div", mux_gpll_cpll_p, CLK_KEEP_REQ_RATE | CLK_OPS_PARENT_ENABLE,
RK1808_CLKSEL_CON(1), 8, 2, MFLAGS, 0, 4, DFLAGS),
COMPOSITE_NOGATE_HALFDIV(0, "clk_npu_np5", mux_gpll_cpll_p, CLK_KEEP_REQ_RATE,
COMPOSITE_NOGATE_HALFDIV(0, "clk_npu_np5", mux_gpll_cpll_p, CLK_KEEP_REQ_RATE | CLK_OPS_PARENT_ENABLE,
RK1808_CLKSEL_CON(1), 10, 2, MFLAGS, 4, 4, DFLAGS),
MUX(0, "clk_npu_pre", mux_npu_p, CLK_SET_RATE_PARENT,
RK1808_CLKSEL_CON(1), 15, 1, MFLAGS),

25
drivers/clk/rockchip/clk.h
View File

@@ -87,6 +87,31 @@ struct clk;
#define RV1108_SDIO_CON1 0x1e4
#define RV1108_EMMC_CON0 0x1e8
#define RV1108_EMMC_CON1 0x1ec
/*
* register positions shared by RK1808 RK2928, RK3036,
* RK3066, RK3188 and RK3228
*/
#define RK1808_PLL_CON(x) ((x) * 0x4)
#define RK1808_MODE_CON 0xa0
#define RK1808_MISC_CON 0xa4
#define RK1808_MISC1_CON 0xa8
#define RK1808_GLB_SRST_FST 0xb8
#define RK1808_GLB_SRST_SND 0xbc
#define RK1808_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
#define RK1808_CLKGATE_CON(x) ((x) * 0x4 + 0x230)
#define RK1808_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
#define RK1808_SDMMC_CON0 0x380
#define RK1808_SDMMC_CON1 0x384
#define RK1808_SDIO_CON0 0x388
#define RK1808_SDIO_CON1 0x38c
#define RK1808_EMMC_CON0 0x390
#define RK1808_EMMC_CON1 0x394
#define RK1808_PMU_PLL_CON(x) ((x) * 0x4 + 0x4000)
#define RK1808_PMU_MODE_CON 0x4020
#define RK1808_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x4040)
#define RK1808_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x4080)
#define RK2928_PLL_CON(x) ((x) * 0x4)
#define RK2928_MODE_CON 0x40