rk30 hdmi: When system wake up from 2nd sleep mode, hdmi reg CSC_CONFIG1 value

is random, which will cause color space convertion mode is incorrect. Need to
set CSC_CONFIG1 to default value before configure color space convertion mode.
This commit is contained in:
Zheng Yang
2012-05-16 17:09:51 +08:00
parent 833908e0db
commit a68d826763
2 changed files with 7 additions and 7 deletions

View File

@@ -293,17 +293,14 @@ static char coeff_csc[][24] = {
static void rk30_hdmi_config_csc(struct rk30_hdmi_video_para *vpara)
{
int i, temp, mode;
int i, mode;
char *coeff = NULL;
if( ((vpara->input_color == VIDEO_INPUT_COLOR_RGB) && (vpara->output_color == VIDEO_OUTPUT_RGB444)) ||
((vpara->input_color == VIDEO_INPUT_COLOR_YCBCR) && (vpara->output_color != VIDEO_OUTPUT_RGB444) ))
{
HDMIWrReg(AV_CTRL2, v_CSC_ENABLE(0));
HDMIWrReg(CSC_CONFIG1, v_CSC_MODE(CSC_MODE_AUTO) | v_CSC_BRSWAP_DIABLE(1));
return;
}
switch(vpara->vic)
{
case HDMI_720x480i_60Hz_4_3:
@@ -333,7 +330,7 @@ static void rk30_hdmi_config_csc(struct rk30_hdmi_video_para *vpara)
coeff = coeff_csc[mode];
HDMIMskReg(temp, CSC_CONFIG1, m_CSC_MODE, v_CSC_MODE(CSC_MODE_MANUAL));
HDMIWrReg(CSC_CONFIG1, v_CSC_MODE(CSC_MODE_MANUAL) | v_CSC_BRSWAP_DIABLE(1));
for(i = 0; i < 24; i++)
HDMIWrReg(CSC_PARA_C0_H + i*4, coeff[i]);
@@ -341,7 +338,6 @@ static void rk30_hdmi_config_csc(struct rk30_hdmi_video_para *vpara)
HDMIWrReg(AV_CTRL2, v_CSC_ENABLE(1));
}
//int rk30_hdmi_config_video(int vic, int output_color, int output_mode)
int rk30_hdmi_config_video(struct rk30_hdmi_video_para *vpara)
{
int value;
@@ -565,6 +561,9 @@ int rk30_hdmi_removed(void)
HDMIWrReg(INTR_MASK2, 0);
HDMIWrReg(INTR_MASK3, 0);
HDMIWrReg(INTR_MASK4, 0);
// Disable color space convertion
HDMIWrReg(AV_CTRL2, v_CSC_ENABLE(0));
HDMIWrReg(CSC_CONFIG1, v_CSC_MODE(CSC_MODE_AUTO) | v_CSC_BRSWAP_DIABLE(1));
rk30_hdmi_set_pwr_mode(PWR_SAVE_MODE_A);
}
return HDMI_ERROR_SUCESS;

View File

@@ -140,6 +140,7 @@ enum{
#define CSC_PARA_C8_H 0xa0
#define CSC_PARA_C8_L 0xa4
#define CSC_PARA_C9_H 0xa8
#define CSC_PARA_C9_L 0xac
#define CSC_PARA_C10_H 0xac
#define CSC_PARA_C10_L 0xb4
#define CSC_PARA_C11_H 0xb8