shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-08 03:40:35 +09:00
Code Issues Packages Projects Releases Wiki Activity

hdmi: support 1440x2560p60hz modes [1/1]

Browse Source 
PD#IPTV-1032

Problem:
Need support 1440x2560p60hz

Solution:
Porting VESA code and 1440x2560p60hz

Verify:
g12b/w400

Change-Id: I3cf38bebc29b76aed50fe2ced7b47e27f2d1af06
Signed-off-by: Kaifu Hu <kaifu.hu@amlogic.com>
This commit is contained in:
Kaifu Hu
2019-01-10 15:14:49 +08:00
committed by Luan Yuan
parent b7f2091068
commit a6a0ef47b8
11 changed files with 3263 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1248
drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c
View File

File diff suppressed because it is too large Load Diff

288
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c
View File

@@ -121,7 +121,7 @@ static int Edid_DecodeHeader(struct hdmitx_info *info, unsigned char *buff)
return ret;
}
static void Edid_ParsingIDManufacturerName(struct rx_cap *pRxCap,
static void Edid_ParsingIDManufacturerName(struct rx_cap *pRXCap,
unsigned char *data)
{
int i;
@@ -141,7 +141,7 @@ static void Edid_ParsingIDManufacturerName(struct rx_cap *pRxCap,
|| ((brand[2] > 26) || (brand[2] == 0)))
return;
for (i = 0; i < 3; i++)
pRxCap->IDManufacturerName[i] = uppercase[brand[i] - 1];
pRXCap->IDManufacturerName[i] = uppercase[brand[i] - 1];
}
static void Edid_ParsingIDProductCode(struct rx_cap *pRXCap,
@@ -163,31 +163,109 @@ static void Edid_ParsingIDSerialNumber(struct rx_cap *pRXCap,
pRXCap->IDSerialNumber[i] = data[3-i];
}
static int Edid_find_name_block(unsigned char *data)
/* store the idx of vesa_timing[32], which is 0 */
static void store_vesa_idx(struct rx_cap *pRXCap, enum hdmi_vic vesa_timing)
{
int ret = 0;
int i;
for (i = 0; i < 3; i++) {
if (data[i])
return ret;
for (i = 0; i < VESA_MAX_TIMING; i++) {
if (!pRXCap->vesa_timing[i]) {
pRXCap->vesa_timing[i] = vesa_timing;
break;
}
if (pRXCap->vesa_timing[i] == vesa_timing)
break;
}
if (data[3] == 0xfc)
ret = 1;
return ret;
pr_info("hdmitx: reach vesa idx MAX\n");
}
static void Edid_ReceiverProductNameParse(struct rx_cap *pRxCap,
static void Edid_EstablishedTimings(struct rx_cap *pRXCap, unsigned char *data)
{
if (data[0] & (1 << 5))
store_vesa_idx(pRXCap, HDMIV_640x480p60hz);
if (data[0] & (1 << 0))
store_vesa_idx(pRXCap, HDMIV_800x600p60hz);
if (data[1] & (1 << 3))
store_vesa_idx(pRXCap, HDMIV_1024x768p60hz);
}
static void Edid_StandardTimingIII(struct rx_cap *pRXCap, unsigned char *data)
{
if (data[0] & (1 << 0))
store_vesa_idx(pRXCap, HDMIV_1152x864p75hz);
if (data[1] & (1 << 6))
store_vesa_idx(pRXCap, HDMIV_1280x768p60hz);
if (data[1] & (1 << 2))
store_vesa_idx(pRXCap, HDMIV_1280x960p60hz);
if (data[1] & (1 << 1))
store_vesa_idx(pRXCap, HDMIV_1280x1024p60hz);
if (data[2] & (1 << 7))
store_vesa_idx(pRXCap, HDMIV_1360x768p60hz);
if (data[2] & (1 << 1))
store_vesa_idx(pRXCap, HDMIV_1400x1050p60hz);
if (data[3] & (1 << 5))
store_vesa_idx(pRXCap, HDMIV_1680x1050p60hz);
if (data[3] & (1 << 2))
store_vesa_idx(pRXCap, HDMIV_1600x1200p60hz);
if (data[4] & (1 << 0))
store_vesa_idx(pRXCap, HDMIV_1920x1200p60hz);
}
static void calc_timing(unsigned char *data, struct vesa_standard_timing *t)
{
struct hdmi_format_para *para = NULL;
if ((data[0] < 2) && (data[1] < 2))
return;
t->hactive = (data[0] + 31) * 8;
switch ((data[1] >> 6) & 0x3) {
case 0:
t->vactive = t->hactive * 5 / 8;
break;
case 1:
t->vactive = t->hactive * 3 / 4;
break;
case 2:
t->vactive = t->hactive * 4 / 5;
break;
case 3:
default:
t->vactive = t->hactive * 9 / 16;
break;
}
t->hsync = (data[1] & 0x3f) + 60;
para = hdmi_get_vesa_paras(t);
if (para)
t->vesa_timing = para->vic;
}
static void Edid_StandardTiming(struct rx_cap *pRXCap, unsigned char *data,
int max_num)
{
int i;
struct vesa_standard_timing timing;
for (i = 0; i < max_num; i++) {
memset(&timing, 0, sizeof(struct vesa_standard_timing));
calc_timing(&data[i * 2], &timing);
if (timing.vesa_timing)
store_vesa_idx(pRXCap, timing.vesa_timing);
}
}
static void Edid_ReceiverProductNameParse(struct rx_cap *pRXCap,
unsigned char *data)
{
int i = 0;
/* some Display Product name end with 0x20, not 0x0a
*/
while ((data[i] != 0x0a) && (data[i] != 0x20) && (i < 13)) {
pRxCap->ReceiverProductName[i] = data[i];
pRXCap->ReceiverProductName[i] = data[i];
i++;
}
pRxCap->ReceiverProductName[i] = '\0';
pRXCap->ReceiverProductName[i] = '\0';
}
void Edid_DecodeStandardTiming(struct hdmitx_info *info,
@@ -1835,7 +1913,7 @@ int check_dvi_hdmi_edid_valid(unsigned char *buf)
return 1;
}
static void Edid_ManufactureDateParse(struct rx_cap *pRxCap,
static void Edid_ManufactureDateParse(struct rx_cap *pRXCap,
unsigned char *data)
{
if (data == NULL)
@@ -1848,20 +1926,20 @@ static void Edid_ManufactureDateParse(struct rx_cap *pRxCap,
* 0xff: model year is specified
*/
if ((data[0] == 0) || ((data[0] >= 0x37) && (data[0] <= 0xfe)))
pRxCap->manufacture_week = 0;
pRXCap->manufacture_week = 0;
else
pRxCap->manufacture_week = data[0];
pRXCap->manufacture_week = data[0];
/* year:
* 0x0~0xf: reserved
* 0x10~0xff: year of manufacture,
* or model year(if specified by week=0xff)
*/
pRxCap->manufacture_year =
pRXCap->manufacture_year =
(data[1] <= 0xf)?0:data[1];
}
static void Edid_VersionParse(struct rx_cap *pRxCap,
static void Edid_VersionParse(struct rx_cap *pRXCap,
unsigned char *data)
{
if (data == NULL)
@@ -1871,13 +1949,13 @@ static void Edid_VersionParse(struct rx_cap *pRxCap,
* 0x1: edid version 1
* 0x0,0x2~0xff: reserved
*/
pRxCap->edid_version = (data[0] == 0x1)?1:0;
pRXCap->edid_version = (data[0] == 0x1)?1:0;
/*
* 0x0~0x4: revision number
* 0x5~0xff: reserved
*/
pRxCap->edid_revision = (data[1] < 0x5)?data[1]:0;
pRXCap->edid_revision = (data[1] < 0x5)?data[1]:0;
}
static void Edid_PhyscialSizeParse(struct rx_cap *pRxCap,
@@ -2019,6 +2097,94 @@ static void rxlatency_to_vinfo(struct vinfo_s *info, struct rx_cap *rx)
info->rx_latency.i_aLatency = rx->i_aLatency;
}
static void Edid_Descriptor_PMT(struct rx_cap *pRXCap,
struct vesa_standard_timing *t, unsigned char *data)
{
struct hdmi_format_para *para = NULL;
t->tmds_clk = data[0] + (data[1] << 8);
t->hactive = data[2] + (((data[4] >> 4) & 0xf) << 8);
t->hblank = data[3] + ((data[4] & 0xf) << 8);
t->vactive = data[5] + (((data[7] >> 4) & 0xf) << 8);
t->vblank = data[6] + ((data[7] & 0xf) << 8);
para = hdmi_get_vesa_paras(t);
if (para && ((para->vic) < (HDMI_3840x2160p60_64x27 + 1))) {
pRXCap->native_VIC = para->vic;
pr_info("hdmitx: get PMT vic: %d\n", para->vic);
}
if (para && ((para->vic) >= HDMITX_VESA_OFFSET))
store_vesa_idx(pRXCap, para->vic);
}
static void Edid_Descriptor_PMT2(struct rx_cap *pRXCap,
struct vesa_standard_timing *t, unsigned char *data)
{
struct hdmi_format_para *para = NULL;
t->tmds_clk = data[0] + (data[1] << 8);
t->hactive = data[2] + (((data[4] >> 4) & 0xf) << 8);
t->hblank = data[3] + ((data[4] & 0xf) << 8);
t->vactive = data[5] + (((data[7] >> 4) & 0xf) << 8);
t->vblank = data[6] + ((data[7] & 0xf) << 8);
para = hdmi_get_vesa_paras(t);
if (para && ((para->vic) >= HDMITX_VESA_OFFSET))
store_vesa_idx(pRXCap, para->vic);
}
static void Edid_CVT_timing_3bytes(struct rx_cap *pRXCap,
struct vesa_standard_timing *t, const unsigned char *data)
{
struct hdmi_format_para *para = NULL;
t->hactive = ((data[0] + (((data[1] >> 4) & 0xf) << 8)) + 1) * 2;
switch ((data[1] >> 2) & 0x3) {
case 0:
t->vactive = t->hactive * 3 / 4;
break;
case 1:
t->vactive = t->hactive * 9 / 16;
break;
case 2:
t->vactive = t->hactive * 5 / 8;
break;
case 3:
default:
t->vactive = t->hactive * 3 / 5;
break;
}
switch ((data[2] >> 5) & 0x3) {
case 0:
t->hsync = 50;
break;
case 1:
t->hsync = 60;
break;
case 2:
t->hsync = 75;
break;
case 3:
default:
t->hsync = 85;
break;
}
para = hdmi_get_vesa_paras(t);
if (para)
t->vesa_timing = para->vic;
}
static void Edid_CVT_timing(struct rx_cap *pRXCap, unsigned char *data)
{
int i;
struct vesa_standard_timing t;
for (i = 0; i < 4; i++) {
memset(&t, 0, sizeof(struct vesa_standard_timing));
Edid_CVT_timing_3bytes(pRXCap, &t, &data[i * 3]);
if (t.vesa_timing)
store_vesa_idx(pRXCap, t.vesa_timing);
}
}
int hdmitx_edid_parse(struct hdmitx_dev *hdmitx_device)
{
unsigned char CheckSum;
@@ -2061,18 +2227,9 @@ int hdmitx_edid_parse(struct hdmitx_dev *hdmitx_device)
Edid_ParsingIDManufacturerName(&hdmitx_device->RXCap, &EDID_buf[8]);
Edid_ParsingIDProductCode(&hdmitx_device->RXCap, &EDID_buf[0x0A]);
Edid_ParsingIDSerialNumber(&hdmitx_device->RXCap, &EDID_buf[0x0C]);
idx[0] = EDID_DETAILED_TIMING_DES_BLOCK0_POS;
idx[1] = EDID_DETAILED_TIMING_DES_BLOCK1_POS;
idx[2] = EDID_DETAILED_TIMING_DES_BLOCK2_POS;
idx[3] = EDID_DETAILED_TIMING_DES_BLOCK3_POS;
for (i = 0; i < 4; i++) {
if ((EDID_buf[idx[i]]) && (EDID_buf[idx[i] + 1]))
Edid_DTD_parsing(pRXCap, &EDID_buf[idx[i]]);
if (Edid_find_name_block(&EDID_buf[idx[i]]))
Edid_ReceiverProductNameParse(&hdmitx_device->RXCap,
&EDID_buf[idx[i]+5]);
}
Edid_EstablishedTimings(&hdmitx_device->RXCap, &EDID_buf[0x23]);
Edid_StandardTiming(&hdmitx_device->RXCap, &EDID_buf[0x26], 8);
Edid_ManufactureDateParse(&hdmitx_device->RXCap, &EDID_buf[16]);
@@ -2173,6 +2330,44 @@ int hdmitx_edid_parse(struct hdmitx_dev *hdmitx_device)
pRXCap->preferred_mode = pRXCap->VIC[0];
}
idx[0] = EDID_DETAILED_TIMING_DES_BLOCK0_POS;
idx[1] = EDID_DETAILED_TIMING_DES_BLOCK1_POS;
idx[2] = EDID_DETAILED_TIMING_DES_BLOCK2_POS;
idx[3] = EDID_DETAILED_TIMING_DES_BLOCK3_POS;
for (i = 0; i < 4; i++) {
if ((EDID_buf[idx[i]]) && (EDID_buf[idx[i] + 1])) {
struct vesa_standard_timing t;
memset(&t, 0, sizeof(struct vesa_standard_timing));
if (i == 0)
Edid_Descriptor_PMT(pRXCap, &t,
&EDID_buf[idx[i]]);
if (i == 1)
Edid_Descriptor_PMT2(pRXCap, &t,
&EDID_buf[idx[i]]);
continue;
}
switch (EDID_buf[idx[i] + 3]) {
case TAG_STANDARD_TIMINGS:
Edid_StandardTiming(pRXCap, &EDID_buf[idx[i] + 5], 6);
break;
case TAG_CVT_TIMING_CODES:
Edid_CVT_timing(pRXCap, &EDID_buf[idx[i] + 6]);
break;
case TAG_ESTABLISHED_TIMING_III:
Edid_StandardTimingIII(pRXCap, &EDID_buf[idx[i] + 6]);
break;
case TAG_RANGE_LIMITS:
break;
case TAG_DISPLAY_PRODUCT_NAME_STRING:
Edid_ReceiverProductNameParse(pRXCap,
&EDID_buf[idx[i] + 5]);
break;
default:
break;
}
}
if (hdmitx_edid_search_IEEEOUI(&EDID_buf[128])) {
pRXCap->ieeeoui = HDMI_IEEEOUI;
pr_info(EDID "find IEEEOUT\n");
@@ -2238,6 +2433,8 @@ static struct dispmode_vic dispmode_vic_tab[] = {
{"1080p25hz", HDMI_1080p25},
{"1080p24hz", HDMI_1080p24},
{"1080p60hz", HDMI_1080p60},
{"2560x1080p50hz", HDMI_2560x1080p50_64x27},
{"2560x1080p60hz", HDMI_2560x1080p60_64x27},
{"2160p30hz", HDMI_4k2k_30},
{"2160p25hz", HDMI_4k2k_25},
{"2160p24hz", HDMI_4k2k_24},
@@ -2252,7 +2449,34 @@ static struct dispmode_vic dispmode_vic_tab[] = {
{"smpte60hz", HDMI_4096x2160p60_256x135},
{"2160p60hz", HDMI_4k2k_60},
{"2160p50hz", HDMI_4k2k_50},
{"640x480p60hz", HDMIV_640x480p60hz},
{"800x480p60hz", HDMIV_800x480p60hz},
{"800x600p60hz", HDMIV_800x600p60hz},
{"852x480p60hz", HDMIV_852x480p60hz},
{"854x480p60hz", HDMIV_854x480p60hz},
{"1024x600p60hz", HDMIV_1024x600p60hz},
{"1024x768p60hz", HDMIV_1024x768p60hz},
{"1152x864p75hz", HDMIV_1152x864p75hz},
{"1280x600p60hz", HDMIV_1280x600p60hz},
{"1280x768p60hz", HDMIV_1280x768p60hz},
{"1280x800p60hz", HDMIV_1280x800p60hz},
{"1280x960p60hz", HDMIV_1280x960p60hz},
{"1280x1024p60hz", HDMIV_1280x1024p60hz},
{"1280x1024", HDMIV_1280x1024p60hz}, /* alias of "1280x1024p60hz" */
{"1360x768p60hz", HDMIV_1360x768p60hz},
{"1366x768p60hz", HDMIV_1366x768p60hz},
{"1400x1050p60hz", HDMIV_1400x1050p60hz},
{"1440x900p60hz", HDMIV_1440x900p60hz},
{"1440x2560p60hz", HDMIV_1440x2560p60hz},
{"1600x900p60hz", HDMIV_1600x900p60hz},
{"1600x1200p60hz", HDMIV_1600x1200p60hz},
{"1680x1050p60hz", HDMIV_1680x1050p60hz},
{"1920x1200p60hz", HDMIV_1920x1200p60hz},
{"2160x1200p90hz", HDMIV_2160x1200p90hz},
{"2560x1080p60hz", HDMIV_2560x1080p60hz},
{"2560x1440p60hz", HDMIV_2560x1440p60hz},
{"2560x1600p60hz", HDMIV_2560x1600p60hz},
{"3440x1440p60hz", HDMIV_3440x1440p60hz},
};
int hdmitx_edid_VIC_support(enum hdmi_vic vic)

59
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c
View File

@@ -2153,6 +2153,8 @@ const char *disp_mode_t[] = {
"1080p50hz",
"1080p25hz",
"1080p24hz",
"2560x1080p50hz",
"2560x1080p60hz",
"2160p30hz",
"2160p25hz",
"2160p24hz",
@@ -2163,6 +2165,34 @@ const char *disp_mode_t[] = {
"smpte60hz",
"2160p50hz",
"2160p60hz",
/* VESA modes */
"640x480p60hz",
"800x480p60hz",
"800x600p60hz",
"852x480p60hz",
"854x480p60hz",
"1024x600p60hz",
"1024x768p60hz",
"1152x864p75hz",
"1280x600p60hz",
"1280x768p60hz",
"1280x800p60hz",
"1280x960p60hz",
"1280x1024p60hz",
"1360x768p60hz",
"1366x768p60hz",
"1400x1050p60hz",
"1440x900p60hz",
"1440x2560p60hz",
"1600x900p60hz",
"1600x1200p60hz",
"1680x1050p60hz",
"1920x1200p60hz",
"2160x1200p90hz",
"2560x1080p60hz",
"2560x1440p60hz",
"2560x1600p60hz",
"3440x1440p60hz",
NULL
};
@@ -2266,6 +2296,29 @@ static ssize_t show_preferred_mode(struct device *dev,
return pos;
}
/* cea_cap, a clone of disp_cap */
static ssize_t show_cea_cap(struct device *dev,
struct device_attribute *attr, char *buf)
{
return show_disp_cap(dev, attr, buf);
}
static ssize_t show_vesa_cap(struct device *dev,
struct device_attribute *attr, char *buf)
{
int i;
struct hdmi_format_para *para = NULL;
enum hdmi_vic *vesa_t = &hdmitx_device.RXCap.vesa_timing[0];
int pos = 0;
for (i = 0; vesa_t[i] && i < VESA_MAX_TIMING; i++) {
para = hdmi_get_fmt_paras(vesa_t[i]);
if (para && (para->vic >= HDMITX_VESA_OFFSET))
pos += snprintf(buf+pos, PAGE_SIZE, "%s\n", para->name);
}
return pos;
}
/**/
static int local_support_3dfp(enum hdmi_vic vic)
{
@@ -3488,6 +3541,8 @@ static DEVICE_ATTR(config, 0664, show_config, store_config);
static DEVICE_ATTR(debug, 0200, NULL, store_debug);
static DEVICE_ATTR(disp_cap, 0444, show_disp_cap, NULL);
static DEVICE_ATTR(preferred_mode, 0444, show_preferred_mode, NULL);
static DEVICE_ATTR(cea_cap, 0444, show_cea_cap, NULL);
static DEVICE_ATTR(vesa_cap, 0444, show_vesa_cap, NULL);
static DEVICE_ATTR(aud_cap, 0444, show_aud_cap, NULL);
static DEVICE_ATTR(hdr_cap, 0444, show_hdr_cap, NULL);
static DEVICE_ATTR(dv_cap, 0444, show_dv_cap, NULL);
@@ -4585,6 +4640,8 @@ static int amhdmitx_probe(struct platform_device *pdev)
ret = device_create_file(dev, &dev_attr_debug);
ret = device_create_file(dev, &dev_attr_disp_cap);
ret = device_create_file(dev, &dev_attr_preferred_mode);
ret = device_create_file(dev, &dev_attr_cea_cap);
ret = device_create_file(dev, &dev_attr_vesa_cap);
ret = device_create_file(dev, &dev_attr_disp_cap_3d);
ret = device_create_file(dev, &dev_attr_aud_cap);
ret = device_create_file(dev, &dev_attr_hdr_cap);
@@ -4687,6 +4744,8 @@ static int amhdmitx_remove(struct platform_device *pdev)
device_remove_file(dev, &dev_attr_debug);
device_remove_file(dev, &dev_attr_disp_cap);
device_remove_file(dev, &dev_attr_preferred_mode);
device_remove_file(dev, &dev_attr_cea_cap);
device_remove_file(dev, &dev_attr_vesa_cap);
device_remove_file(dev, &dev_attr_disp_cap_3d);
device_remove_file(dev, &dev_attr_hdr_cap);
device_remove_file(dev, &dev_attr_dv_cap);

326
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_video.c
View File

@@ -490,6 +490,325 @@ static struct hdmitx_vidpara hdmi_tx_video_params[] = {
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_2560x1080p50_64x27,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_2560x1080p60_64x27,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_640x480p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_4_3,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_800x480p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_800x600p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_4_3,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_854x480p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_852x480p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_1024x600p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_1024x768p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_4_3,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_1152x864p75hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_4_3,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_1280x600p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_1280x768p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_1280x800p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_1280x960p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_1280x1024p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_4_3,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_1360x768p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_1366x768p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_1400x1050p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_1440x900p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_1440x2560p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_1600x900p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_1600x1200p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_1680x1050p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_1920x1200p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_2160x1200p90hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_4_3,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_2560x1080p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_2560x1440p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_2560x1600p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_2560x1440p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
};
static struct hdmitx_vidpara *hdmi_get_video_param(
@@ -618,6 +937,12 @@ int hdmitx_set_display(struct hdmitx_dev *hdev, enum hdmi_vic VideoCode)
pr_info(VID "rx edid only support RGB format\n");
}
if (VideoCode >= HDMITX_VESA_OFFSET) {
hdev->para->cs = COLORSPACE_RGB444;
hdev->para->cd = COLORDEPTH_24B;
pr_info("hdmitx: VESA only support RGB format\n");
}
if (hdev->HWOp.SetDispMode(hdev) >= 0) {
/* HDMI CT 7-33 DVI Sink, no HDMI VSDB nor any
* other VSDB, No GB or DI expected
@@ -682,6 +1007,7 @@ static void hdmi_set_vend_spec_infofram(struct hdmitx_dev *hdev,
int i;
unsigned char VEN_DB[6];
unsigned char VEN_HB[3];
VEN_HB[0] = 0x81;
VEN_HB[1] = 0x01;
VEN_HB[2] = 0x5;

807
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c
View File

@@ -687,6 +687,787 @@ static const struct reg_s tvregs_4k2k_smpte_60hz[] = {
{P_ENCI_VIDEO_EN, 0},
{MREG_END_MARKER, 0},
};
static const struct reg_s tvregs_2560x1080p50hz[] = {
{P_ENCP_VIDEO_EN, 0},
{P_ENCI_VIDEO_EN, 0},
{P_VENC_DVI_SETTING, 0x000d},
{P_ENCP_VIDEO_MAX_PXCNT, 3299},
{P_ENCP_VIDEO_MAX_LNCNT, 1124},
{P_ENCP_VIDEO_HSPULS_BEGIN, 44},
{P_ENCP_VIDEO_HSPULS_END, 132},
{P_ENCP_VIDEO_HSPULS_SWITCH, 44},
{P_ENCP_VIDEO_HAVON_BEGIN, 192},
{P_ENCP_VIDEO_HAVON_END, 2751},
{P_ENCP_VIDEO_HSO_BEGIN, 0},
{P_ENCP_VIDEO_HSO_END, 44},
{P_ENCP_VIDEO_VSPULS_BEGIN, 220},
{P_ENCP_VIDEO_VSPULS_END, 2140},
{P_ENCP_VIDEO_VSPULS_BLINE, 0},
{P_ENCP_VIDEO_VSPULS_ELINE, 4},
{P_ENCP_VIDEO_EQPULS_BLINE, 0},
{P_ENCP_VIDEO_EQPULS_ELINE, 4},
{P_ENCP_VIDEO_VAVON_BLINE, 41},
{P_ENCP_VIDEO_VAVON_ELINE, 1120},
{P_ENCP_VIDEO_VSO_BEGIN, 79},
{P_ENCP_VIDEO_VSO_END, 79},
{P_ENCP_VIDEO_VSO_BLINE, 0},
{P_ENCP_VIDEO_VSO_ELINE, 5},
{P_ENCP_VIDEO_YFP1_HTIME, 271},
{P_ENCP_VIDEO_YFP2_HTIME, 2190},
{P_VENC_VIDEO_PROG_MODE, 0x100},
{P_ENCP_VIDEO_MODE, 0x4040},
{P_ENCP_VIDEO_MODE_ADV, 0x0018},
{P_ENCP_VIDEO_SYNC_MODE, 0x7},
{P_ENCP_VIDEO_YC_DLY, 0},
{P_ENCP_VIDEO_RGB_CTRL, 2},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCI_VIDEO_EN, 0},
{P_ENCP_VIDEO_EN, 1},
{MREG_END_MARKER, 0},
};
static const struct reg_s tvregs_2560x1080p60hz[] = {
{P_ENCP_VIDEO_EN, 0},
{P_ENCI_VIDEO_EN, 0},
{P_VENC_DVI_SETTING, 0x000d},
{P_ENCP_VIDEO_MAX_PXCNT, 2999},
{P_ENCP_VIDEO_MAX_LNCNT, 1099},
{P_ENCP_VIDEO_HSPULS_BEGIN, 44},
{P_ENCP_VIDEO_HSPULS_END, 132},
{P_ENCP_VIDEO_HSPULS_SWITCH, 44},
{P_ENCP_VIDEO_HAVON_BEGIN, 192},
{P_ENCP_VIDEO_HAVON_END, 2751},
{P_ENCP_VIDEO_HSO_BEGIN, 0},
{P_ENCP_VIDEO_HSO_END, 44},
{P_ENCP_VIDEO_VSPULS_BEGIN, 220},
{P_ENCP_VIDEO_VSPULS_END, 2140},
{P_ENCP_VIDEO_VSPULS_BLINE, 0},
{P_ENCP_VIDEO_VSPULS_ELINE, 4},
{P_ENCP_VIDEO_EQPULS_BLINE, 0},
{P_ENCP_VIDEO_EQPULS_ELINE, 4},
{P_ENCP_VIDEO_VAVON_BLINE, 16},
{P_ENCP_VIDEO_VAVON_ELINE, 1095},
{P_ENCP_VIDEO_VSO_BEGIN, 79},
{P_ENCP_VIDEO_VSO_END, 79},
{P_ENCP_VIDEO_VSO_BLINE, 0},
{P_ENCP_VIDEO_VSO_ELINE, 5},
{P_ENCP_VIDEO_YFP1_HTIME, 271},
{P_ENCP_VIDEO_YFP2_HTIME, 2190},
{P_VENC_VIDEO_PROG_MODE, 0x100},
{P_ENCP_VIDEO_MODE, 0x4040},
{P_ENCP_VIDEO_MODE_ADV, 0x0018},
{P_ENCP_VIDEO_SYNC_MODE, 0x7},
{P_ENCP_VIDEO_YC_DLY, 0},
{P_ENCP_VIDEO_RGB_CTRL, 2},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCI_VIDEO_EN, 0},
{P_ENCP_VIDEO_EN, 1},
{MREG_END_MARKER, 0},
};
static const struct reg_s tvregs_vesa_640x480p60hz[] = {
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0x31F,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x20C,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x90,},
{P_ENCP_VIDEO_HAVON_END, 0x30F,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x23,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x202,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0x60,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x2,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1,},
{P_ENCI_VIDEO_EN, 0,},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_800x600p60hz[] = {
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0x41F,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x273,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0xD8,},
{P_ENCP_VIDEO_HAVON_END, 0x3F7,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x1B,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x272,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0x80,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x4,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1,},
{P_ENCI_VIDEO_EN, 0,},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_800x480p60hz[] = {
{P_ENCP_VIDEO_EN, 0},
{P_ENCI_VIDEO_EN, 0},
{P_VENC_VDAC_SETTING, 0xff},
{P_ENCP_VIDEO_MODE, 0x4040},
{P_ENCP_VIDEO_MODE_ADV, 0x18},
{P_ENCP_VIDEO_MAX_PXCNT, 0x3DF},
{P_ENCP_VIDEO_MAX_LNCNT, 0x1F3},
{P_ENCP_VIDEO_HAVON_BEGIN, 0xA8},
{P_ENCP_VIDEO_HAVON_END, 0x3C7},
{P_ENCP_VIDEO_VAVON_BLINE, 0x11},
{P_ENCP_VIDEO_VAVON_ELINE, 0x1F0},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0},
{P_ENCP_VIDEO_HSO_END, 0x48},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E},
{P_ENCP_VIDEO_VSO_END, 0x32},
{P_ENCP_VIDEO_VSO_BLINE, 0x0},
{P_ENCP_VIDEO_VSO_ELINE, 0x7},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1},
{P_ENCI_VIDEO_EN, 0},
{MREG_END_MARKER, 0},
};
static const struct reg_s tvregs_vesa_852x480p60hz[] = {
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0x3B3,},/*947//htotal-1*/
{P_ENCP_VIDEO_MAX_LNCNT, 0x213,},/*531//vtotal-1*/
{P_ENCP_VIDEO_HAVON_BEGIN, 0x38,},/*56//hblank-hfront*/
{P_ENCP_VIDEO_HAVON_END, 0x38B,},/*907//htotal-hfront-1*/
{P_ENCP_VIDEO_VAVON_BLINE, 0x2A,},/*42//vblank-vfront*/
{P_ENCP_VIDEO_VAVON_ELINE, 0x209,},/*521//vtotal-vfront-1*/
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0x10,},/*16/hor sync time*/
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x2,},/*2//ver sync time*/
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1,},
{P_ENCI_VIDEO_EN, 0,},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_854x480p60hz[] = {
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0x3B5,},/*949//htotal-1*/
{P_ENCP_VIDEO_MAX_LNCNT, 0x212,},/*530//vtotal-1*/
{P_ENCP_VIDEO_HAVON_BEGIN, 0x38,},/*56//hblank-hfront*/
{P_ENCP_VIDEO_HAVON_END, 0x38D,},/*909//htotal-hfront-1*/
{P_ENCP_VIDEO_VAVON_BLINE, 0x29,},/*41//vblank-vfront*/
{P_ENCP_VIDEO_VAVON_ELINE, 0x208,},/*520//vtotal-vfront-1*/
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0x10,},/*16//hor sync time*/
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x2,},/*2//ver sync time*/
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1,},
{P_ENCI_VIDEO_EN, 0,},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_1024x600p60hz[] = {
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0x53F,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x27D,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x128,},
{P_ENCP_VIDEO_HAVON_END, 0x527,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x23,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x27A,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0x88,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1,},
{P_ENCI_VIDEO_EN, 0,},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_1024x768p60hz[] = {
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0x53F,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x325,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x128,},
{P_ENCP_VIDEO_HAVON_END, 0x527,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x23,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x322,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0x88,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1,},
{P_ENCI_VIDEO_EN, 0,},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_1152x864p75hz[] = {
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0x63F,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x383,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x180,},
{P_ENCP_VIDEO_HAVON_END, 0x5FF,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x23,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x382,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0x80,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x3,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1,},
{P_ENCI_VIDEO_EN, 0,},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_1280x600p60hz[] = {
#if 0
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0x59F,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x336,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x70,},
{P_ENCP_VIDEO_HAVON_END, 0x56F,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x14,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x333,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0x20,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCI_VIDEO_EN, 0},
{P_ENCP_VIDEO_EN, 1},
{MREG_END_MARKER, 0}
#endif
};
static const struct reg_s tvregs_vesa_1280x768p60hz[] = {
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0x67F,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x31D,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x140,},
{P_ENCP_VIDEO_HAVON_END, 0x63F,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x1B,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x31A,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0x80,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x7,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCI_VIDEO_EN, 0},
{P_ENCP_VIDEO_EN, 1},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_1280x800p60hz[] = {
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0x59F,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x336,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x70,},
{P_ENCP_VIDEO_HAVON_END, 0x56F,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x14,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x333,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0x20,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCI_VIDEO_EN, 0},
{P_ENCP_VIDEO_EN, 1},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_1280x960p60hz[] = {
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0x707,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x3E7,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x1A8,},
{P_ENCP_VIDEO_HAVON_END, 0x6A7,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x27,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x3E6,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0x70,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x3,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCI_VIDEO_EN, 0},
{P_ENCP_VIDEO_EN, 1},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_1280x1024p60hz[] = {
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0x697,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x429,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x168,},
{P_ENCP_VIDEO_HAVON_END, 0x667,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x29,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x428,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0x70,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x3,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCI_VIDEO_EN, 0},
{P_ENCP_VIDEO_EN, 1},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_1360x768p60hz[] = {
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0x6FF,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x31A,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x170,},
{P_ENCP_VIDEO_HAVON_END, 0x6BF,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x18,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x317,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0x70,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1,},
{P_ENCI_VIDEO_EN, 0,},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_1366x768p60hz[] = {
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0x6FF,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x31D,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x164,},
{P_ENCP_VIDEO_HAVON_END, 0x6B9,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x1B,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x31A,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0x8F,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x3,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1,},
{P_ENCI_VIDEO_EN, 0,},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_1400x1050p60hz[] = {
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0x747,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x440,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x178,},
{P_ENCP_VIDEO_HAVON_END, 0x6EF,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x24,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x43D,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0x90,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x4,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1,},
{P_ENCI_VIDEO_EN, 0,},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_1440x900p60hz[] = {
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0x76F,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x3A5,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x180,},
{P_ENCP_VIDEO_HAVON_END, 0x71F,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x1F,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x3A2,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0x98,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1,},
{P_ENCI_VIDEO_EN, 0,},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_1440x2560p60hz[] = {
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0x623,},
{P_ENCP_VIDEO_MAX_LNCNT, 0xA23,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x44,},
{P_ENCP_VIDEO_HAVON_END, 0x5E3,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x14,},
{P_ENCP_VIDEO_VAVON_ELINE, 0xA13,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0x4,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x4,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1,},
{P_ENCI_VIDEO_EN, 0,},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_1600x900p60hz[] = {
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0x707,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x3E7,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0xB0,},
{P_ENCP_VIDEO_HAVON_END, 0x6EF,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x63,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x3E6,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0x50,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x3,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1,},
{P_ENCI_VIDEO_EN, 0,},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_1600x1200p60hz[] = {
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0x86F,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x4E1,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x1F0,},
{P_ENCP_VIDEO_HAVON_END, 0x82F,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x31,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x4E0,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0xC0,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x3,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1,},
{P_ENCI_VIDEO_EN, 0,},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_1680x1050p60hz[] = {
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0x8BF,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x440,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x1C8,},
{P_ENCP_VIDEO_HAVON_END, 0x857,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x24,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x43D,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0xB0,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1,},
{P_ENCI_VIDEO_EN, 0,},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_1920x1200p60hz[] = {
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0xA1F,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x4DC,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x218,},
{P_ENCP_VIDEO_HAVON_END, 0x997,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x2A,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x4D9,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0xC8,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCI_VIDEO_EN, 0},
{P_ENCP_VIDEO_EN, 1},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_2160x1200p90hz[] = {
{P_ENCP_VIDEO_EN, 0},
{P_ENCI_VIDEO_EN, 0},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0x99D,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x4BB,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x70,},
{P_ENCP_VIDEO_HAVON_END, 0x8DF,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x6,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x4B5,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0x20,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x3,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1},
{P_ENCI_VIDEO_EN, 0},
{MREG_END_MARKER, 0},
};
static const struct reg_s tvregs_vesa_2560x1600p60hz[] = {
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0xDAF,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x679,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x2F0,},
{P_ENCP_VIDEO_HAVON_END, 0xCEF,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x37,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x676,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0x118,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCI_VIDEO_EN, 0},
{P_ENCP_VIDEO_EN, 1},
{MREG_END_MARKER, 0}
};
#if 0 /* TODO */
static const struct reg_s tvregs_vesa_2560x1080p60hz[] = {
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0xA1F,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x4DC,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x218,},
{P_ENCP_VIDEO_HAVON_END, 0x997,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x2A,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x4D9,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0xC8,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCI_VIDEO_EN, 0},
{P_ENCP_VIDEO_EN, 1},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_2560x1440p60hz[] = {
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0xA1F,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x4DC,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x218,},
{P_ENCP_VIDEO_HAVON_END, 0x997,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x2A,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x4D9,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0xC8,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCI_VIDEO_EN, 0},
{P_ENCP_VIDEO_EN, 1},
{MREG_END_MARKER, 0}
};
static const struct reg_s tvregs_vesa_3440x1440p60hz[] = {
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0xA1F,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x4DC,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x218,},
{P_ENCP_VIDEO_HAVON_END, 0x997,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x2A,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x4D9,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
{P_ENCP_VIDEO_HSO_END, 0xC8,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCI_VIDEO_EN, 0},
{P_ENCP_VIDEO_EN, 1},
{MREG_END_MARKER, 0}
};
#endif
struct vic_tvregs_set {
enum hdmi_vic vic;
const struct reg_s *reg_setting;
@@ -725,6 +1506,32 @@ static struct vic_tvregs_set tvregsTab[] = {
{HDMI_3840x2160p50_16x9, tvregs_4k2k_25hz},
{HDMI_3840x2160p60_16x9_Y420, tvregs_4k2k_30hz},
{HDMI_3840x2160p50_16x9_Y420, tvregs_4k2k_25hz},
{HDMI_2560x1080p50_64x27, tvregs_2560x1080p50hz},
{HDMI_2560x1080p60_64x27, tvregs_2560x1080p60hz},
{HDMIV_640x480p60hz, tvregs_vesa_640x480p60hz},
{HDMIV_800x480p60hz, tvregs_vesa_800x480p60hz},
{HDMIV_800x600p60hz, tvregs_vesa_800x600p60hz},
{HDMIV_852x480p60hz, tvregs_vesa_852x480p60hz},
{HDMIV_854x480p60hz, tvregs_vesa_854x480p60hz},
{HDMIV_1024x600p60hz, tvregs_vesa_1024x600p60hz},
{HDMIV_1024x768p60hz, tvregs_vesa_1024x768p60hz},
{HDMIV_1152x864p75hz, tvregs_vesa_1152x864p75hz},
{HDMIV_1280x600p60hz, tvregs_vesa_1280x600p60hz},
{HDMIV_1280x768p60hz, tvregs_vesa_1280x768p60hz},
{HDMIV_1280x800p60hz, tvregs_vesa_1280x800p60hz},
{HDMIV_1280x960p60hz, tvregs_vesa_1280x960p60hz},
{HDMIV_1280x1024p60hz, tvregs_vesa_1280x1024p60hz},
{HDMIV_1360x768p60hz, tvregs_vesa_1360x768p60hz},
{HDMIV_1366x768p60hz, tvregs_vesa_1366x768p60hz},
{HDMIV_1400x1050p60hz, tvregs_vesa_1400x1050p60hz},
{HDMIV_1440x900p60hz, tvregs_vesa_1440x900p60hz},
{HDMIV_1440x2560p60hz, tvregs_vesa_1440x2560p60hz},
{HDMIV_1600x900p60hz, tvregs_vesa_1600x900p60hz},
{HDMIV_1600x1200p60hz, tvregs_vesa_1600x1200p60hz},
{HDMIV_1680x1050p60hz, tvregs_vesa_1680x1050p60hz},
{HDMIV_1920x1200p60hz, tvregs_vesa_1920x1200p60hz},
{HDMIV_2160x1200p90hz, tvregs_vesa_2160x1200p90hz},
{HDMIV_2560x1600p60hz, tvregs_vesa_2560x1600p60hz},
};
/*

193
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
View File

@@ -1265,6 +1265,154 @@ static void hdmi_tvenc480i_set(struct hdmitx_vidpara *param)
hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 0, 1);
}
static void hdmi_tvenc_vesa_set(struct hdmitx_vidpara *param)
{
unsigned long VFIFO2VD_TO_HDMI_LATENCY = 2;
unsigned long TOTAL_PIXELS = 0, PIXEL_REPEAT_HDMI = 0,
PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 0;
unsigned int FRONT_PORCH = 0, HSYNC_PIXELS = 0, ACTIVE_LINES = 0,
INTERLACE_MODE = 0, TOTAL_LINES = 0, SOF_LINES = 0,
VSYNC_LINES = 0;
unsigned int LINES_F0 = 0, LINES_F1 = 0, BACK_PORCH = 0,
EOF_LINES = 0, TOTAL_FRAMES = 0;
unsigned long total_pixels_venc = 0;
unsigned long active_pixels_venc = 0;
unsigned long front_porch_venc = 0;
unsigned long hsync_pixels_venc = 0;
unsigned long de_h_begin = 0, de_h_end = 0;
unsigned long de_v_begin_even = 0, de_v_end_even = 0,
de_v_begin_odd = 0, de_v_end_odd = 0;
unsigned long hs_begin = 0, hs_end = 0;
unsigned long vs_adjust = 0;
unsigned long vs_bline_evn = 0, vs_eline_evn = 0,
vs_bline_odd = 0, vs_eline_odd = 0;
unsigned long vso_begin_evn = 0, vso_begin_odd = 0;
struct hdmi_format_para *vpara = NULL;
struct hdmi_cea_timing *vtiming = NULL;
vpara = hdmi_get_fmt_paras(param->VIC);
if (vpara == NULL) {
pr_info("hdmitx: don't find Paras for VESA %d\n", param->VIC);
return;
}
vtiming = &vpara->timing;
INTERLACE_MODE = 0;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = vtiming->h_active;
ACTIVE_LINES = vtiming->v_active;
LINES_F0 = vtiming->v_total;
LINES_F1 = vtiming->v_total;
FRONT_PORCH = vtiming->h_front;
HSYNC_PIXELS = vtiming->h_sync;
BACK_PORCH = vtiming->h_back;
EOF_LINES = vtiming->v_front;
VSYNC_LINES = vtiming->v_sync;
SOF_LINES = vtiming->v_back;
TOTAL_FRAMES = 4;
TOTAL_PIXELS = (FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS);
TOTAL_LINES = (LINES_F0+(LINES_F1*INTERLACE_MODE));
total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
(1+PIXEL_REPEAT_VENC);
active_pixels_venc = (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
(1+PIXEL_REPEAT_VENC);
front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) *
(1+PIXEL_REPEAT_VENC);
hsync_pixels_venc = (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
(1+PIXEL_REPEAT_VENC);
hd_write_reg(P_ENCP_VIDEO_MODE, hd_read_reg(P_ENCP_VIDEO_MODE)|(1<<14));
/* Program DE timing */
de_h_begin = modulo(hd_read_reg(P_ENCP_VIDEO_HAVON_BEGIN) +
VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc);
de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc);
hd_write_reg(P_ENCP_DE_H_BEGIN, de_h_begin); /* 220 */
hd_write_reg(P_ENCP_DE_H_END, de_h_end); /* 1660 */
/* Program DE timing for even field */
de_v_begin_even = hd_read_reg(P_ENCP_VIDEO_VAVON_BLINE);
de_v_end_even = de_v_begin_even + ACTIVE_LINES;
hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even);
hd_write_reg(P_ENCP_DE_V_END_EVEN, de_v_end_even); /* 522 */
/* Program DE timing for odd field if needed */
if (INTERLACE_MODE) {
de_v_begin_odd = to_signed(
(hd_read_reg(P_ENCP_VIDEO_OFLD_VOAV_OFST)
& 0xf0)>>4) + de_v_begin_even + (TOTAL_LINES-1)/2;
de_v_end_odd = de_v_begin_odd + ACTIVE_LINES;
hd_write_reg(P_ENCP_DE_V_BEGIN_ODD, de_v_begin_odd);
hd_write_reg(P_ENCP_DE_V_END_ODD, de_v_end_odd);
}
/* Program Hsync timing */
if (de_h_end + front_porch_venc >= total_pixels_venc) {
hs_begin = de_h_end + front_porch_venc - total_pixels_venc;
vs_adjust = 1;
} else {
hs_begin = de_h_end + front_porch_venc;
vs_adjust = 0;
}
hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc);
hd_write_reg(P_ENCP_DVI_HSO_BEGIN, hs_begin);
hd_write_reg(P_ENCP_DVI_HSO_END, hs_end);
/* Program Vsync timing for even field */
if (de_v_begin_even >= SOF_LINES + VSYNC_LINES + (1-vs_adjust))
vs_bline_evn = de_v_begin_even - SOF_LINES - VSYNC_LINES -
(1-vs_adjust);
else
vs_bline_evn = TOTAL_LINES + de_v_begin_even - SOF_LINES -
VSYNC_LINES - (1-vs_adjust);
vs_eline_evn = modulo(vs_bline_evn + VSYNC_LINES, TOTAL_LINES);
hd_write_reg(P_ENCP_DVI_VSO_BLINE_EVN, vs_bline_evn); /* 5 */
hd_write_reg(P_ENCP_DVI_VSO_ELINE_EVN, vs_eline_evn); /* 11 */
vso_begin_evn = hs_begin; /* 1692 */
hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn); /* 1692 */
hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn); /* 1692 */
/* Program Vsync timing for odd field if needed */
if (INTERLACE_MODE) {
vs_bline_odd = de_v_begin_odd-1 - SOF_LINES - VSYNC_LINES;
vs_eline_odd = de_v_begin_odd-1 - SOF_LINES;
vso_begin_odd = modulo(hs_begin + (total_pixels_venc>>1),
total_pixels_venc);
hd_write_reg(P_ENCP_DVI_VSO_BLINE_ODD, vs_bline_odd);
hd_write_reg(P_ENCP_DVI_VSO_ELINE_ODD, vs_eline_odd);
hd_write_reg(P_ENCP_DVI_VSO_BEGIN_ODD, vso_begin_odd);
hd_write_reg(P_ENCP_DVI_VSO_END_ODD, vso_begin_odd);
}
switch (param->VIC) {
case HDMIV_640x480p60hz:
hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
(0 << 1) |
(0 << 2) |
(0 << 3) |
(0 << 4) |
(4 << 5) |
(0 << 8) |
(0 << 12)
);
hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
break;
default:
hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
(0 << 1) | /* [ 1] src_sel_encp */
(HSYNC_POLARITY << 2) |
(VSYNC_POLARITY << 3) |
(0 << 4) |
(4 << 5) |
(0 << 8) |
(0 << 12)
);
hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
}
hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
}
static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
{
unsigned long VFIFO2VD_TO_HDMI_LATENCY = 2;
@@ -1287,6 +1435,20 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
unsigned long vs_adjust = 0;
unsigned long vs_bline_evn = 0, vs_eline_evn = 0;
unsigned long vso_begin_evn = 0;
struct hdmi_format_para *hdmi_encp_para = NULL;
struct hdmi_cea_timing *hdmi_encp_timing = NULL;
if ((param->VIC & HDMITX_VESA_OFFSET) == HDMITX_VESA_OFFSET) {
/* VESA modes setting */
hdmi_tvenc_vesa_set(param);
return;
}
hdmi_encp_para = hdmi_get_fmt_paras(param->VIC);
if (hdmi_encp_para == NULL) {
pr_info("hdmitx: don't find Paras for VIC : %d\n", param->VIC);
} else {
hdmi_encp_timing = &hdmi_encp_para->timing;
switch (param->VIC) {
case HDMI_3840x1080p120hz:
@@ -1471,6 +1633,23 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
SOF_LINES = 36;
TOTAL_FRAMES = 4;
break;
case HDMI_2560x1080p50_64x27:
case HDMI_2560x1080p60_64x27:
INTERLACE_MODE = 0U;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = hdmi_encp_timing->h_active;
ACTIVE_LINES = hdmi_encp_timing->v_active;
LINES_F0 = hdmi_encp_timing->v_total;
LINES_F1 = hdmi_encp_timing->v_total;
FRONT_PORCH = hdmi_encp_timing->h_front;
HSYNC_PIXELS = hdmi_encp_timing->h_sync;
BACK_PORCH = hdmi_encp_timing->h_back;
EOF_LINES = hdmi_encp_timing->v_front;
VSYNC_LINES = hdmi_encp_timing->v_sync;
SOF_LINES = hdmi_encp_timing->v_back;
TOTAL_FRAMES = 4;
break;
default:
break;
}
@@ -1644,6 +1823,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
(param->VIC == HDMI_576p50_16x9_rpt))
hd_set_reg_bits(P_VPU_HDMI_SETTING, 3, 12, 4);
hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
}
}
void phy_pll_off(void)
@@ -1868,6 +2048,9 @@ static void hdmitx_set_scdc(struct hdmitx_dev *hdev)
else
hdev->para->tmds_clk_div40 = 1;
break;
case HDMIV_2560x1600p60hz:
hdev->para->tmds_clk_div40 = 0;
break;
default:
hdev->para->tmds_clk_div40 = 0;
break;
@@ -4373,9 +4556,9 @@ static void hdcptx_events_handle(unsigned long arg)
pr_info("hdcp14: instat: 0x%x\n", st_flag);
}
if (st_flag & (1 << 6)) {
if (st_flag & (1 << 6))
hdmitx_set_reg_bits(HDMITX_DWC_A_HDCPCFG1, 1, 1, 1);
}
if (st_flag & (1 << 7)) {
hdmitx_wr_reg(HDMITX_DWC_A_APIINTCLR, 1 << 7);
hdmitx_hdcp_opr(3);
@@ -5449,6 +5632,12 @@ static void config_hdmi20_tx(enum hdmi_vic vic,
hdmitx_wr_reg(HDMITX_DWC_FC_AVIVID, (para->vic & HDMITX_VIC_MASK));
/* For VESA modes, set VIC as 0 */
if (para->vic >= HDMITX_VESA_OFFSET) {
hdmitx_wr_reg(HDMITX_DWC_FC_AVIVID, 0);
hd_write_reg(P_ISA_DEBUG_REG0, para->vic);
}
/* write Audio Infoframe packet configuration */
data32 = 0;

78
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
View File

@@ -763,6 +763,12 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
HDMI_1920x1080p25_16x9,
HDMI_VIC_END},
5940000, 4, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
{{HDMI_2560x1080p50_64x27,
HDMI_VIC_END},
3712500, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
{{HDMI_2560x1080p60_64x27,
HDMI_VIC_END},
3960000, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
{{HDMI_3840x2160p30_16x9,
HDMI_3840x2160p25_16x9,
HDMI_3840x2160p24_16x9,
@@ -786,6 +792,66 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
{{HDMI_VIC_FAKE,
HDMI_VIC_END},
3450000, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
/* pll setting for VESA modes */
{{HDMIV_640x480p60hz, /* 4.028G / 16 = 251.75M */
HDMI_VIC_END},
4028000, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_800x480p60hz,
HDMI_VIC_END},
4761600, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_800x600p60hz,
HDMI_VIC_END},
3200000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_852x480p60hz,
HDMIV_854x480p60hz,
HDMI_VIC_END},
4838400, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_1024x600p60hz,
HDMI_VIC_END},
4115866, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_1024x768p60hz,
HDMI_VIC_END},
5200000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_1280x768p60hz,
HDMI_VIC_END},
3180000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_1280x800p60hz,
HDMI_VIC_END},
5680000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_1152x864p75hz,
HDMIV_1280x960p60hz,
HDMIV_1280x1024p60hz,
HDMIV_1600x900p60hz,
HDMI_VIC_END},
4320000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_1600x1200p60hz,
HDMI_VIC_END},
3240000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_1360x768p60hz,
HDMIV_1366x768p60hz,
HDMI_VIC_END},
3420000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_1400x1050p60hz,
HDMI_VIC_END},
4870000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_1440x900p60hz,
HDMI_VIC_END},
4260000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_1440x2560p60hz,
HDMI_VIC_END},
4897000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_1680x1050p60hz,
HDMI_VIC_END},
5850000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_1920x1200p60hz,
HDMI_VIC_END},
3865000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_2160x1200p90hz,
HDMI_VIC_END},
5371100, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
{{HDMIV_2560x1600p60hz,
HDMI_VIC_END},
3485000, 1, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
};
/* For colordepth 10bits */
@@ -815,6 +881,12 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_30[] = {
HDMI_1920x1080p25_16x9,
HDMI_VIC_END},
3712500, 2, 2, 2, VID_PLL_DIV_6p25, 1, 1, 1, -1},
{{HDMI_2560x1080p50_64x27,
HDMI_VIC_END},
4640625, 1, 2, 2, VID_PLL_DIV_6p25, 1, 1, 1, -1},
{{HDMI_2560x1080p60_64x27,
HDMI_VIC_END},
4950000, 1, 2, 2, VID_PLL_DIV_6p25, 1, 1, 1, -1},
{{HDMI_4096x2160p60_256x135_Y420,
HDMI_4096x2160p50_256x135_Y420,
HDMI_3840x2160p60_16x9_Y420,
@@ -856,6 +928,12 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_36[] = {
HDMI_1920x1080p50_16x9,
HDMI_VIC_END},
4455000, 1, 2, 2, VID_PLL_DIV_7p5, 1, 1, 1, -1},
{{HDMI_2560x1080p50_64x27,
HDMI_VIC_END},
5568750, 1, 2, 2, VID_PLL_DIV_7p5, 1, 1, 1, -1},
{{HDMI_2560x1080p60_64x27,
HDMI_VIC_END},
5940000, 1, 2, 2, VID_PLL_DIV_7p5, 1, 1, 1, -1},
{{HDMI_1920x1080p30_16x9,
HDMI_1920x1080p24_16x9,
HDMI_1920x1080p25_16x9,

18
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
View File

@@ -204,11 +204,9 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
}
if (set_hpll_hclk_v1(0xf7, frac_rate ? 0x8148 : 0x10000))
break;
else if (set_hpll_hclk_v2(0x7b, 0x18000))
if (set_hpll_hclk_v2(0x7b, 0x18000))
break;
else if (set_hpll_hclk_v3(0xf7, 0x10000))
break;
else
if (set_hpll_hclk_v3(0xf7, 0x10000))
break;
break;
case 5405400:
@@ -226,6 +224,18 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
break;
case 4897000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004cc);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0000d560);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
break;
case 4455000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004b9);
if (frac_rate)

240
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_gxl.c
View File

@@ -132,6 +132,18 @@ void set_gxl_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 5680000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002ec);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb2ab);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 5405400:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002e1);
if (frac_rate)
@@ -147,6 +159,30 @@ void set_gxl_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 5200000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002d8);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb2ab);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 4870000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002ca);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb3ab);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 4455000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002b9);
if (frac_rate)
@@ -177,6 +213,18 @@ void set_gxl_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 3485000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x40000291);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb0d5);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 3450000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x4000028f);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb300);
@@ -204,6 +252,18 @@ void set_gxl_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 3240000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x40000287);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 2970000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x4000027b);
if (frac_rate)
@@ -234,6 +294,186 @@ void set_gxl_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 4320000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002b4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 3180000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x40000284);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 3200000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x40000285);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb155);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 3340000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x4000028b);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb0ab);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 3420000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x4000028e);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb200);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 3865000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002a1);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb02b);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 4028000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002a7);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb355);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 4115866:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002a8);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb1fa);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 4260000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002b1);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb200);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 4761600:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002c6);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb19a);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 4838400:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002c9);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb266);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 4897000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002cc);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb02b);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 5371100:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002df);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb32f);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 5600000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002e9);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb155);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 5850000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002f3);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb300);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
default:
pr_info("error hpll clk: %d\n", clk);
break;

43
include/linux/amlogic/media/vout/hdmi_tx/hdmi_common.h
View File

@@ -27,6 +27,8 @@
*/
#define HDMITX_VIC420_OFFSET 0x100
#define HDMITX_VIC420_FAKE_OFFSET 0x200
#define HDMITX_VESA_OFFSET 0x300
#define HDMITX_VIC_MASK 0xff
@@ -176,6 +178,33 @@ enum hdmi_vic {
HDMI_VIC_Y420_MAX,
HDMI_VIC_FAKE = HDMITX_VIC420_FAKE_OFFSET,
HDMIV_640x480p60hz = HDMITX_VESA_OFFSET,
HDMIV_800x480p60hz,
HDMIV_800x600p60hz,
HDMIV_852x480p60hz,
HDMIV_854x480p60hz,
HDMIV_1024x600p60hz,
HDMIV_1024x768p60hz,
HDMIV_1152x864p75hz,
HDMIV_1280x600p60hz,
HDMIV_1280x768p60hz,
HDMIV_1280x800p60hz,
HDMIV_1280x960p60hz,
HDMIV_1280x1024p60hz,
HDMIV_1360x768p60hz,
HDMIV_1366x768p60hz,
HDMIV_1400x1050p60hz,
HDMIV_1440x900p60hz,
HDMIV_1440x2560p60hz,
HDMIV_1600x900p60hz,
HDMIV_1600x1200p60hz,
HDMIV_1680x1050p60hz,
HDMIV_1920x1200p60hz,
HDMIV_2160x1200p90hz,
HDMIV_2560x1080p60hz,
HDMIV_2560x1440p60hz,
HDMIV_2560x1600p60hz,
HDMIV_3440x1440p60hz,
HDMI_VIC_END,
};
@@ -228,6 +257,7 @@ struct hdmi_cea_timing {
unsigned int frac_freq; /* 1.001 shift */
unsigned int h_freq; /* Unit: Hz */
unsigned int v_freq; /* Unit: 0.001 Hz */
unsigned int vsync; /* Unit: Hz, rough data */
unsigned int vsync_polarity:1;
unsigned int hsync_polarity:1;
unsigned short h_active;
@@ -352,6 +382,7 @@ enum hdmi_aspect_ratio {
TV_ASPECT_RATIO_14_9 = 0xB,
TV_ASPECT_RATIO_MAX
};
struct vesa_standard_timing;
struct hdmi_format_para *hdmi_get_fmt_paras(enum hdmi_vic vic);
struct hdmi_format_para *hdmi_match_dtd_paras(struct dtd *t);
@@ -367,6 +398,8 @@ const char *hdmi_get_str_cs(struct hdmi_format_para *para);
const char *hdmi_get_str_cr(struct hdmi_format_para *para);
unsigned int hdmi_get_aud_n_paras(enum hdmi_audio_fs fs,
enum hdmi_color_depth cd, unsigned int tmds_clk);
struct hdmi_format_para *hdmi_get_vesa_paras(struct vesa_standard_timing *t);
/* HDMI Audio Parmeters */
/* Refer to CEA-861-D Page 88 */
@@ -583,4 +616,14 @@ struct dtd {
enum hdmi_vic vic;
};
struct vesa_standard_timing {
unsigned short hactive;
unsigned short vactive;
unsigned short hblank;
unsigned short vblank;
unsigned short hsync;
unsigned short tmds_clk; /* Value = Pixel clock ?? 10,000 */
enum hdmi_vic vesa_timing;
};
#endif

2
include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h
View File

@@ -82,6 +82,7 @@ struct hdr_dynamic_struct {
unsigned char support_flags;
unsigned char optional_fields[20];
};
#define VESA_MAX_TIMING 64
struct rx_cap {
unsigned int native_Mode;
@@ -89,6 +90,7 @@ struct rx_cap {
unsigned int VIC[VIC_MAX_NUM];
unsigned int VIC_count;
unsigned int native_VIC;
enum hdmi_vic vesa_timing[VESA_MAX_TIMING]; /* Max 64 */
/*audio*/
struct rx_audiocap RxAudioCap[AUD_MAX_NUM];
unsigned char AUD_count;