shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 03:15:31 +09:00
Code Issues Packages Projects Releases Wiki Activity

drm/rockchip: vop2: Set sdr2hdr_path_en when sdr2hdr enabled

Browse Source 
If sdr2hdr_path_en is not set in sdr2hdr mode, the dly may
not match with the delay number list in TRM.

Change-Id: I989df532e42dc071ee78db79c234fa9582b8bccd
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
This commit is contained in:
Andy Yan
2021-03-09 11:21:44 +08:00
parent 47e32bf33c
commit a80aeb4d42
3 changed files with 3 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -570,6 +570,7 @@ struct vop2_video_port_regs {
struct vop_reg sdr2hdr_oetf_en;
struct vop_reg sdr2hdr_bypass_en;
struct vop_reg sdr2hdr_auto_gating_en;
struct vop_reg sdr2hdr_path_en;
struct vop_reg hdr2sdr_en;
struct vop_reg hdr2sdr_bypass_en;
struct vop_reg hdr2sdr_auto_gating_en;

1
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -4160,6 +4160,7 @@ static void vop2_setup_hdr10(struct vop2_video_port *vp, uint8_t win_phys_id)
vop2_load_sdr2hdr_table(vp, sdr2hdr_tf);
VOP_MODULE_SET(vop2, vp, sdr2hdr_r2r_mode, sdr2hdr_r2r_mode);
}
VOP_MODULE_SET(vop2, vp, sdr2hdr_path_en, sdr2hdr_en);
VOP_MODULE_SET(vop2, vp, sdr2hdr_oetf_en, sdr2hdr_en);
VOP_MODULE_SET(vop2, vp, sdr2hdr_eotf_en, sdr2hdr_en);
VOP_MODULE_SET(vop2, vp, sdr2hdr_r2r_en, sdr2hdr_en);

1
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View File

@@ -471,6 +471,7 @@ static const struct vop2_video_port_regs rk3568_vop_vp0_regs = {
.sdr2hdr_oetf_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 3),
.sdr2hdr_bypass_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 8),
.sdr2hdr_auto_gating_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 9),
.sdr2hdr_path_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 5),
.hdr2sdr_en = VOP_REG(RK3568_HDR2SDR_CTRL, 0x1, 0),
.hdr2sdr_bypass_en = VOP_REG(RK3568_HDR2SDR_CTRL, 0x1, 8),
.hdr2sdr_auto_gating_en = VOP_REG(RK3568_HDR2SDR_CTRL, 0x1, 9),