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arm64: dts: rockchip: add naneng combo phy nodes for RK3568

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Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I85cbf3f7f104e0b0c37a57517dcbb0fc22500623
This commit is contained in:
Yifeng Zhao
2020-10-09 15:12:58 +08:00
committed by Tao Huang
parent 2989301f4e
commit a829648072
1 changed files with 59 additions and 0 deletions
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59
arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -228,6 +228,11 @@
};
};
pipegrf: syscon@fdc50000 {
compatible = "rockchip,rk3568-pipegrf", "syscon";
reg = <0x0 0xfdc50000 0x0 0x1000>;
};
grf: syscon@fdc60000 {
compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
reg = <0x0 0xfdc60000 0x0 0x10000>;
@@ -238,6 +243,21 @@
};
};
pipe_phy_grf0: syscon@fdc70000 {
compatible = "rockchip,pipe-phy-grf", "syscon";
reg = <0x0 0xfdc70000 0x0 0x1000>;
};
pipe_phy_grf1: syscon@fdc80000 {
compatible = "rockchip,pipe-phy-grf", "syscon";
reg = <0x0 0xfdc80000 0x0 0x1000>;
};
pipe_phy_grf2: syscon@fdc90000 {
compatible = "rockchip,pipe-phy-grf", "syscon";
reg = <0x0 0xfdc90000 0x0 0x1000>;
};
pmucru: clock-controller@fdd00000 {
compatible = "rockchip,rk3568-pmucru";
reg = <0x0 0xfdd00000 0x0 0x1000>;
@@ -1258,6 +1278,45 @@
status = "disabled";
};
combphy0_us: phy@fe820000 {
compatible = "rockchip,rk3568-naneng-combphy";
reg = <0x0 0xfe820000 0x0 0x100>;
#phy-cells = <1>;
clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>;
clock-names = "refclk", "apbclk";
resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
reset-names = "combphy-apb", "combphy";
rockchip,pipe-grf = <&pipegrf>;
rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
status = "disabled";
};
combphy1_usq: phy@fe830000 {
compatible = "rockchip,rk3568-naneng-combphy";
reg = <0x0 0xfe830000 0x0 0x100>;
#phy-cells = <1>;
clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>;
clock-names = "refclk", "apbclk";
resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
reset-names = "combphy-apb", "combphy";
rockchip,pipe-grf = <&pipegrf>;
rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
status = "disabled";
};
combphy2_psq: phy@fe840000 {
compatible = "rockchip,rk3568-naneng-combphy";
reg = <0x0 0xfe840000 0x0 0x100>;
#phy-cells = <1>;
clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>;
clock-names = "refclk", "apbclk";
resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>;
reset-names = "combphy-apb", "combphy";
rockchip,pipe-grf = <&pipegrf>;
rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
status = "disabled";
};
pinctrl: pinctrl {
compatible = "rockchip,rk3568-pinctrl";
rockchip,grf = <&grf>;