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Merge commit '0b97d73d8e712e12e7fdea55e59bc0a21bf50b4c'
* commit '0b97d73d8e712e12e7fdea55e59bc0a21bf50b4c': video: rockchip: rga3: fix the wrong check of resolution in RGA3 rotating video: rockchip: rga3: Add debug log when assign cores media: rockchip: isp: dvbm buf support from rockit media: rockchip: isp: support multiple wrap media: rockchip: isp: fix isp stop to read stats buf ASoC: rockchip: trcm: Fix sleeping function called in atomic context ARM: dts: rockchip: Add core dtsi for RV1106G3 Change-Id: I699210591b363274d44466b9f34f45bae6a38eab
This commit is contained in:
32
arch/arm/boot/dts/rv1106g3.dtsi
Normal file
32
arch/arm/boot/dts/rv1106g3.dtsi
Normal file
@@ -0,0 +1,32 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*/
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#include "rv1106.dtsi"
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/ {
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compatible = "rockchip,rv1106g3";
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};
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&cru {
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assigned-clocks =
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<&cru PLL_GPLL>, <&cru PLL_CPLL>,
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<&cru ARMCLK>,
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<&cru ACLK_PERI_ROOT>, <&cru HCLK_PERI_ROOT>,
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<&cru PCLK_PERI_ROOT>, <&cru ACLK_BUS_ROOT>,
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<&cru PCLK_TOP_ROOT>, <&cru PCLK_PMU_ROOT>,
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<&cru HCLK_PMU_ROOT>, <&cru CLK_500M_SRC>;
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assigned-clock-rates =
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<1188000000>, <700000000>,
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<1104000000>,
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<400000000>, <200000000>,
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<100000000>, <300000000>,
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<100000000>, <100000000>,
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<200000000>, <700000000>;
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};
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&npu {
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assigned-clock-rates = <700000000>;
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};
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@@ -1155,12 +1155,8 @@ static int rkisp_set_wrap_line(struct rkisp_stream *stream, struct rkisp_wrap_in
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{
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struct rkisp_device *dev = stream->ispdev;
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if (dev->isp_ver != ISP_V32 ||
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dev->hw_dev->dev_link_num > 1 ||
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!stream->ops->set_wrap ||
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dev->hw_dev->unite) {
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v4l2_err(&dev->v4l2_dev,
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"wrap only support for single sensor and mainpath\n");
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if (!stream->ops->set_wrap) {
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v4l2_err(&dev->v4l2_dev, "no support wrap\n");
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return -EINVAL;
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}
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dev->cap_dev.wrap_width = arg->width;
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@@ -752,7 +752,8 @@ static int mp_config_mi(struct rkisp_stream *stream)
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mi_frame_end_int_enable(stream);
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/* set up first buffer */
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mi_frame_end(stream, FRAME_INIT);
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if (dev->cap_dev.wrap_line && stream->dummy_buf.mem_priv)
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mi_frame_end(stream, FRAME_INIT);
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rkisp_unite_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
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rkisp_unite_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
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@@ -1364,11 +1365,6 @@ static int mi_frame_start(struct rkisp_stream *stream, u32 mis)
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unsigned long lock_flags = 0;
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u32 val;
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if (stream->streaming && dev->isp_ver == ISP_V32) {
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rkisp_rockit_buf_done(stream, ROCKIT_DVBM_START);
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rkisp_rockit_ctrl_fps(stream);
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}
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/* readback start to update stream buf if null */
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spin_lock_irqsave(&stream->vbq_lock, lock_flags);
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if (stream->streaming) {
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@@ -1709,17 +1705,19 @@ static int rkisp_create_dummy_buf(struct rkisp_stream *stream)
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{
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struct rkisp_device *dev = stream->ispdev;
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struct rkisp_dummy_buffer *buf = &stream->dummy_buf;
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int ret;
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int ret = 0;
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/* mainpath for warp default */
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if (!dev->cap_dev.wrap_line || stream->id != RKISP_STREAM_MP)
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return 0;
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buf->size = dev->cap_dev.wrap_width * dev->cap_dev.wrap_line * 2;
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if (stream->out_isp_fmt.output_format == ISP32_MI_OUTPUT_YUV420)
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buf->size = buf->size - buf->size / 4;
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buf->is_need_dbuf = true;
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ret = rkisp_alloc_buffer(stream->ispdev, buf);
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if (!buf->dma_addr) {
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buf->size = dev->cap_dev.wrap_width * dev->cap_dev.wrap_line * 2;
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if (stream->out_isp_fmt.output_format == ISP32_MI_OUTPUT_YUV420)
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buf->size = buf->size - buf->size / 4;
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buf->is_need_dbuf = true;
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ret = rkisp_alloc_buffer(stream->ispdev, buf);
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}
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if (ret == 0) {
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ret = rkisp_dvbm_init(stream);
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if (ret < 0)
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@@ -1737,6 +1735,7 @@ static void rkisp_destroy_dummy_buf(struct rkisp_stream *stream)
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return;
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rkisp_dvbm_deinit();
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rkisp_free_buffer(dev, &stream->dummy_buf);
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stream->dummy_buf.dma_addr = 0;
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}
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static void destroy_buf_queue(struct rkisp_stream *stream,
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@@ -2044,7 +2043,7 @@ rkisp_start_streaming(struct vb2_queue *queue, unsigned int count)
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goto buffer_done;
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if (dev->isp_ver == ISP_V32 &&
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count == 0 && !stream->dummy_buf.mem_priv &&
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count == 0 && !stream->dummy_buf.dma_addr &&
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list_empty(&stream->buf_queue)) {
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v4l2_err(v4l2_dev, "no buf for %s\n", node->vdev.name);
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ret = -EINVAL;
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@@ -30,7 +30,7 @@ void rkisp_rockit_buf_state_clear(struct rkisp_stream *stream);
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int rkisp_rockit_buf_free(struct rkisp_stream *stream);
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void rkisp_rockit_dev_init(struct rkisp_device *dev);
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void rkisp_rockit_dev_deinit(void);
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bool rkisp_rockit_ctrl_fps(struct rkisp_stream *stream);
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void rkisp_rockit_frame_start(struct rkisp_device *dev);
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int rkisp_rockit_fps_set(int *dst_fps, struct rkisp_stream *stream);
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int rkisp_rockit_fps_get(int *dst_fps, struct rkisp_stream *stream);
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int rkisp_rockit_buf_done(struct rkisp_stream *stream, int cmd);
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@@ -44,7 +44,7 @@ static inline void rkisp_rockit_buf_state_clear(struct rkisp_stream *stream) { r
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static inline int rkisp_rockit_buf_free(struct rkisp_stream *stream) { return -EINVAL; }
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static inline void rkisp_rockit_dev_init(struct rkisp_device *dev) { return; }
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static inline void rkisp_rockit_dev_deinit(void) {}
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static inline bool rkisp_rockit_ctrl_fps(struct rkisp_stream *stream) { return false; }
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static inline void rkisp_rockit_frame_start(struct rkisp_device *dev) {}
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static inline int rkisp_rockit_fps_set(int *dst_fps, struct rkisp_stream *stream) { return -EINVAL; }
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static inline int rkisp_rockit_fps_get(int *dst_fps, struct rkisp_stream *stream) { return -EINVAL; }
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static inline int rkisp_rockit_buf_done(struct rkisp_stream *stream, int cmd) { return -EINVAL; }
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@@ -87,6 +87,7 @@ int rkisp_rockit_buf_queue(struct rockit_cfg *input_rockit_cfg)
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int i, height, offset, dev_id;
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struct rkisp_stream_cfg *stream_cfg = NULL;
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unsigned long lock_flags = 0;
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u32 reg, val, bytesperline;
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if (!input_rockit_cfg)
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return -EINVAL;
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@@ -158,6 +159,20 @@ int rkisp_rockit_buf_queue(struct rockit_cfg *input_rockit_cfg)
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isprk_buf->isp_buf.buff_addr[i] = isprk_buf->buff_addr;
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}
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if (ispdev->cap_dev.wrap_line && stream->id == RKISP_STREAM_MP && isprk_buf) {
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val = isprk_buf->buff_addr;
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reg = stream->config->mi.y_base_ad_init;
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rkisp_write(ispdev, reg, val, false);
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bytesperline = stream->out_fmt.plane_fmt[0].bytesperline;
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val += bytesperline * ispdev->cap_dev.wrap_line;
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reg = stream->config->mi.cb_base_ad_init;
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rkisp_write(ispdev, reg, val, false);
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stream->dummy_buf.dma_addr = isprk_buf->buff_addr;
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v4l2_info(&ispdev->v4l2_dev, "rockit wrap buf:0x%x\n", isprk_buf->buff_addr);
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return -EINVAL;
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}
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if (stream_cfg->is_discard && stream->streaming)
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return -EINVAL;
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@@ -178,8 +193,8 @@ int rkisp_rockit_buf_queue(struct rockit_cfg *input_rockit_cfg)
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if (stream->out_isp_fmt.mplanes == 1) {
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for (i = 0; i < stream->out_isp_fmt.cplanes - 1; i++) {
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height = stream->out_fmt.height;
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offset = (i == 0) ?
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stream->out_fmt.plane_fmt[i].bytesperline * height :
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bytesperline = stream->out_fmt.plane_fmt[i].bytesperline;
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offset = (i == 0) ? bytesperline * height :
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stream->out_fmt.plane_fmt[i].sizeimage;
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isprk_buf->isp_buf.buff_addr[i + 1] =
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isprk_buf->isp_buf.buff_addr[i] + offset;
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@@ -305,6 +320,7 @@ int rkisp_rockit_config_stream(struct rockit_cfg *input_rockit_cfg,
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struct rkisp_buffer *isp_buf, *buf_temp;
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int offset, i, ret;
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unsigned long lock_flags = 0;
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u32 reg, val, bytesperline;
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stream = rkisp_rockit_get_stream(input_rockit_cfg);
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@@ -321,8 +337,18 @@ int rkisp_rockit_config_stream(struct rockit_cfg *input_rockit_cfg,
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pr_err("stream id %d config failed\n", stream->id);
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return -EINVAL;
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}
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if (stream->ispdev->cap_dev.wrap_line && stream->id == RKISP_STREAM_MP)
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if (stream->ispdev->cap_dev.wrap_line && stream->id == RKISP_STREAM_MP) {
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rkisp_dvbm_init(stream);
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if (!stream->dummy_buf.mem_priv && stream->dummy_buf.dma_addr) {
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bytesperline = stream->out_fmt.plane_fmt[0].bytesperline;
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val = stream->dummy_buf.dma_addr;
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reg = stream->config->mi.y_base_ad_init;
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rkisp_write(stream->ispdev, reg, val, false);
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val += bytesperline * stream->ispdev->cap_dev.wrap_line;
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reg = stream->config->mi.cb_base_ad_init;
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rkisp_write(stream->ispdev, reg, val, false);
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}
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}
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spin_lock_irqsave(&stream->vbq_lock, lock_flags);
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if (stream->curr_buf) {
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@@ -339,11 +365,10 @@ int rkisp_rockit_config_stream(struct rockit_cfg *input_rockit_cfg,
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if (stream->out_isp_fmt.mplanes == 1) {
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for (i = 0; i < stream->out_isp_fmt.cplanes - 1; i++) {
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height = stream->out_fmt.height;
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offset = (i == 0) ?
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stream->out_fmt.plane_fmt[i].bytesperline * height :
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bytesperline = stream->out_fmt.plane_fmt[i].bytesperline;
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offset = (i == 0) ? bytesperline * height :
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stream->out_fmt.plane_fmt[i].sizeimage;
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isp_buf->buff_addr[i + 1] =
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isp_buf->buff_addr[i] + offset;
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isp_buf->buff_addr[i + 1] = isp_buf->buff_addr[i] + offset;
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}
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}
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}
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@@ -576,7 +601,7 @@ int rkisp_rockit_fps_get(int *dst_fps, struct rkisp_stream *stream)
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return 0;
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}
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bool rkisp_rockit_ctrl_fps(struct rkisp_stream *stream)
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static bool rkisp_rockit_ctrl_fps(struct rkisp_stream *stream)
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{
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struct rkisp_device *dev = stream->ispdev;
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struct rkisp_sensor_info *sensor = NULL;
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@@ -654,6 +679,25 @@ bool rkisp_rockit_ctrl_fps(struct rkisp_stream *stream)
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return true;
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}
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void rkisp_rockit_frame_start(struct rkisp_device *dev)
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{
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struct rkisp_stream *stream;
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int i;
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if (rockit_cfg == NULL)
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return;
|
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for (i = 0; i < RKISP_MAX_STREAM; i++) {
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if (i == RKISP_STREAM_VIR || i == RKISP_STREAM_LUMA)
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continue;
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stream = &dev->cap_dev.stream[i];
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if (!stream->streaming)
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continue;
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rkisp_rockit_buf_done(stream, ROCKIT_DVBM_START);
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rkisp_rockit_ctrl_fps(stream);
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}
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}
|
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|
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void *rkisp_rockit_function_register(void *function, int cmd)
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{
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if (rockit_cfg == NULL) {
|
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|
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@@ -145,11 +145,12 @@ static void rkisp_stats_vb2_buf_queue(struct vb2_buffer *vb)
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struct rkisp_buffer *stats_buf = to_rkisp_buffer(vbuf);
|
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struct vb2_queue *vq = vb->vb2_queue;
|
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struct rkisp_isp_stats_vdev *stats_dev = vq->drv_priv;
|
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struct rkisp_device *dev = stats_dev->dev;
|
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u32 size = stats_dev->vdev_fmt.fmt.meta.buffersize;
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unsigned long flags;
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|
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stats_buf->vaddr[0] = vb2_plane_vaddr(vb, 0);
|
||||
if (stats_dev->dev->isp_ver == ISP_V32) {
|
||||
if (dev->isp_ver == ISP_V32) {
|
||||
struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
|
||||
|
||||
stats_buf->buff_addr[0] = sg_dma_address(sgt->sgl);
|
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@@ -157,11 +158,12 @@ static void rkisp_stats_vb2_buf_queue(struct vb2_buffer *vb)
|
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if (stats_buf->vaddr[0])
|
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memset(stats_buf->vaddr[0], 0, size);
|
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spin_lock_irqsave(&stats_dev->rd_lock, flags);
|
||||
if (stats_dev->dev->isp_ver == ISP_V32 && stats_dev->dev->is_pre_on) {
|
||||
if (dev->isp_ver == ISP_V32 && dev->is_pre_on) {
|
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struct rkisp32_isp_stat_buffer *buf = stats_dev->stats_buf[0].vaddr;
|
||||
|
||||
if (buf && !buf->frame_id && buf->meas_type && stats_buf->vaddr[0]) {
|
||||
dev_info(stats_dev->dev->dev,
|
||||
if (dev->isp_state & ISP_START && stats_buf->vaddr[0] &&
|
||||
buf && !buf->frame_id && buf->meas_type) {
|
||||
dev_info(dev->dev,
|
||||
"tb stat seq:%d meas_type:0x%x\n",
|
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buf->frame_id, buf->meas_type);
|
||||
memcpy(stats_buf->vaddr[0], buf, sizeof(struct rkisp32_isp_stat_buffer));
|
||||
|
||||
@@ -711,6 +711,8 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo
|
||||
params_vdev->rdbk_times = dma2frm + 1;
|
||||
|
||||
run_next:
|
||||
if (!dev->sw_rd_cnt)
|
||||
rkisp_rockit_frame_start(dev);
|
||||
rkisp_params_cfgsram(params_vdev, true);
|
||||
stats_vdev->rdbk_drop = false;
|
||||
if (dev->is_frame_double) {
|
||||
@@ -4163,6 +4165,7 @@ void rkisp_isp_isr(unsigned int isp_mis,
|
||||
dev->isp_sdev.frm_timestamp = rkisp_time_get_ns(dev);
|
||||
rkisp_isp_queue_event_sof(&dev->isp_sdev);
|
||||
rkisp_stream_frame_start(dev, isp_mis);
|
||||
rkisp_rockit_frame_start(dev);
|
||||
}
|
||||
vs_skip:
|
||||
writel(CIF_ISP_V_START, base + CIF_ISP_ICR);
|
||||
@@ -4317,6 +4320,7 @@ vs_skip:
|
||||
dev->isp_sdev.frm_timestamp = rkisp_time_get_ns(dev);
|
||||
rkisp_isp_queue_event_sof(&dev->isp_sdev);
|
||||
rkisp_stream_frame_start(dev, isp_mis);
|
||||
rkisp_rockit_frame_start(dev);
|
||||
}
|
||||
|
||||
if (isp_mis & ISP3X_OUT_FRM_QUARTER) {
|
||||
|
||||
@@ -1755,32 +1755,71 @@ static int rga3_scale_check(const struct rga3_req *req)
|
||||
u32 win0_saw, win0_sah, win0_daw, win0_dah;
|
||||
u32 win1_saw, win1_sah, win1_daw, win1_dah;
|
||||
|
||||
win0_saw = req->win0.src_act_w;
|
||||
win0_sah = req->win0.src_act_h;
|
||||
win0_daw = req->win0.dst_act_w;
|
||||
win0_dah = req->win0.dst_act_h;
|
||||
if (req->rotate_mode & RGA3_ROT_BIT_ROT_90) {
|
||||
if (req->win1.yrgb_addr != 0) {
|
||||
/* ABB */
|
||||
if (req->win0.yrgb_addr == req->wr.yrgb_addr) {
|
||||
/* win0 do not need rotate, but net equal to wr */
|
||||
win0_saw = req->win0.src_act_h;
|
||||
win0_sah = req->win0.src_act_w;
|
||||
win0_daw = req->win0.dst_act_h;
|
||||
win0_dah = req->win0.dst_act_w;
|
||||
|
||||
win1_saw = req->win1.dst_act_w;
|
||||
win1_sah = req->win1.dst_act_h;
|
||||
win1_daw = req->win1.dst_act_h;
|
||||
win1_dah = req->win1.dst_act_w;
|
||||
} else {
|
||||
win0_saw = req->win0.src_act_w;
|
||||
win0_sah = req->win0.src_act_h;
|
||||
win0_daw = req->win0.dst_act_w;
|
||||
win0_dah = req->win0.dst_act_h;
|
||||
|
||||
win1_saw = req->win1.src_act_w;
|
||||
win1_sah = req->win1.src_act_h;
|
||||
win1_daw = req->win1.dst_act_w;
|
||||
win1_dah = req->win1.dst_act_h;
|
||||
}
|
||||
} else {
|
||||
win0_saw = req->win0.src_act_w;
|
||||
win0_sah = req->win0.src_act_h;
|
||||
win0_daw = req->win0.dst_act_h;
|
||||
win0_dah = req->win0.dst_act_w;
|
||||
}
|
||||
} else {
|
||||
win0_saw = req->win0.src_act_w;
|
||||
win0_sah = req->win0.src_act_h;
|
||||
win0_daw = req->win0.dst_act_w;
|
||||
win0_dah = req->win0.dst_act_h;
|
||||
|
||||
if (req->win1.yrgb_addr != 0) {
|
||||
win1_saw = req->win1.src_act_w;
|
||||
win1_sah = req->win1.src_act_h;
|
||||
win1_daw = req->win1.dst_act_w;
|
||||
win1_dah = req->win1.dst_act_h;
|
||||
}
|
||||
}
|
||||
|
||||
if (((win0_saw >> 3) > win0_daw) || ((win0_sah >> 3) > win0_dah)) {
|
||||
pr_info("win0 unsupported to scaling less than 1/8 times.\n");
|
||||
pr_info("win0 unsupported to scaling less than 1/8 times. src[%d, %d], dst[%d, %d]\n",
|
||||
win0_saw, win0_sah, win0_daw, win0_dah);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (((win0_daw >> 3) > win0_saw) || ((win0_dah >> 3) > win0_sah)) {
|
||||
pr_info("win0 unsupported to scaling more than 8 times.\n");
|
||||
pr_info("win0 unsupported to scaling more than 8 times. src[%d, %d], dst[%d, %d]\n",
|
||||
win0_saw, win0_sah, win0_daw, win0_dah);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (req->win1.yrgb_addr != 0) {
|
||||
win1_saw = req->win1.src_act_w;
|
||||
win1_sah = req->win1.src_act_h;
|
||||
win1_daw = req->win1.dst_act_w;
|
||||
win1_dah = req->win1.dst_act_h;
|
||||
|
||||
if (((win1_saw >> 3) > win1_daw) || ((win1_sah >> 3) > win1_dah)) {
|
||||
pr_info("win1 unsupported to scaling less than 1/8 times.\n");
|
||||
pr_info("win1 unsupported to scaling less than 1/8 times. src[%d, %d], dst[%d, %d]\n",
|
||||
win1_saw, win1_sah, win1_daw, win1_dah);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (((win1_daw >> 3) > win1_saw) || ((win1_dah >> 3) > win1_sah)) {
|
||||
pr_info("win1 unsupported to scaling more than 8 times.\n");
|
||||
pr_info("win1 unsupported to scaling more than 8 times. src[%d, %d], dst[%d, %d]\n",
|
||||
win1_saw, win1_sah, win1_daw, win1_dah);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -161,65 +161,55 @@ static bool rga_check_align(uint32_t byte_stride_align, uint32_t format, uint16_
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool rga_check_src0(const struct rga_hw_data *data,
|
||||
struct rga_img_info_t *src0)
|
||||
static bool rga_check_channel(const struct rga_hw_data *data,
|
||||
struct rga_img_info_t *img,
|
||||
const char *name, int input, int win_num)
|
||||
{
|
||||
if (!rga_check_resolution(&data->input_range, src0->act_w, src0->act_h))
|
||||
const struct rga_rect_range *range;
|
||||
|
||||
if (input)
|
||||
range = &data->input_range;
|
||||
else
|
||||
range = &data->output_range;
|
||||
|
||||
if (!rga_check_resolution(range, img->act_w, img->act_h)) {
|
||||
if (DEBUGGER_EN(MSG))
|
||||
pr_info("%s resolution check error, input range[%dx%d ~ %dx%d], [w,h] = [%d, %d]\n",
|
||||
name,
|
||||
data->input_range.min.width, data->input_range.min.height,
|
||||
data->input_range.max.width, data->input_range.max.height,
|
||||
img->act_w, img->act_h);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
if (data == &rga3_data &&
|
||||
!rga_check_resolution(&data->input_range,
|
||||
src0->act_w + src0->x_offset,
|
||||
src0->act_h + src0->y_offset))
|
||||
img->act_w + img->x_offset,
|
||||
img->act_h + img->y_offset)) {
|
||||
if (DEBUGGER_EN(MSG))
|
||||
pr_info("%s RGA3 resolution check error, input range[%dx%d ~ %dx%d], [w+x,h+y] = [%d, %d]\n",
|
||||
name,
|
||||
data->input_range.min.width, data->input_range.min.height,
|
||||
data->input_range.max.width, data->input_range.max.height,
|
||||
img->act_w + img->x_offset,
|
||||
img->act_h + img->y_offset);
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!rga_check_format(data, src0->rd_mode, src0->format, 0))
|
||||
if (!rga_check_format(data, img->rd_mode, img->format, win_num)) {
|
||||
if (DEBUGGER_EN(MSG))
|
||||
pr_info("%s format check error, mode = %#x, format = %#x\n",
|
||||
name, img->rd_mode, img->format);
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!rga_check_align(data->byte_stride_align, src0->format, src0->vir_w))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool rga_check_src1(const struct rga_hw_data *data,
|
||||
struct rga_img_info_t *src1)
|
||||
{
|
||||
if (!rga_check_resolution(&data->input_range, src1->act_w, src1->act_h))
|
||||
return false;
|
||||
|
||||
if (data == &rga3_data &&
|
||||
!rga_check_resolution(&data->input_range,
|
||||
src1->act_w + src1->x_offset,
|
||||
src1->act_h + src1->y_offset))
|
||||
return false;
|
||||
|
||||
if (!rga_check_format(data, src1->rd_mode, src1->format, 1))
|
||||
return false;
|
||||
|
||||
if (!rga_check_align(data->byte_stride_align, src1->format, src1->vir_w))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool rga_check_dst(const struct rga_hw_data *data,
|
||||
struct rga_img_info_t *dst)
|
||||
{
|
||||
if (!rga_check_resolution(&data->output_range, dst->act_w, dst->act_h))
|
||||
return false;
|
||||
|
||||
if (data == &rga3_data &&
|
||||
!rga_check_resolution(&data->output_range,
|
||||
dst->act_w + dst->x_offset,
|
||||
dst->act_h + dst->y_offset))
|
||||
return false;
|
||||
|
||||
if (!rga_check_format(data, dst->rd_mode, dst->format, 2))
|
||||
return false;
|
||||
|
||||
if (!rga_check_align(data->byte_stride_align, dst->format, dst->vir_w))
|
||||
if (!rga_check_align(data->byte_stride_align, img->format, img->vir_w)) {
|
||||
if (DEBUGGER_EN(MSG))
|
||||
pr_info("%s align check error, byte_stride_align[%d], format[%#x], vir_w[%d]\n",
|
||||
name, data->byte_stride_align, img->format, img->vir_w);
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
@@ -235,33 +225,33 @@ static bool rga_check_scale(const struct rga_hw_data *data,
|
||||
|
||||
sw = src0->act_w;
|
||||
sh = src0->act_h;
|
||||
|
||||
if ((rga_base->sina == 65536 && rga_base->cosa == 0)
|
||||
|| (rga_base->sina == -65536 && rga_base->cosa == 0)) {
|
||||
dw = dst->act_h;
|
||||
dh = dst->act_w;
|
||||
} else {
|
||||
dw = dst->act_w;
|
||||
dh = dst->act_h;
|
||||
}
|
||||
dw = dst->act_w;
|
||||
dh = dst->act_h;
|
||||
|
||||
if (sw > dw) {
|
||||
if ((sw >> data->max_downscale_factor) > dw)
|
||||
return false;
|
||||
goto check_error;
|
||||
} else if (sw < dw) {
|
||||
if ((sw << data->max_upscale_factor) < dw)
|
||||
return false;
|
||||
goto check_error;
|
||||
}
|
||||
|
||||
if (sh > dh) {
|
||||
if ((sh >> data->max_downscale_factor) > dh)
|
||||
return false;
|
||||
goto check_error;
|
||||
} else if (sh < dh) {
|
||||
if ((sh << data->max_upscale_factor) < dh)
|
||||
return false;
|
||||
goto check_error;
|
||||
}
|
||||
|
||||
return true;
|
||||
check_error:
|
||||
if (DEBUGGER_EN(MSG))
|
||||
pr_info("scale check error, scale limit[1/%d ~ %d], src[%d, %d], dst[%d, %d]\n",
|
||||
(1 << data->max_downscale_factor), (1 << data->max_upscale_factor),
|
||||
sw, sh, dw, dh);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
int rga_job_assign(struct rga_job *job)
|
||||
@@ -315,7 +305,7 @@ int rga_job_assign(struct rga_job *job)
|
||||
if (feature > 0) {
|
||||
if (!(feature & data->feature)) {
|
||||
if (DEBUGGER_EN(MSG))
|
||||
pr_info("core = %d, break on feature",
|
||||
pr_info("core = %d, break on feature\n",
|
||||
scheduler->core);
|
||||
continue;
|
||||
}
|
||||
@@ -324,20 +314,38 @@ int rga_job_assign(struct rga_job *job)
|
||||
/* only colorfill need single win (colorpalette?) */
|
||||
if (!(feature & 1)) {
|
||||
if (src1->yrgb_addr > 0) {
|
||||
if ((!(src0->rd_mode & data->win[0].rd_mode)) ||
|
||||
(!(src1->rd_mode & data->win[1].rd_mode)) ||
|
||||
(!(dst->rd_mode & data->win[2].rd_mode))) {
|
||||
if (!(src0->rd_mode & data->win[0].rd_mode)) {
|
||||
if (DEBUGGER_EN(MSG))
|
||||
pr_info("core = %d, ABC break on rd_mode",
|
||||
scheduler->core);
|
||||
pr_info("core[%#x], src0 break on rd_mode[%#x]\n",
|
||||
scheduler->core, src0->rd_mode);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!(src1->rd_mode & data->win[1].rd_mode)) {
|
||||
if (DEBUGGER_EN(MSG))
|
||||
pr_info("core[%#x], src1 break on rd_mode[%#x]\n",
|
||||
scheduler->core, src1->rd_mode);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!(dst->rd_mode & data->win[2].rd_mode)) {
|
||||
if (DEBUGGER_EN(MSG))
|
||||
pr_info("core[%#x], dst break on rd_mode[%#x]\n",
|
||||
scheduler->core, dst->rd_mode);
|
||||
continue;
|
||||
}
|
||||
} else {
|
||||
if ((!(src0->rd_mode & data->win[0].rd_mode)) ||
|
||||
(!(dst->rd_mode & data->win[2].rd_mode))) {
|
||||
if (!(src0->rd_mode & data->win[0].rd_mode)) {
|
||||
if (DEBUGGER_EN(MSG))
|
||||
pr_info("core = %d, ABB break on rd_mode",
|
||||
scheduler->core);
|
||||
pr_info("core[%#x], src break on rd_mode[%#x]\n",
|
||||
scheduler->core, src0->rd_mode);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!(dst->rd_mode & data->win[2].rd_mode)) {
|
||||
if (DEBUGGER_EN(MSG))
|
||||
pr_info("core[%#x], dst break on rd_mode[%#x]\n",
|
||||
scheduler->core, dst->rd_mode);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
@@ -349,26 +357,26 @@ int rga_job_assign(struct rga_job *job)
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!rga_check_src0(data, src0)) {
|
||||
if (!rga_check_channel(data, src0, "src0", true, 0)) {
|
||||
if (DEBUGGER_EN(MSG))
|
||||
pr_info("core = %d, break on rga_check_src0",
|
||||
pr_info("core = %d, break on src0",
|
||||
scheduler->core);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (src1->yrgb_addr > 0) {
|
||||
if (!rga_check_src1(data, src1)) {
|
||||
if (!rga_check_channel(data, src1, "src1", true, 1)) {
|
||||
if (DEBUGGER_EN(MSG))
|
||||
pr_info("core = %d, break on rga_check_src1",
|
||||
pr_info("core = %d, break on src1",
|
||||
scheduler->core);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (!rga_check_dst(data, dst)) {
|
||||
if (!rga_check_channel(data, dst, "dst", false, 2)) {
|
||||
if (DEBUGGER_EN(MSG))
|
||||
pr_info("core = %d, break on rga_check_dst",
|
||||
pr_info("core = %d, break on dst",
|
||||
scheduler->core);
|
||||
continue;
|
||||
}
|
||||
|
||||
@@ -272,7 +272,7 @@ int dmaengine_trcm_dma_guard_ctrl(struct snd_soc_component *component,
|
||||
return 0;
|
||||
|
||||
if (!en)
|
||||
return dmaengine_terminate_sync(chan);
|
||||
return dmaengine_terminate_async(chan);
|
||||
|
||||
direction = stream ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
|
||||
|
||||
@@ -304,7 +304,7 @@ static int dmaengine_trcm_trigger(struct snd_soc_component *component,
|
||||
|
||||
switch (cmd) {
|
||||
case SNDRV_PCM_TRIGGER_START:
|
||||
dmaengine_terminate_sync(prtd->dma_chan);
|
||||
dmaengine_terminate_async(prtd->dma_chan);
|
||||
ret = dmaengine_trcm_prepare_and_submit(substream);
|
||||
if (ret)
|
||||
return ret;
|
||||
@@ -318,13 +318,13 @@ static int dmaengine_trcm_trigger(struct snd_soc_component *component,
|
||||
if (runtime->info & SNDRV_PCM_INFO_PAUSE)
|
||||
dmaengine_pause(prtd->dma_chan);
|
||||
else
|
||||
dmaengine_terminate_sync(prtd->dma_chan);
|
||||
dmaengine_terminate_async(prtd->dma_chan);
|
||||
break;
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
||||
dmaengine_pause(prtd->dma_chan);
|
||||
break;
|
||||
case SNDRV_PCM_TRIGGER_STOP:
|
||||
dmaengine_terminate_sync(prtd->dma_chan);
|
||||
dmaengine_terminate_async(prtd->dma_chan);
|
||||
dmaengine_trcm_dma_guard_ctrl(component, substream->stream, 1);
|
||||
break;
|
||||
default:
|
||||
|
||||
Reference in New Issue
Block a user