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nvmem: rockchip-otp: enable ecc and ecc-check for rk3568
Change-Id: I1bc8880d7ba8c3236d51d6982bf3689063d907b9 Signed-off-by: Liang Chen <cl@rock-chips.com>
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@@ -27,6 +27,7 @@
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#define OTPC_USER_CTRL 0x0100
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#define OTPC_USER_ADDR 0x0104
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#define OTPC_USER_ENABLE 0x0108
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#define OTPC_USER_QP 0x0120
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#define OTPC_USER_Q 0x0124
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#define OTPC_INT_STATUS 0x0304
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#define OTPC_SBPI_CMD0_OFFSET 0x1000
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@@ -255,6 +256,7 @@ static int rk3568_otp_read(void *context, unsigned int offset, void *val,
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{
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struct rockchip_otp *otp = context;
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unsigned int addr_start, addr_end, addr_offset, addr_len;
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unsigned int otp_qp;
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u32 out_value;
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u8 *buf;
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int ret = 0, i = 0;
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@@ -281,7 +283,7 @@ static int rk3568_otp_read(void *context, unsigned int offset, void *val,
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goto disable_clks;
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}
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ret = px30_otp_ecc_enable(otp, false);
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ret = px30_otp_ecc_enable(otp, true);
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if (ret < 0) {
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dev_err(otp->dev, "rockchip_otp_ecc_enable err\n");
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goto disable_clks;
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@@ -299,6 +301,12 @@ static int rk3568_otp_read(void *context, unsigned int offset, void *val,
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dev_err(otp->dev, "timeout during read setup\n");
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goto read_end;
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}
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otp_qp = readl(otp->base + OTPC_USER_QP);
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if (((otp_qp & 0xc0) == 0xc0) || (otp_qp & 0x20)) {
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ret = -EIO;
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dev_err(otp->dev, "ecc check error during read setup\n");
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goto read_end;
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}
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out_value = readl(otp->base + OTPC_USER_Q);
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memcpy(&buf[i], &out_value, RK3568_NBYTES);
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i += RK3568_NBYTES;
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