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arm64: dts: rockchip: rk1808: add mipi csi dts config

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Change-Id: I79068090de87b0650da44dd0a49029b05e6b2ac5
Signed-off-by: Xu Hongfei <xuhf@rock-chips.com>
This commit is contained in:
Xu Hongfei
2019-04-18 16:52:32 +08:00
committed by Tao Huang
parent 70c49f8428
commit a9b3e6c878
1 changed files with 18 additions and 10 deletions
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28
arch/arm64/boot/dts/rockchip/rk1808.dtsi
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@@ -1434,18 +1434,14 @@
cif: cif@ffae0000 {
compatible = "rockchip,rk1808-cif";
reg = <0x0 0xffae0000 0x0 0x200>, <0x0 0xffb10000 0x0 0x100>;
reg-names = "cif_regs", "csihost_regs";
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cif-intr", "csi-intr1", "csi-intr2";
reg = <0x0 0xffae0000 0x0 0x200>;
reg-names = "cif_regs";
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cif-intr";
clocks = <&cru ACLK_CIF>, <&cru DCLK_CIF>,
<&cru HCLK_CIF>, <&cru SCLK_CIF_OUT>,
<&cru PCLK_CSI2HOST>;
<&cru HCLK_CIF>, <&cru SCLK_CIF_OUT>;
clock-names = "aclk_cif", "dclk_cif",
"hclk_cif", "sclk_cif_out",
"pclk_csi2host";
"hclk_cif", "sclk_cif_out";
resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>,
<&cru SRST_CIF_I>, <&cru SRST_CIF_D>,
<&cru SRST_CIF_PCLKIN>;
@@ -1509,6 +1505,18 @@
status = "disabled";
};
mipi_csi2: mipi-csi2@ffb10000 {
compatible = "rockchip,rk1808-mipi-csi2";
reg = <0x0 0xffb10000 0x0 0x100>;
reg-names = "csihost_regs";
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "csi-intr1", "csi-intr2";
clocks = <&cru PCLK_CSI2HOST>;
clock-names = "pclk_csi2host";
status = "disabled";
};
csi_tx: csi@ffb20000 {
compatible = "rockchip,rk1808-mipi-csi";
reg = <0x0 0xffb20000 0x0 0x500>;