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arm64: dts: ti: k3-am62a7: Correct L2 cache size to 512KB

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[ Upstream commit 438b8dc949 ]

Per AM62Ax SoC datasheet[0] L2 cache is 512KB.

[0] https://www.ti.com/lit/gpn/am62a7 Page 1.

Fixes: 5fc6b1b626 ("arm64: dts: ti: Introduce AM62A7 family of SoCs")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230320044935.2512288-2-vigneshr@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Vignesh Raghavendra
2023-03-20 10:19:35 +05:30
committed by Greg Kroah-Hartman
parent fe9dc0a264
commit a9b3ef13eb
1 changed files with 1 additions and 1 deletions
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arch/arm64/boot/dts/ti/k3-am62a7.dtsi
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@@ -96,7 +96,7 @@
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-size = <0x40000>;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
};