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[ARM] tegra: Set bit 22 in the PL310 AuxCtrl

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Duplicate Catalin Marinas' <catalin.marinas@arm.com> ARM change
6395/1 for VExpress to tegra

Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

Change-Id: I37232041c035f5153a7ad73257c6333634a5f4b8
Signed-off-by: Gary King <gking@nvidia.com>
This commit is contained in:
Gary King
2010-10-12 18:55:07 -07:00
committed by Colin Cross
parent dca2f292ae
commit aba71d0453
1 changed files with 1 additions and 1 deletions
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2
arch/arm/mach-tegra/common.c
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@@ -62,7 +62,7 @@ void __init tegra_init_cache(void)
writel(0x331, p + L2X0_TAG_LATENCY_CTRL);
writel(0x441, p + L2X0_DATA_LATENCY_CTRL);
l2x0_init(p, 0x6C080001, 0x8200c3fe);
l2x0_init(p, 0x6C480001, 0x8200c3fe);
#endif
}