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hdmitx: add hdmitx driver

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PD#138714: add hdmitx driver

Change-Id: Iffe4a2a88633d3e3d67ba1aec4c6ea5c2a912aec
Signed-off-by: Zongdong Jiao <zongdong.jiao@amlogic.com>
This commit is contained in:
Zongdong Jiao
2017-02-08 19:02:48 +08:00
parent 4dafe9905e
commit abf5acf549
56 changed files with 23139 additions and 1 deletions
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7
MAINTAINERS
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@@ -13464,6 +13464,13 @@ AMLOGIC reboot
M: Jianxin Pan <jianxin.pan@amlogic.com>
F: drivers/amlogic/reboot/*
HDMITX OUTPUT DRIVER
M: Zongdong Jiao <zongdong.jiao@amlogic.com>
S: Maintained
F: drivers/amlogic/media/vout/hdmitx/*
F: drivers/amlogic/media/vout/hdmitx/hdcp/*
F: include/linux/amlogic/media/vout/hdmi_tx/*
AMLOGIC DWC_OTG USB
M: Yue Wang <yue.wang@amlogic.com>
F: drivers/amlogic/usb/*

19
arch/arm64/boot/dts/amlogic/gxl_p212_1g.dts
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@@ -200,6 +200,25 @@
status = "okay";
};
amhdmitx: amhdmitx{
compatible = "amlogic, amhdmitx";
dev_name = "amhdmitx";
status = "okay";
vend-data = <&vend_data>;
pinctrl-names="hdmitx_hpd", "hdmitx_ddc";
pinctrl-0=<&hdmitx_hpd>;
pinctrl-1=<&hdmitx_ddc>;
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
interrupts = <0 57 1>;
interrupt-names = "hdmitx_hpd";
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */
vendor_id = <0x000000>;
product_desc = "MBox Meson Ref"; /* Max Chars: 16 */
};
};
pwm {
compatible = "amlogic, meson-pwm";
status = "okay";

19
arch/arm64/boot/dts/amlogic/gxl_p212_2g.dts
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@@ -278,6 +278,25 @@
status = "okay";
};
amhdmitx: amhdmitx{
compatible = "amlogic, amhdmitx";
dev_name = "amhdmitx";
status = "okay";
vend-data = <&vend_data>;
pinctrl-names="hdmitx_hpd", "hdmitx_ddc";
pinctrl-0=<&hdmitx_hpd>;
pinctrl-1=<&hdmitx_ddc>;
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
interrupts = <0 57 1>;
interrupt-names = "hdmitx_hpd";
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */
vendor_id = <0x000000>;
product_desc = "MBox Meson Ref"; /* Max Chars: 16 */
};
};
pwm {
compatible = "amlogic, meson-pwm";
status = "okay";

19
arch/arm64/boot/dts/amlogic/gxm_q200_2g.dts
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@@ -277,6 +277,25 @@
status = "okay";
};
amhdmitx: amhdmitx{
compatible = "amlogic, amhdmitx";
dev_name = "amhdmitx";
status = "okay";
vend-data = <&vend_data>;
pinctrl-names="hdmitx_hpd", "hdmitx_ddc";
pinctrl-0=<&hdmitx_hpd>;
pinctrl-1=<&hdmitx_ddc>;
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
interrupts = <0 57 1>;
interrupt-names = "hdmitx_hpd";
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */
vendor_id = <0x000000>;
product_desc = "MBox Meson Ref"; /* Max Chars: 16 */
};
};
pwm {
compatible = "amlogic, meson-pwm";
status = "okay";

19
arch/arm64/boot/dts/amlogic/gxm_skt.dts
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@@ -245,6 +245,25 @@
interrupts = <0 89 1>;
interrupt-names = "rdma";
};
amhdmitx: amhdmitx{
compatible = "amlogic, amhdmitx";
dev_name = "amhdmitx";
status = "okay";
vend-data = <&vend_data>;
pinctrl-names="hdmitx_hpd", "hdmitx_ddc";
pinctrl-0=<&hdmitx_hpd>;
pinctrl-1=<&hdmitx_ddc>;
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
interrupts = <0 57 1>;
interrupt-names = "hdmitx_hpd";
ranges;
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */
vendor_id = <0x000000>;
product_desc = "MBox Meson Ref"; /* Max Chars: 16 */
};
};
};
&efuse {

1
arch/arm64/configs/meson64_defconfig
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@@ -206,6 +206,7 @@ CONFIG_AMLOGIC_MEDIA_FB=y
CONFIG_AMLOGIC_MEDIA_FB_OSD_VSYNC_RDMA=y
CONFIG_AMLOGIC_MEDIA_FB_OSD2_ENABLE=y
CONFIG_AMLOGIC_MEDIA_FB_OSD2_CURSOR=y
CONFIG_AMLOGIC_HDMITX=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y

1
drivers/amlogic/media/vout/Kconfig
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@@ -17,6 +17,7 @@ if AMLOGIC_VOUT
source "drivers/amlogic/media/vout/vout_serve/Kconfig"
source "drivers/amlogic/media/vout/cvbs/Kconfig"
source "drivers/amlogic/media/vout/vdac/Kconfig"
source "drivers/amlogic/media/vout/hdmitx/Kconfig"
endif

1
drivers/amlogic/media/vout/Makefile
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@@ -1,3 +1,4 @@
obj-$(CONFIG_AMLOGIC_VOUT_SERVE) += vout_serve/
obj-$(CONFIG_AMLOGIC_CVBS_OUTPUT) += cvbs/
obj-$(CONFIG_AMLOGIC_VDAC) += vdac/
obj-$(CONFIG_AMLOGIC_HDMITX) += hdmitx/

12
drivers/amlogic/media/vout/hdmitx/Kconfig Normal file
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@@ -0,0 +1,12 @@
#
# HDMITX
#
menu "Amlogic HDMITX Module"
config AMLOGIC_HDMITX
bool "HDMITX Output Enable"
default n
help
HDMITX Output Enable
endmenu

3
drivers/amlogic/media/vout/hdmitx/Makefile Normal file
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@@ -0,0 +1,3 @@
ifdef CONFIG_AMLOGIC_HDMITX
obj-$(CONFIG_AMLOGIC_HDMITX) += hdmi_tx_20/ hdmi_common/
endif

3
drivers/amlogic/media/vout/hdmitx/hdmi_common/Makefile Normal file
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@@ -0,0 +1,3 @@
obj-y += hdmi_common.o
hdmi_common-objs := hdmi_parameters.o

2019
drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c Normal file
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File diff suppressed because it is too large Load Diff

8
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/Makefile Normal file
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@@ -0,0 +1,8 @@
obj-$(CONFIG_AMLOGIC_HDMITX) += hdmitx20.o
hdmitx20-objs := hdmi_tx_main.o hdmi_tx_video.o hdmi_tx_audio.o hdmi_tx_edid.o \
hdmi_tx_audio.o hdmi_tx_hdcp.o hdmi_tx_scdc.o \
obj-$(CONFIG_AMLOGIC_HDMITX) += hw/ hdcp22/
#EXTRA_CFLAGS += -O2

49
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdcp22/ESMHostLibDriverErrors.h Normal file
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@@ -0,0 +1,49 @@
/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdcp22/ESMHostLibDriverErrors.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef _ESMDRIVERERROR_H_
#define _ESMDRIVERERROR_H_
/**
* \defgroup HostLibErrors General Library Errors
*
* The following are error code definitions produced
* by the API library.
*
* \addtogroup HostLibErrors
* @{
*
*/
#define ESM_HL_DRIVER_SUCCESS 0
#define ESM_HL_DRIVER_FAILED (-1)
#define ESM_HL_DRIVER_NO_MEMORY (-2)
#define ESM_HL_DRIVER_NO_ACCESS (-3)
#define ESM_HL_DRIVER_INVALID_PARAM (-4)
#define ESM_HL_DRIVER_TOO_MANY_ESM_DEVICES (-5)
#define ESM_HL_DRIVER_USER_DEFINED_ERROR (-6)
/* anything beyond this error code is user defined */
/* End of APIErrors group */
/**
* @}
*/
/**
* @}
*/
#endif

167
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdcp22/ESMHostTypes.h Normal file
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@@ -0,0 +1,167 @@
/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdcp22/ESMHostTypes.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef _ESMHOSTTYPES_H_
#define _ESMHOSTTYPES_H_
#include "elliptic_std_def.h"
#include "elliptic_system_types.h"
/* return type for all functions */
#define ESM_STATUS ELP_STATUS
/**
* \defgroup InitFlags Initialization Flags
*
* Options which can be set when calling ESM_Initialize().
*
* \addtogroup InitFlags
* @{
*/
#define ESM_INIT_FLAG_IRQ_SUPPORTED (1ul << 0)
/**
* @}
*/
/**
* \defgroup LogTypes Log message types
*
* These are the defined log message types.
*
* \addtogroup LogTypes
* @{
*/
#define ESM_LOG_TYPE_TEXT 0xfd /* Normal text log message. */
#define ESM_LOG_TYPE_BINARY 0xfc /* Binary dump message. */
/**
* @}
*/
/**
* \details
*
* This structure contains the ESM's last internal status when queried.
*
*/
struct esm_status_t {
/**
* The ESM Exception vector has the following bitfields:
*
* <table>
* <tr align="center">
* <td><b>HW/SW</b></td>
* <td><b>Exception Line Number</b></td>
* <td><b>Exception Flag</b></td>
* <td><b>Type</b></td>
* </tr>
* <tr>
* <td>Bit 31<br>hardware = 1, software = 0</td>
* <td>Bits 30..10</td>
* <td>Bits 9..1<br>See \ref ExFlagDefines</td>
* <td>Bit 0<br>notify = 1, abort = 0</td>
* </tr>
* </table>
*/
uint32_t esm_exception;
/* Indicates that the synchronization lost. */
uint32_t esm_sync_lost;
/* Indicates that the last AKE Start command was passed. */
uint32_t esm_auth_pass;
/* Indicates that the last AKE Start command has failed. */
uint32_t esm_auth_fail;
};
/**
* \details
*
* This structure will be filled when ESM firmware successfully started
* and it contains ESM buffers configuration values.
*
*/
struct esm_config_t {
/* Indicates what ESM firmware running: 0-unknown; 1-RX; 2-TX. */
uint32_t esm_type;
/* Indicates maximum size of a topology slot memory. */
uint32_t topo_buffer_size;
/* Indicates amount of topology slot memories. */
uint8_t topo_slots;
/* Indicates maximum size of the topology seed memory. */
uint8_t topo_seed_buffer_size;
/* Indicates maximum size of the logging memory. */
uint32_t log_buffer_size;
/* Indicates maximum size of the mailbox memory. */
uint32_t mb_buffer_size;
/* Indicates maximum size of the exceptions memory. */
uint32_t exceptions_buffer_size;
/* Indicates maximum size of the TX SRM memory. */
uint32_t srm_buffer_size;
/* Indicates maximum size of the TX Pairing memory.*/
uint32_t pairing_buffer_size;
};
/**
* \details
*
* This structure contains a text log message which can be displayed
* directly to the user.
*/
struct esm_logmsg_text_t {
char *file; /* Firmware source filename. */
char *msg; /* Human-readable log message. */
uint16_t line; /* Firmware source line number. */
};
struct esm_logmsg_bin_t {
char *msg; /* Human-readable description. */
uint8_t *data; /* Pointer to first byte of data. */
uint16_t datalen; /* Number of data bytes. */
};
/**
* \details
*
* This structure contains a parsed log message from the ESM. The ESM
* has different types of log messages, which are distinguished by the
* type value. The actual message (which depends on the type) can be
* accessed through the appropriate union member.
*/
struct esm_logmsg_t {
/* Raw (unparsed) message length (in bytes). */
uint16_t rawlen;
/* Type of log message.
* See \ref LogTypes for a list of supported message types.
*/
uint8_t type;
/* Log message ID (-1 if no ID). */
int32_t id;
/* Pointer to raw (unparsed) message. */
uint8_t *raw;
union {
/* Normal text log message.
* Only valid if type is #ESM_LOG_TYPE_TEXT.
*/
struct esm_logmsg_text_t *text;
/*Binary dump message.
* Only valid if type is #ESM_LOG_TYPE_BINARY.
*/
struct esm_logmsg_bin_t *bin;
} u; /* Union for decoded message data. */
};
#endif

1
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdcp22/Makefile Normal file
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@@ -0,0 +1 @@
obj-y += hdcp_main.o

78
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdcp22/elliptic_std_def.h Normal file
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@@ -0,0 +1,78 @@
/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdcp22/elliptic_std_def.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __ELLIPTIC_STD_DEF_H__
#define __ELLIPTIC_STD_DEF_H__
#ifndef __KERNEL__
/**
* \defgroup CALDef Common Definitions
*
* This section defines the common shared types
*
* \addtogroup CALDef
* @{
*
*/
/**
* \defgroup SysStdTypes Standard Types
* This section defines the common SHARED STANDARD types
* \addtogroup SysStdTypes
* @{
*
*/
/**
* \ingroup SysStdTypes Standard Types
* include <stddef.h>\n
* > - C89 compliant: if this is not available then add your definition here
*
*/
/* C89 compliant - if this is not available then add your definition here */
#include <stddef.h>
/**
* \ingroup SysStdTypes Standard Types
* include <stdint.h>\n
* > - C99 compliant: if this is not available then add your definition here
*
*/
/* C99 compliant - if this is not available then add your definition here */
#include <stdint.h>
/**
* \ingroup SysStdTypes Standard Types
* include <stdarg.h>\n
* > - C89 compliant: if this is not available then add your definition here
*
*/
/* C89 compliant - if this is not available then add your definition here */
#include <stdarg.h>
/**
* @}
*/
/**
* @}
*/
#else
#include <linux/types.h>
#include <linux/kernel.h>
#endif
#endif /* __ELLIPTIC_STD_DEF_H__ */

79
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdcp22/elliptic_system_types.h Normal file
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@@ -0,0 +1,79 @@
/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdcp22/elliptic_system_types.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __ELLIPTIC_SYSTEM_TYPE_H__
#define __ELLIPTIC_SYSTEM_TYPE_H__
/**
* \defgroup CALDef Common Definitions
*
* This section defines the common shared types
*
* \addtogroup CALDef
* \{
*
*/
/**
* \defgroup SysTypes System Types
*
* This section defines the common SHARED SYSTEM types
*
* \addtogroup SysTypes
* \{
*
*/
/* System types definitions. */
#define ELP_STATUS int16_t
#define ELP_SYSTEM_INFO int16_t
#define ELP_SYSTEM_BIG_ENDIAN 0
#define ELP_SYSTEM_LITLLE_ENDIAN 1
/* PRNG definitions. */
#define PRINT_FUNC printf_ptr
#define PRINT_FUNC_DECL int32_t (*PRINT_FUNC)(const void *str, ...)
#define PRNG_FUNC prng
#define PRNG_FUNC2 prng2
#define PRNG_FUNC_DECL uint8_t (*PRNG_FUNC)(void *, void *, uint8_t)
#define PRNG_FUNC2_DECL uint32_t (*PRNG_FUNC2)(void *, void *, uint32_t)
struct elp_std_prng_info {
void *prng_inst;
PRNG_FUNC_DECL;
};
struct elp_std_prng_info2 {
void *prng_inst;
PRNG_FUNC2_DECL;
};
#define ELP_STD_PRNG_INFO elp_std_prng_info
#define ELP_STD_PRNG_INFO2 elp_std_prng_info2
/**
* \}
*/
/**
* \}
*/
#endif

1213
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdcp22/hdcp_main.c Normal file
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File diff suppressed because it is too large Load Diff

152
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdcp22/host_driver_linux_if.h Normal file
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@@ -0,0 +1,152 @@
/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdcp22/host_driver_linux_if.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef _HOST_LIB_DRIVER_LINUX_IF_H_
#define _HOST_LIB_DRIVER_LINUX_IF_H_
#ifdef __KERNEL__
#include <linux/ioctl.h>
#else
#include <sys/ioctl.h>
#endif
#include "ESMHostTypes.h"
#include "ESMHostLibDriverErrors.h"
/* ESM_HLD_IOCTL_LOAD_CODE */
struct esm_hld_ioctl_load_code {
uint8_t *code;
uint32_t code_size;
ESM_STATUS returned_status;
};
struct compact_esm_hld_ioctl_load_code {
compat_uptr_t code;
uint32_t code_size;
ESM_STATUS returned_status;
};
/* ESM_HLD_IOCTL_GET_CODE_PHYS_ADDR */
struct esm_hld_ioctl_get_code_phys_addr {
uint32_t returned_phys_addr;
ESM_STATUS returned_status;
};
/* ESM_HLD_IOCTL_GET_DATA_PHYS_ADDR */
struct esm_hld_ioctl_get_data_phys_addr {
uint32_t returned_phys_addr;
ESM_STATUS returned_status;
};
/* ESM_HLD_IOCTL_GET_DATA_SIZE */
struct esm_hld_ioctl_get_data_size {
uint32_t returned_data_size;
ESM_STATUS returned_status;
};
/* ESM_HLD_IOCTL_HPI_READ */
struct esm_hld_ioctl_hpi_read {
uint32_t offset;
uint32_t returned_data;
ESM_STATUS returned_status;
};
/* ESM_HLD_IOCTL_HPI_WRITE */
struct esm_hld_ioctl_hpi_write {
uint32_t offset;
uint32_t data;
ESM_STATUS returned_status;
};
/* ESM_HLD_IOCTL_DATA_READ */
struct esm_hld_ioctl_data_read {
uint32_t offset;
uint32_t nbytes;
uint8_t *dest_buf;
ESM_STATUS returned_status;
};
struct compact_esm_hld_ioctl_data_read {
uint32_t offset;
uint32_t nbytes;
compat_uptr_t dest_buf;
ESM_STATUS returned_status;
};
/* ESM_HLD_IOCTL_DATA_WRITE */
struct esm_hld_ioctl_data_write {
uint32_t offset;
uint32_t nbytes;
uint8_t *src_buf;
ESM_STATUS returned_status;
};
struct compact_esm_hld_ioctl_data_write {
uint32_t offset;
uint32_t nbytes;
compat_uptr_t src_buf;
ESM_STATUS returned_status;
};
/* ESM_HLD_IOCTL_DATA_SET */
struct esm_hld_ioctl_data_set {
uint32_t offset;
uint32_t nbytes;
uint8_t data;
ESM_STATUS returned_status;
};
/* ESM_HLD_IOCTL_ESM_OPEN */
struct esm_hld_ioctl_esm_open {
uint32_t hpi_base;
uint32_t code_base;
uint32_t code_size;
uint32_t data_base;
uint32_t data_size;
ESM_STATUS returned_status;
};
/* IOCTL commands */
#define ESM_HLD_IOC_MAGIC 'E'
#define ESM_HLD_IOCTL_LOAD_CODE \
_IOWR(ESM_HLD_IOC_MAGIC, 1000, struct esm_hld_ioctl_load_code)
#define ESM_HLD_IOCTL_GET_CODE_PHYS_ADDR \
_IOR(ESM_HLD_IOC_MAGIC, 1001, struct esm_hld_ioctl_get_code_phys_addr)
#define ESM_HLD_IOCTL_GET_DATA_PHYS_ADDR \
_IOR(ESM_HLD_IOC_MAGIC, 1002, struct esm_hld_ioctl_get_data_phys_addr)
#define ESM_HLD_IOCTL_GET_DATA_SIZE \
_IOR(ESM_HLD_IOC_MAGIC, 1003, struct esm_hld_ioctl_get_data_size)
#define ESM_HLD_IOCTL_HPI_READ \
_IOWR(ESM_HLD_IOC_MAGIC, 1004, struct esm_hld_ioctl_hpi_read)
#define ESM_HLD_IOCTL_HPI_WRITE \
_IOWR(ESM_HLD_IOC_MAGIC, 1005, struct esm_hld_ioctl_hpi_write)
#define ESM_HLD_IOCTL_DATA_READ \
_IOWR(ESM_HLD_IOC_MAGIC, 1006, struct esm_hld_ioctl_data_read)
#define ESM_HLD_IOCTL_DATA_WRITE \
_IOWR(ESM_HLD_IOC_MAGIC, 1007, struct esm_hld_ioctl_data_write)
#define ESM_HLD_IOCTL_DATA_SET \
_IOWR(ESM_HLD_IOC_MAGIC, 1008, struct esm_hld_ioctl_data_set)
#define ESM_HLD_IOCTL_ESM_OPEN \
_IOWR(ESM_HLD_IOC_MAGIC, 1009, struct esm_hld_ioctl_esm_open)
#define ESM_HLD_IOCTL_LOAD_CODE32 \
_IOWR(ESM_HLD_IOC_MAGIC, 1000, struct compact_esm_hld_ioctl_load_code)
#define ESM_HLD_IOCTL_DATA_READ32 \
_IOWR(ESM_HLD_IOC_MAGIC, 1006, struct compact_esm_hld_ioctl_data_read)
#define ESM_HLD_IOCTL_DATA_WRITE32 \
_IOWR(ESM_HLD_IOC_MAGIC, 1007, struct compact_esm_hld_ioctl_data_write)
#endif /* _HOST_LIB_DRIVER_LINUX_IF_H_ */

238
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_audio.c Normal file
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/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_audio.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/version.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/mm.h>
#include <linux/major.h>
#include <linux/platform_device.h>
#include <linux/mutex.h>
#include <linux/cdev.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_info_global.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_compliance.h>
#undef PCM_USE_INFOFRAME
static const unsigned char channel_status_freq[] = {
0x0,
0x3, /*32K*/
0x0, /*44.1k*/
0x2, /*48k*/
0x8, /*88.2k*/
0xa, /*96k*/
0xc, /*176.4k*/
0xe, /*192k*/
};
static const unsigned char channel_status_sample_word_length[] = {
0x0,
0x2, /*16 bits*/
0x3, /*20 bits*/
0xb /*24 bits*/
};
void hdmi_tx_set_N_CTS(unsigned int N_value, unsigned int CTS)
{
}
static void hdmi_tx_construct_aud_packet(
struct hdmitx_audpara *audio_param, unsigned char *AUD_DB,
unsigned char *CHAN_STAT_BUF, int hdmi_ch)
{
#ifndef PCM_USE_INFOFRAME
if (audio_param->type == CT_PCM) {
hdmi_print(INF, AUD "Audio Type: PCM\n");
if (AUD_DB) {
/*Note: HDMI Spec V1.4 Page 154*/
if ((audio_param->channel_num == CC_2CH) ||
(audio_param->channel_num ==
CC_REFER_TO_STREAM))
AUD_DB[0] = 0;
else
AUD_DB[0] = (0<<4)|(audio_param->channel_num);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
AUD_DB[2] = 0x0;
if (audio_param->channel_num == CC_6CH)
AUD_DB[3] = 0xb;
else if (audio_param->channel_num == CC_8CH) {
if (hdmi_ch == CC_6CH)
AUD_DB[3] = 0x0b;
else
AUD_DB[3] = 0x13;
} else
AUD_DB[3] = 0;
AUD_DB[4] = 0;
}
if (CHAN_STAT_BUF) {
CHAN_STAT_BUF[2] = 0x10|(audio_param->channel_num+1);
CHAN_STAT_BUF[24+2] = 0x20|(audio_param->channel_num+1);
CHAN_STAT_BUF[3] = CHAN_STAT_BUF[24+3] =
channel_status_freq[audio_param->sample_rate];
CHAN_STAT_BUF[4] = CHAN_STAT_BUF[24+4] =
channel_status_sample_word_length[
audio_param->sample_size]|
((~channel_status_freq[
audio_param->sample_rate])<<4);
}
} else if (audio_param->type == CT_AC_3) {
hdmi_print(INF, AUD "Audio Type: AC3\n");
if (AUD_DB) {
AUD_DB[0] = (CT_AC_3<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
AUD_DB[3] = 0;
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_MPEG1) {
hdmi_print(INF, AUD "Audio Type: MPEG1\n");
if (AUD_DB) {
AUD_DB[0] = (CT_MPEG1<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
AUD_DB[3] = 0;
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_MP3) {
hdmi_print(INF, AUD "Audio Type: MP3\n");
if (AUD_DB) {
AUD_DB[0] = (CT_MP3<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
AUD_DB[3] = 0;
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_MPEG2) {
hdmi_print(INF, AUD "Audio Type: MPEG2\n");
if (AUD_DB) {
AUD_DB[0] = (CT_MPEG2<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
AUD_DB[3] = 0;
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_AAC) {
hdmi_print(INF, AUD "Audio Type: AAC\n");
if (AUD_DB) {
AUD_DB[0] = (CT_AAC<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
AUD_DB[3] = 0;
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_DTS) {
hdmi_print(INF, AUD "Audio Type: DTS\n");
if (AUD_DB) {
AUD_DB[0] = (CT_DTS<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
AUD_DB[3] = 0;
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_ATRAC) {
hdmi_print(INF, AUD "Audio Type: ATRAC\n");
if (AUD_DB) {
AUD_DB[0] = (CT_ATRAC<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
AUD_DB[3] = 0;
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_ONE_BIT_AUDIO) {
hdmi_print(INF, AUD "Audio Type: One Bit Audio\n");
if (AUD_DB) {
AUD_DB[0] = (CT_ONE_BIT_AUDIO<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
AUD_DB[3] = 0;
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_DOLBY_D) {
hdmi_print(INF, AUD "Audio Type: Dobly Digital +\n");
if (AUD_DB) {
AUD_DB[0] =
(FS_REFER_TO_STREAM<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
AUD_DB[3] = 0;
AUD_DB[4] = 0;
}
if (CHAN_STAT_BUF) {
CHAN_STAT_BUF[0] = CHAN_STAT_BUF[24+0] = 0x2;
CHAN_STAT_BUF[3] = CHAN_STAT_BUF[24+3] = 0x1e;
CHAN_STAT_BUF[4] = CHAN_STAT_BUF[24+4] = 0x1;
}
} else if (audio_param->type == CT_DTS_HD) {
hdmi_print(INF, AUD "Audio Type: DTS-HD\n");
if (AUD_DB) {
AUD_DB[0] =
(FS_REFER_TO_STREAM<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
AUD_DB[3] = 0;
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_MAT) {
hdmi_print(INF, AUD "Audio Type: MAT(MLP)\n");
if (AUD_DB) {
AUD_DB[0] = (CT_MAT<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
AUD_DB[3] = 0;
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_DST) {
hdmi_print(INF, AUD "Audio Type: DST\n");
if (AUD_DB) {
AUD_DB[0] = (CT_DST<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
AUD_DB[3] = 0;
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_WMA) {
hdmi_print(INF, AUD "Audio Type: WMA Pro\n");
if (AUD_DB) {
AUD_DB[0] = (CT_WMA<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
AUD_DB[3] = 0;
AUD_DB[4] = 0;
}
} else {
;
}
AUD_DB[0] = AUD_DB[0] & 0xf;/*bit[7:4] always set to 0 in HDMI*/
AUD_DB[1] = 0; /*always set to 0 in HDMI*/
#endif
}
int hdmitx_set_audio(struct hdmitx_dev *hdmitx_device,
struct hdmitx_audpara *audio_param, int hdmi_ch)
{
int i, ret = -1;
unsigned char AUD_DB[32];
unsigned char CHAN_STAT_BUF[24*2];
for (i = 0; i < 32; i++)
AUD_DB[i] = 0;
for (i = 0; i < (24*2); i++)
CHAN_STAT_BUF[i] = 0;
if (hdmitx_device->HWOp.SetAudMode(hdmitx_device,
audio_param) >= 0) {
hdmi_tx_construct_aud_packet(audio_param, AUD_DB,
CHAN_STAT_BUF, hdmi_ch);
hdmitx_device->HWOp.SetAudioInfoFrame(AUD_DB, CHAN_STAT_BUF);
ret = 0;
}
return ret;
}

2406
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c Normal file
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155
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_hdcp.c Normal file
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/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_hdcp.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/version.h>
#include <linux/module.h>
#include <linux/irq.h>
#include <linux/types.h>
#include <linux/input.h>
#include <linux/kernel.h>
#include <linux/kthread.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/mm.h>
#include <linux/major.h>
#include <linux/platform_device.h>
#include <linux/mutex.h>
#include <linux/cdev.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <linux/spinlock_types.h>
#include <linux/extcon.h>
/* #include <mach/am_regs.h> */
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_info_global.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
/* #include <mach/hdmi_tx_reg.h> */
#include "hdmi_tx_hdcp.h"
/*
* hdmi_tx_hdcp.c
* version 1.1
*/
/* android ics switch device */
static struct extcon_dev hdcp_dev = {
.name = "hdcp",
};
/* For most cases, we don't use HDCP
* If using HDCP, need add follow command in boot/init.rc and
* recovery/boot/init.rc
* write /sys/module/hdmitx/parameters/hdmi_output_force 0
*/
static int hdmi_output_force = 1;
static int hdmi_authenticated;
static int hdmi_hdcp_process = 1;
/* Notic: the HDCP key setting has been moved to uboot
* On MBX project, it is too late for HDCP get from
* other devices
*/
/* verify ksv, 20 ones and 20 zeroes */
int hdcp_ksv_valid(unsigned char *dat)
{
int i, j, one_num = 0;
for (i = 0; i < 5; i++) {
for (j = 0; j < 8; j++) {
if ((dat[i] >> j) & 0x1)
one_num++;
}
}
return one_num == 20;
}
static struct timer_list hdcp_monitor_timer;
static void hdcp_monitor_func(unsigned long arg)
{
/* static int hdcp_auth_flag = 0; */
struct hdmitx_dev *hdev = (struct hdmitx_dev *)hdcp_monitor_timer.data;
if ((hdev->HWOp.Cntl) && (hdev->log & (HDMI_LOG_HDCP)))
hdev->HWOp.Cntl(hdev, HDMITX_HDCP_MONITOR, 1);
mod_timer(&hdcp_monitor_timer, jiffies + 2 * HZ);
}
static int hdmitx_hdcp_task(void *data)
{
struct hdmitx_dev *hdev = (struct hdmitx_dev *)data;
init_timer(&hdcp_monitor_timer);
hdcp_monitor_timer.data = (ulong) data;
hdcp_monitor_timer.function = hdcp_monitor_func;
hdcp_monitor_timer.expires = jiffies + HZ;
add_timer(&hdcp_monitor_timer);
while (hdev->hpd_event != 0xff) {
hdmi_authenticated = hdev->HWOp.CntlDDC(hdev,
DDC_HDCP_GET_AUTH, 0);
extcon_set_state(&hdcp_dev, 0, hdmi_authenticated); //TO_DO___49
msleep_interruptible(200);
}
return 0;
}
static int __init hdmitx_hdcp_init(void)
{
struct hdmitx_dev *hdev = get_hdmitx_device();
hdmi_print(IMP, SYS "hdmitx_hdcp_init\n");
if (hdev->hdtx_dev == NULL) {
hdmi_print(IMP, SYS "exit for null device of hdmitx!\n");
return -ENODEV;
}
extcon_dev_register(&hdcp_dev);
hdev->task_hdcp = kthread_run(hdmitx_hdcp_task, (void *)hdev,
"kthread_hdcp");
return 0;
}
static void __exit hdmitx_hdcp_exit(void)
{
extcon_dev_unregister(&hdcp_dev);
}
MODULE_PARM_DESC(hdmi_authenticated, "\n hdmi_authenticated\n");
module_param(hdmi_authenticated, int, 0444);
MODULE_PARM_DESC(hdmi_hdcp_process, "\n hdmi_hdcp_process\n");
module_param(hdmi_hdcp_process, int, 0664);
MODULE_PARM_DESC(hdmi_output_force, "\n hdmi_output_force\n");
module_param(hdmi_output_force, int, 0664);
module_init(hdmitx_hdcp_init);
module_exit(hdmitx_hdcp_exit);
MODULE_DESCRIPTION("AMLOGIC HDMI TX HDCP driver");
MODULE_LICENSE("GPL");

35
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_hdcp.h Normal file
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/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_hdcp.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __HDMI_TX_HDCP_H
#define __HDMI_TX_HDCP_H
/*
* hdmi_tx_hdcp.c
* version 1.0
*/
/* Notic: the HDCP key setting has been moved to uboot
* On MBX project, it is too late for HDCP get from
* other devices
*/
/* int task_tx_key_setting(unsigned force_wrong); */
int hdcp_ksv_valid(unsigned char *dat);
#endif

3064
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c Normal file
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59
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_scdc.c Normal file
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/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_scdc.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/delay.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_ddc.h>
static struct timer_list scdc_tmds_cfg_timer;
static int cnt;
static void tmds_config(unsigned long arg)
{
struct hdmitx_dev *hdev = (struct hdmitx_dev *)arg;
uint8_t st = 0;
/* TMDS 1/40 & Scramble */
scdc_wr_sink(TMDS_CFG, hdev->para->tmds_clk_div40 ? 0x3 : 0);
scdc_wr_sink(TMDS_CFG, hdev->para->tmds_clk_div40 ? 0x3 : 0);
scdc_rd_sink(SCRAMBLER_ST, &st);
cnt++;
if ((hdev->para->tmds_clk_div40) && (st & 0x1)) {
pr_info("hdmitx20: rx scrambler status\n");
return;
}
if ((hdev->para->tmds_clk_div40) && (cnt < 3))
mod_timer(&scdc_tmds_cfg_timer, jiffies + HZ / 2);
else
cnt = 0;
}
void scdc_config(void *hdev)
{
static int init_flag;
if (!init_flag) {
init_flag = 1;
init_timer(&scdc_tmds_cfg_timer);
scdc_tmds_cfg_timer.data = (ulong)hdev;
scdc_tmds_cfg_timer.function = tmds_config;
scdc_tmds_cfg_timer.expires = jiffies;
add_timer(&scdc_tmds_cfg_timer);
return;
}
mod_timer(&scdc_tmds_cfg_timer, jiffies);
}

774
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_video.c Normal file
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/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_video.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/version.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/mm.h>
#include <linux/major.h>
#include <linux/platform_device.h>
#include <linux/mutex.h>
#include <linux/cdev.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_info_global.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_compliance.h>
static unsigned char hdmi_output_rgb;
static void hdmitx_set_spd_info(struct hdmitx_dev *hdmitx_device);
static void hdmi_set_vend_spec_infofram(struct hdmitx_dev *hdmitx_device,
enum hdmi_vic VideoCode);
static struct hdmitx_vidpara hdmi_tx_video_params[] = {
{
.VIC = HDMI_640x480p60,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_4_3,
.cc = CC_ITU601,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_480p60,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_4_3,
.cc = CC_ITU601,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_480p60_16x9,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU601,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_480p60_16x9_rpt,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = HDMI_4_TIMES_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU601,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_720p60,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_1080i60,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_480i60,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = HDMI_2_TIMES_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_4_3,
.cc = CC_ITU601,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_480i60_16x9,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = HDMI_2_TIMES_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU601,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_480i60_16x9_rpt,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = HDMI_4_TIMES_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU601,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_1440x480p60,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_4_3,
.cc = CC_ITU601,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_1080p60,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_576p50,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_4_3,
.cc = CC_ITU601,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_576p50_16x9,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU601,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_576p50_16x9_rpt,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = HDMI_4_TIMES_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU601,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_720p50,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_1080i50,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_576i50,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = HDMI_2_TIMES_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_4_3,
.cc = CC_ITU601,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_576i50_16x9,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = HDMI_2_TIMES_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU601,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_576i50_16x9_rpt,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = HDMI_4_TIMES_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU601,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_1080p50,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_1080p24,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_1080p25,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_1080p30,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_4k2k_30,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_4k2k_25,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_4k2k_24,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_4k2k_smpte_24,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_4096x2160p25_256x135,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_4096x2160p30_256x135,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_4096x2160p50_256x135,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_4096x2160p60_256x135,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_4k2k_60,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_4k2k_50,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_4k2k_60,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_4k2k_50,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_4k2k_60,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_4k2k_50,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_4k2k_60_y420,
.color_prefer = COLORSPACE_YUV420,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_4k2k_50_y420,
.color_prefer = COLORSPACE_YUV420,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_4k2k_smpte_60_y420,
.color_prefer = COLORSPACE_YUV420,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_4k2k_smpte_50_y420,
.color_prefer = COLORSPACE_YUV420,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = TV_ASPECT_RATIO_16_9,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
};
static struct hdmitx_vidpara *hdmi_get_video_param(
enum hdmi_vic VideoCode)
{
struct hdmitx_vidpara *video_param = NULL;
int i;
int count = ARRAY_SIZE(hdmi_tx_video_params);
for (i = 0; i < count; i++) {
if (VideoCode == hdmi_tx_video_params[i].VIC)
break;
}
if (i < count)
video_param = &(hdmi_tx_video_params[i]);
return video_param;
}
static void hdmi_tx_construct_avi_packet(
struct hdmitx_vidpara *video_param, char *AVI_DB)
{
unsigned char color, bar_info, aspect_ratio, cc, ss, sc, ec = 0;
ss = video_param->ss;
bar_info = video_param->bar_info;
if (video_param->color == COLORSPACE_YUV444)
color = 2;
else if (video_param->color == COLORSPACE_YUV422)
color = 1;
else
color = 0;
AVI_DB[0] = (ss) | (bar_info << 2) | (1<<4) | (color << 5);
aspect_ratio = video_param->aspect_ratio;
cc = video_param->cc;
/*HDMI CT 7-24*/
AVI_DB[1] = 8 | (aspect_ratio << 4) | (cc << 6);
sc = video_param->sc;
if (video_param->cc == CC_ITU601)
ec = 0;
if (video_param->cc == CC_ITU709)
/*according to CEA-861-D, all other values are reserved*/
ec = 1;
AVI_DB[2] = (sc) | (ec << 4);
AVI_DB[3] = video_param->VIC;
if ((video_param->VIC == HDMI_4k2k_30) ||
(video_param->VIC == HDMI_4k2k_25) ||
(video_param->VIC == HDMI_4k2k_24) ||
(video_param->VIC == HDMI_4k2k_smpte_24))
/*HDMI Spec V1.4b P151*/
AVI_DB[3] = 0;
AVI_DB[4] = video_param->repeat_time;
}
/************************************
* hdmitx protocol level interface
*************************************/
void hdmitx_init_parameters(struct hdmitx_info *info)
{
memset(info, 0, sizeof(struct hdmitx_info));
info->video_out_changing_flag = 1;
info->audio_flag = 1;
info->audio_info.type = CT_REFER_TO_STREAM;
info->audio_info.format = AF_I2S;
info->audio_info.fs = FS_44K1;
info->audio_info.ss = SS_16BITS;
info->audio_info.channels = CC_2CH;
info->audio_out_changing_flag = 1;
info->auto_hdcp_ri_flag = 1;
info->hw_sha_calculator_flag = 1;
}
/*
* HDMI Identifier = 0x000c03
* If not, treated as a DVI Device
*/
static int is_dvi_device(struct rx_cap *pRXCap)
{
if (pRXCap->IEEEOUI != 0x000c03)
return 1;
else
return 0;
}
void hdmitx_output_rgb(void)
{
hdmi_output_rgb = 1;
}
int hdmitx_set_display(struct hdmitx_dev *hdev, enum hdmi_vic VideoCode)
{
struct hdmitx_vidpara *param = NULL;
enum hdmi_vic vic;
int i, ret = -1;
unsigned char AVI_DB[32];
unsigned char AVI_HB[32];
AVI_HB[0] = TYPE_AVI_INFOFRAMES;
AVI_HB[1] = AVI_INFOFRAMES_VERSION;
AVI_HB[2] = AVI_INFOFRAMES_LENGTH;
for (i = 0; i < 32; i++)
AVI_DB[i] = 0;
vic = hdev->HWOp.GetState(hdev, STAT_VIDEO_VIC, 0);
hdmi_print(IMP, SYS "already init VIC = %d Now VIC = %d\n",
vic, VideoCode);
if ((vic != HDMI_Unknown) && (vic == VideoCode)) {
hdev->cur_VIC = vic;
/* return 1; */
}
param = hdmi_get_video_param(VideoCode);
hdev->cur_video_param = param;
if (param) {
param->color = param->color_prefer;
if (hdmi_output_rgb) {
param->color = COLORSPACE_RGB444;
} else {
/* HDMI CT 7-24 Pixel Encoding
* YCbCr to YCbCr Sink
*/
switch (hdev->RXCap.native_Mode & 0x30) {
case 0x20:/*bit5==1, then support YCBCR444 + RGB*/
case 0x30:
param->color = COLORSPACE_YUV444;
break;
case 0x10:/*bit4==1, then support YCBCR422 + RGB*/
param->color = COLORSPACE_YUV422;
break;
default:
param->color = COLORSPACE_RGB444;
}
/* For Y420 modes */
switch (VideoCode) {
case HDMI_3840x2160p50_16x9_Y420:
case HDMI_3840x2160p60_16x9_Y420:
case HDMI_4096x2160p50_256x135_Y420:
case HDMI_4096x2160p60_256x135_Y420:
param->color = COLORSPACE_YUV420;
break;
default:
break;
}
if (param->color == COLORSPACE_RGB444) {
hdev->para->cs = hdev->cur_video_param->color;
pr_info("hdmitx: rx edid only support RGB format\n");
}
}
if (hdev->HWOp.SetDispMode(hdev) >= 0) {
/* HDMI CT 7-33 DVI Sink, no HDMI VSDB nor any
* other VSDB, No GB or DI expected
* TMDS_MODE[hdmi_config]
* 0: DVI Mode 1: HDMI Mode
*/
if (is_dvi_device(&hdev->RXCap)) {
hdmi_print(1, "Sink is DVI device\n");
hdev->HWOp.CntlConfig(hdev,
CONF_HDMI_DVI_MODE, DVI_MODE);
} else {
hdmi_print(1, "Sink is HDMI device\n");
hdev->HWOp.CntlConfig(hdev,
CONF_HDMI_DVI_MODE, HDMI_MODE);
}
hdmi_tx_construct_avi_packet(param, (char *)AVI_DB);
if ((VideoCode == HDMI_4k2k_30) ||
(VideoCode == HDMI_4k2k_25) ||
(VideoCode == HDMI_4k2k_24) ||
(VideoCode == HDMI_4k2k_smpte_24))
hdmi_set_vend_spec_infofram(hdev, VideoCode);
else if ((!hdev->flag_3dfp) && (!hdev->flag_3dtb) &&
(!hdev->flag_3dss))
hdmi_set_vend_spec_infofram(hdev, 0);
else
;
ret = 0;
}
}
hdmitx_set_spd_info(hdev);
#if 0
hdmitx_special_handler_video(hdev);
#endif
return ret;
}
static void hdmi_set_vend_spec_infofram(struct hdmitx_dev *hdev,
enum hdmi_vic VideoCode)
{
int i;
unsigned char VEN_DB[6];
unsigned char VEN_HB[3];
VEN_HB[0] = 0x81;
VEN_HB[1] = 0x01;
VEN_HB[2] = 0x5;
for (i = 0; i < 0x6; i++)
VEN_DB[i] = 0;
VEN_DB[0] = 0x03;
VEN_DB[1] = 0x0c;
VEN_DB[2] = 0x00;
VEN_DB[3] = 0x20; /* 4k x 2k Spec P156 */
if (VideoCode == 0) { /* For non-4kx2k mode setting */
hdev->HWOp.SetPacket(HDMI_PACKET_VEND, NULL, VEN_HB);
return;
}
if (VideoCode == HDMI_4k2k_30)
VEN_DB[4] = 0x1;
else if (VideoCode == HDMI_4k2k_25)
VEN_DB[4] = 0x2;
else if (VideoCode == HDMI_4k2k_24)
VEN_DB[4] = 0x3;
else if (VideoCode == HDMI_4k2k_smpte_24)
VEN_DB[4] = 0x4;
else
;
hdev->HWOp.SetPacket(HDMI_PACKET_VEND, VEN_DB, VEN_HB);
}
int hdmi_set_3d(struct hdmitx_dev *hdev, int type, unsigned int param)
{
int i;
unsigned char VEN_DB[6];
unsigned char VEN_HB[3];
VEN_HB[0] = 0x81;
VEN_HB[1] = 0x01;
VEN_HB[2] = 0x6;
if (type == T3D_DISABLE)
hdev->HWOp.SetPacket(HDMI_PACKET_VEND, NULL, VEN_HB);
else {
for (i = 0; i < 0x6; i++)
VEN_DB[i] = 0;
VEN_DB[0] = 0x03;
VEN_DB[1] = 0x0c;
VEN_DB[2] = 0x00;
VEN_DB[3] = 0x40;
VEN_DB[4] = type<<4;
VEN_DB[5] = param<<4;
hdev->HWOp.SetPacket(HDMI_PACKET_VEND, VEN_DB, VEN_HB);
}
return 0;
}
/* Set Source Product Descriptor InfoFrame
*/
static void hdmitx_set_spd_info(struct hdmitx_dev *hdev)
{
unsigned char SPD_DB[25] = {0x00};
unsigned char SPD_HB[3] = {0x83, 0x1, 0x19};
unsigned int len = 0;
struct vendor_info_data *vend_data;
if (hdev->config_data.vend_data)
vend_data = hdev->config_data.vend_data;
else {
hdmi_print(INF, SYS "packet: can\'t get vendor data\n");
return;
}
if (vend_data->vendor_name) {
len = strlen(vend_data->vendor_name);
strncpy(&SPD_DB[0], vend_data->vendor_name,
(len > 8) ? 8 : len);
}
if (vend_data->product_desc) {
len = strlen(vend_data->product_desc);
strncpy(&SPD_DB[8], vend_data->product_desc,
(len > 16) ? 16 : len);
}
SPD_DB[24] = 0x1;
hdev->HWOp.SetPacket(HDMI_SOURCE_DESCRIPTION, SPD_DB, SPD_HB);
}

2
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/Makefile Normal file
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obj-y += hdmi_tx_hw.o reg_ops.o sec_ops.o enc_cfg_hw.o hdmi_tx_ddc.o hdcpVerify.o
obj-y += hw_gxbb.o hw_gxtvbb.o hw_gxl.o hw_clk.o

54
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/common.h Normal file
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/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/common.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __HDMITX_HW_COMMON_H__
#define __HDMITX_HW_COMMON_H__
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_ddc.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_common.h>
#include "mach_reg.h"
#include "hdmi_tx_reg.h"
/*
* HDMITX HPD HW related operations
*/
enum hpd_op {
HPD_INIT_DISABLE_PULLUP,
HPD_INIT_SET_FILTER,
HPD_IS_HPD_MUXED,
HPD_MUX_HPD,
HPD_UNMUX_HPD,
HPD_READ_HPD_GPIO,
};
int hdmitx_hpd_hw_op_gxbb(enum hpd_op cmd);
int read_hpd_gpio_gxbb(void);
int hdmitx_ddc_hw_op_gxbb(enum ddc_op cmd);
int hdmitx_hpd_hw_op_gxtvbb(enum hpd_op cmd);
int read_hpd_gpio_gxtvbb(void);
int hdmitx_ddc_hw_op_gxtvbb(enum ddc_op cmd);
int hdmitx_hpd_hw_op_gxl(enum hpd_op cmd);
int read_hpd_gpio_gxl(void);
int hdmitx_ddc_hw_op_gxl(enum ddc_op cmd);
void set_gxl_hpll_clk_out(unsigned int frac_rate, unsigned int clk);
void set_hpll_sspll_gxl(enum hdmi_vic vic);
void set_hpll_od1_gxl(unsigned int div);
void set_hpll_od2_gxl(unsigned int div);
void set_hpll_od3_gxl(unsigned int div);
#endif

1013
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c Normal file
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45
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdcp.h Normal file
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/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdcp.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef HDCP_H_
#define HDCP_H_
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
enum hdcp_status_t {
HDCP_IDLE = 0,
HDCP_KSV_LIST_READY,
HDCP_ERR_KSV_LIST_NOT_VALID,
HDCP_KSV_LIST_ERR_DEPTH_EXCEEDED,
HDCP_KSV_LIST_ERR_MEM_ACCESS,
HDCP_ENGAGED,
HDCP_FAILED
};
/* HDCP Interrupt bit fields */
#define INT_KSV_ACCESS (0)
#define INT_KSV_SHA1 (1)
#define INT_HDCP_FAIL (6)
#define INT_HDCP_ENGAGED (7)
#endif /* HDCP_H_ */

600
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdcpVerify.c Normal file
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/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdcpVerify.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include "hdcpVerify.h"
#define SIZE (160/8)
#define KSIZE (1024/8)
void sha_Reset(struct sha_t *sha)
{
size_t i = 0;
sha->mIndex = 0;
sha->mComputed = FALSE;
sha->mCorrupted = FALSE;
for (i = 0; i < sizeof(sha->mLength); i++)
sha->mLength[i] = 0;
sha->mDigest[0] = 0x67452301;
sha->mDigest[1] = 0xEFCDAB89;
sha->mDigest[2] = 0x98BADCFE;
sha->mDigest[3] = 0x10325476;
sha->mDigest[4] = 0xC3D2E1F0;
}
int sha_Result(struct sha_t *sha)
{
if (sha->mCorrupted == TRUE)
return FALSE;
if (sha->mComputed == FALSE) {
sha_PadMessage(sha);
sha->mComputed = TRUE;
}
return TRUE;
}
void sha_Input(struct sha_t *sha, const uint8_t *data, size_t size)
{
int i = 0;
unsigned int j = 0;
int rc = TRUE;
if (data == 0 || size == 0) {
pr_info("invalid input data");
return;
}
if (sha->mComputed == TRUE || sha->mCorrupted == TRUE) {
sha->mCorrupted = TRUE;
return;
}
while (size-- && sha->mCorrupted == FALSE) {
sha->mBlock[sha->mIndex++] = *data;
for (i = 0; i < 8; i++) {
rc = TRUE;
for (j = 0; j < sizeof(sha->mLength); j++) {
sha->mLength[j]++;
if (sha->mLength[j] != 0) {
rc = FALSE;
break;
}
}
sha->mCorrupted = (sha->mCorrupted == TRUE ||
rc == TRUE) ? TRUE : FALSE;
}
/* if corrupted then message is too long */
if (sha->mIndex == 64)
sha_ProcessBlock(sha);
data++;
}
}
void sha_ProcessBlock(struct sha_t *sha)
{
#define shaCircularShift(bits, word) \
((((word) << (bits)) & 0xFFFFFFFF) | ((word) >> (32-(bits))))
const unsigned int K[] = {
/* constants defined in SHA-1 */
0x5A827999, 0x6ED9EBA1, 0x8F1BBCDC, 0xCA62C1D6 };
unsigned int W[80]; /* word sequence */
unsigned int A, B, C, D, E; /* word buffers */
unsigned int temp = 0;
int t = 0;
/* Initialize the first 16 words in the array W */
for (t = 0; t < 80; t++) {
if (t < 16) {
W[t] = ((unsigned int) sha->mBlock[t * 4 + 0]) << 24;
W[t] |= ((unsigned int) sha->mBlock[t * 4 + 1]) << 16;
W[t] |= ((unsigned int) sha->mBlock[t * 4 + 2]) << 8;
W[t] |= ((unsigned int) sha->mBlock[t * 4 + 3]) << 0;
} else
W[t] = shaCircularShift(1,
W[t-3] ^ W[t-8] ^ W[t-14] ^ W[t-16]);
}
A = sha->mDigest[0];
B = sha->mDigest[1];
C = sha->mDigest[2];
D = sha->mDigest[3];
E = sha->mDigest[4];
for (t = 0; t < 80; t++) {
temp = shaCircularShift(5, A);
if (t < 20)
temp += ((B & C) | ((~B) & D)) + E + W[t] + K[0];
else if (t < 40)
temp += (B ^ C ^ D) + E + W[t] + K[1];
else if (t < 60)
temp += ((B & C) | (B & D) | (C & D)) + E + W[t] + K[2];
else
temp += (B ^ C ^ D) + E + W[t] + K[3];
E = D;
D = C;
C = shaCircularShift(30, B);
B = A;
A = (temp & 0xFFFFFFFF);
}
sha->mDigest[0] = (sha->mDigest[0] + A) & 0xFFFFFFFF;
sha->mDigest[1] = (sha->mDigest[1] + B) & 0xFFFFFFFF;
sha->mDigest[2] = (sha->mDigest[2] + C) & 0xFFFFFFFF;
sha->mDigest[3] = (sha->mDigest[3] + D) & 0xFFFFFFFF;
sha->mDigest[4] = (sha->mDigest[4] + E) & 0xFFFFFFFF;
sha->mIndex = 0;
}
void sha_PadMessage(struct sha_t *sha)
{
/*
* Check to see if the current message block is too small to hold
* the initial padding bits and length. If so, we will pad the
* block, process it, and then continue padding into a second
* block.
*/
if (sha->mIndex > 55) {
sha->mBlock[sha->mIndex++] = 0x80;
while (sha->mIndex < 64)
sha->mBlock[sha->mIndex++] = 0;
sha_ProcessBlock(sha);
while (sha->mIndex < 56)
sha->mBlock[sha->mIndex++] = 0;
} else {
sha->mBlock[sha->mIndex++] = 0x80;
while (sha->mIndex < 56)
sha->mBlock[sha->mIndex++] = 0;
}
/* Store the message length as the last 8 octets */
sha->mBlock[56] = sha->mLength[7];
sha->mBlock[57] = sha->mLength[6];
sha->mBlock[58] = sha->mLength[5];
sha->mBlock[59] = sha->mLength[4];
sha->mBlock[60] = sha->mLength[3];
sha->mBlock[61] = sha->mLength[2];
sha->mBlock[62] = sha->mLength[1];
sha->mBlock[63] = sha->mLength[0];
sha_ProcessBlock(sha);
}
int hdcpVerify_DSA(const uint8_t *M, size_t n, const uint8_t *r,
const uint8_t *s)
{
int i = 0;
struct sha_t sha;
static const uint8_t q[] = {
0xE7, 0x08, 0xC7, 0xF9, 0x4D, 0x3F, 0xEF, 0x97,
0xE2, 0x14, 0x6D, 0xCD, 0x6A, 0xB5, 0x6D, 0x5E,
0xCE, 0xF2, 0x8A, 0xEE };
static const uint8_t p[] = {
0x27, 0x75, 0x28, 0xF3, 0x2B, 0x80, 0x59, 0x8C,
0x11, 0xC2, 0xED, 0x46, 0x1C, 0x95, 0x39, 0x2A,
0x54, 0x19, 0x89, 0x96, 0xFD, 0x49, 0x8A, 0x02,
0x3B, 0x73, 0x75, 0x32, 0x14, 0x9C, 0x7B, 0x5C,
0x49, 0x20, 0x98, 0xB9, 0x07, 0x32, 0x3F, 0xA7,
0x30, 0x15, 0x72, 0xB3, 0x09, 0x55, 0x71, 0x10,
0x3A, 0x4C, 0x97, 0xD1, 0xBC, 0xA0, 0x04, 0xF4,
0x35, 0xCF, 0x47, 0x54, 0x0E, 0xA7, 0x2B, 0xE5,
0x83, 0xB9, 0xC6, 0xD4, 0x47, 0xC7, 0x44, 0xB8,
0x67, 0x76, 0x7C, 0xAE, 0x0C, 0xDC, 0x34, 0x4F,
0x4B, 0x9E, 0x96, 0x1D, 0x82, 0x84, 0xD2, 0xA0,
0xDC, 0xE0, 0x00, 0xF5, 0x64, 0xA1, 0x7F, 0x8E,
0xFF, 0x58, 0x70, 0x6A, 0xC3, 0x4F, 0xA2, 0xA1,
0xB8, 0xC7, 0x52, 0x5A, 0x35, 0x5B, 0x39, 0x17,
0x6B, 0x78, 0x43, 0x93, 0xF7, 0x75, 0x8D, 0x01,
0xB7, 0x61, 0x17, 0xFD, 0xB2, 0xF5, 0xC3, 0xD3 };
static const uint8_t g[] = {
0xD9, 0x0B, 0xBA, 0xC2, 0x42, 0x24, 0x46, 0x69,
0x5B, 0x40, 0x67, 0x2F, 0x5B, 0x18, 0x3F, 0xB9,
0xE8, 0x6F, 0x21, 0x29, 0xAC, 0x7D, 0xFA, 0x51,
0xC2, 0x9D, 0x4A, 0xAB, 0x8A, 0x9B, 0x8E, 0xC9,
0x42, 0x42, 0xA5, 0x1D, 0xB2, 0x69, 0xAB, 0xC8,
0xE3, 0xA5, 0xC8, 0x81, 0xBE, 0xB6, 0xA0, 0xB1,
0x7F, 0xBA, 0x21, 0x2C, 0x64, 0x35, 0xC8, 0xF7,
0x5F, 0x58, 0x78, 0xF7, 0x45, 0x29, 0xDD, 0x92,
0x9E, 0x79, 0x3D, 0xA0, 0x0C, 0xCD, 0x29, 0x0E,
0xA9, 0xE1, 0x37, 0xEB, 0xBF, 0xC6, 0xED, 0x8E,
0xA8, 0xFF, 0x3E, 0xA8, 0x7D, 0x97, 0x62, 0x51,
0xD2, 0xA9, 0xEC, 0xBD, 0x4A, 0xB1, 0x5D, 0x8F,
0x11, 0x86, 0x27, 0xCD, 0x66, 0xD7, 0x56, 0x5D,
0x31, 0xD7, 0xBE, 0xA9, 0xAC, 0xDE, 0xAF, 0x02,
0xB5, 0x1A, 0xDE, 0x45, 0x24, 0x3E, 0xE4, 0x1A,
0x13, 0x52, 0x4D, 0x6A, 0x1B, 0x5D, 0xF8, 0x92 };
static const uint8_t y[] = {
0x99, 0x37, 0xE5, 0x36, 0xFA, 0xF7, 0xA9, 0x62,
0x83, 0xFB, 0xB3, 0xE9, 0xF7, 0x9D, 0x8F, 0xD8,
0xCB, 0x62, 0xF6, 0x66, 0x8D, 0xDC, 0xC8, 0x95,
0x10, 0x24, 0x6C, 0x88, 0xBD, 0xFF, 0xB7, 0x7B,
0xE2, 0x06, 0x52, 0xFD, 0xF7, 0x5F, 0x43, 0x62,
0xE6, 0x53, 0x65, 0xB1, 0x38, 0x90, 0x25, 0x87,
0x8D, 0xA4, 0x9E, 0xFE, 0x56, 0x08, 0xA7, 0xA2,
0x0D, 0x4E, 0xD8, 0x43, 0x3C, 0x97, 0xBA, 0x27,
0x6C, 0x56, 0xC4, 0x17, 0xA4, 0xB2, 0x5C, 0x8D,
0xDB, 0x04, 0x17, 0x03, 0x4F, 0xE1, 0x22, 0xDB,
0x74, 0x18, 0x54, 0x1B, 0xDE, 0x04, 0x68, 0xE1,
0xBD, 0x0B, 0x4F, 0x65, 0x48, 0x0E, 0x95, 0x56,
0x8D, 0xA7, 0x5B, 0xF1, 0x55, 0x47, 0x65, 0xE7,
0xA8, 0x54, 0x17, 0x8A, 0x65, 0x76, 0x0D, 0x4F,
0x0D, 0xFF, 0xAC, 0xA3, 0xE0, 0xFB, 0x80, 0x3A,
0x86, 0xB0, 0xA0, 0x6B, 0x52, 0x00, 0x06, 0xC7 };
uint8_t w[SIZE];
uint8_t z[SIZE];
uint8_t u1[SIZE];
uint8_t u2[SIZE];
uint8_t gu1[KSIZE];
uint8_t yu2[KSIZE];
uint8_t pro[KSIZE];
uint8_t v[SIZE];
/* adapt to the expected format by arithmetic functions */
uint8_t r1[SIZE];
uint8_t s1[SIZE];
sha_Reset(&sha);
hdcpVerify_ArrayCPY(r1, r, sizeof(r1));
hdcpVerify_ArrayCPY(s1, s, sizeof(s1));
hdcpVerify_ArraySWP(r1, sizeof(r1));
hdcpVerify_ArraySWP(s1, sizeof(s1));
hdcpVerify_ComputeINV(w, s1, q, sizeof(w));
sha_Input(&sha, M, n);
if (sha_Result(&sha) == TRUE) {
for (i = 0; i < 5; i++) {
z[i * 4 + 0] = sha.mDigest[i] >> 24;
z[i * 4 + 1] = sha.mDigest[i] >> 16;
z[i * 4 + 2] = sha.mDigest[i] >> 8;
z[i * 4 + 3] = sha.mDigest[i] >> 0;
}
hdcpVerify_ArraySWP(z, sizeof(z));
} else {
pr_info("cannot digest message");
return FALSE;
}
if (hdcpVerify_ComputeMUL(u1, z, w, q, sizeof(u1)) == FALSE)
return FALSE;
if (hdcpVerify_ComputeMUL(u2, r1, w, q, sizeof(u2)) == FALSE)
return FALSE;
if (hdcpVerify_ComputeEXP(gu1, g, u1, p, sizeof(gu1), sizeof(u1))
== FALSE)
return FALSE;
if (hdcpVerify_ComputeEXP(yu2, y, u2, p, sizeof(yu2), sizeof(u2))
== FALSE)
return FALSE;
if (hdcpVerify_ComputeMUL(pro, gu1, yu2, p, sizeof(pro)) == FALSE)
return FALSE;
if (hdcpVerify_ComputeMOD(v, pro, q, sizeof(v)) == FALSE)
return FALSE;
return hdcpVerify_ArrayCMP(v, r1, sizeof(v)) == 0;
}
int hdcpVerify_ArrayADD(uint8_t *r, const uint8_t *a, const uint8_t *b,
size_t n)
{
uint8_t c = 0;
size_t i = 0;
for (i = 0; i < n; i++) {
u16 s = a[i] + b[i] + c;
c = (uint8_t) (s >> 8);
r[i] = (uint8_t) s;
}
return c;
}
int hdcpVerify_ArrayCMP(const uint8_t *a, const uint8_t *b, size_t n)
{
int i = 0;
for (i = n; i > 0; i--) {
if (a[i - 1] > b[i - 1])
return 1;
else if (a[i - 1] < b[i - 1])
return -1;
}
return 0;
}
void hdcpVerify_ArrayCPY(uint8_t *dst, const uint8_t *src, size_t n)
{
size_t i = 0;
for (i = 0; i < n; i++)
dst[i] = src[i];
}
int hdcpVerify_ArrayDIV(uint8_t *r, const uint8_t *D, const uint8_t *d,
size_t n)
{
int i = 0;
if (r == D || r == d || (!hdcpVerify_ArrayTST(d, 0, n)) == TRUE) {
pr_info("invalid input data");
return FALSE;
}
hdcpVerify_ArraySET(&r[n], 0, n);
hdcpVerify_ArrayCPY(r, D, n);
for (i = n; i > 0; i--) {
r[i - 1 + n] = 0;
while (hdcpVerify_ArrayCMP(&r[i - 1], d, n) >= 0) {
hdcpVerify_ArraySUB(&r[i - 1], &r[i - 1], d, n);
r[i - 1 + n] += 1;
}
}
return TRUE;
}
int hdcpVerify_ArrayMAC(uint8_t *r, const uint8_t *M, const uint8_t m, size_t n)
{
u16 c = 0;
size_t i = 0;
for (i = 0; i < n; i++) {
u16 p = (M[i] * m) + c + r[i];
c = p >> 8;
r[i] = (uint8_t) p;
}
return (uint8_t) c;
}
int hdcpVerify_ArrayMUL(uint8_t *r, const uint8_t *M, const uint8_t *m,
size_t n)
{
size_t i = 0;
if (r == M || r == m) {
pr_info("invalid input data");
return FALSE;
}
hdcpVerify_ArraySET(r, 0, n);
for (i = 0; i < n; i++) {
if (m[i] == 0)
continue;
else if (m[i] == 1)
hdcpVerify_ArrayADD(&r[i], &r[i], M, n - i);
else
hdcpVerify_ArrayMAC(&r[i], M, m[i], n - i);
}
return TRUE;
}
void hdcpVerify_ArraySET(uint8_t *dst, const uint8_t src, size_t n)
{
size_t i = 0;
for (i = 0; i < n; i++)
dst[i] = src;
}
int hdcpVerify_ArraySUB(uint8_t *r, const uint8_t *a, const uint8_t *b,
size_t n)
{
uint8_t c = 1;
size_t i = 0;
for (i = 0; i < n; i++) {
u16 s = ((uint8_t) a[i] + (uint8_t) (~b[i])) + c;
c = (uint8_t) (s >> 8);
r[i] = (uint8_t) s;
}
return c;
}
void hdcpVerify_ArraySWP(uint8_t *r, size_t n)
{
size_t i = 0;
for (i = 0; i < (n / 2); i++) {
uint8_t tmp = r[i];
r[i] = r[n - 1 - i];
r[n - 1 - i] = tmp;
}
}
int hdcpVerify_ArrayTST(const uint8_t *a, const uint8_t b, size_t n)
{
size_t i = 0;
for (i = 0; i < n; i++) {
if (a[i] != b)
return FALSE;
}
return TRUE;
}
int hdcpVerify_ComputeEXP(uint8_t *c, const uint8_t *M, const uint8_t *e,
const uint8_t *p, size_t n, size_t nE)
{
int i = 8 * nE - 1;
int rc = TRUE;
/* LR Binary Method */
if ((e[i / 8] & (1 << (i % 8))) != 0)
hdcpVerify_ArrayCPY(c, M, n);
else {
hdcpVerify_ArraySET(c, 0, n);
c[0] = 1;
}
for (i -= 1; i >= 0; i--) {
rc |= hdcpVerify_ComputeMUL(c, c, c, p, n);
if ((e[i / 8] & (1 << (i % 8))) != 0)
rc &= hdcpVerify_ComputeMUL(c, c, M, p, n);
}
return rc;
}
int hdcpVerify_ComputeINV(uint8_t *out, const uint8_t *z, const uint8_t *a,
size_t n)
{
uint8_t w[2][SIZE];
uint8_t x[2][SIZE];
uint8_t y[2][SIZE];
uint8_t r[2*SIZE];
uint8_t *i, *j, *q, *t;
uint8_t *x1, *x2;
uint8_t *y1, *y2;
if ((n > SIZE) || (hdcpVerify_ArrayTST(z, 0, n) == TRUE)
|| (hdcpVerify_ArrayTST(a, 0, n) == TRUE)
|| (hdcpVerify_ArrayCMP(z, a, n) >= 0)) {
pr_info("invalid input data");
return FALSE;
}
hdcpVerify_ArrayCPY(w[0], a, n);
hdcpVerify_ArrayCPY(w[1], z, n);
i = w[0];
j = w[1];
hdcpVerify_ArraySET(x[1], 0, n);
x[1][0] = 1;
hdcpVerify_ArraySET(x[0], 0, n);
x2 = x[1];
x1 = x[0];
hdcpVerify_ArraySET(y[1], 0, n);
hdcpVerify_ArraySET(y[0], 0, n);
y[0][0] = 1;
y2 = y[1];
y1 = y[0];
do {
hdcpVerify_ArrayDIV(r, i, j, n);
hdcpVerify_ArrayCPY(i, r, n);
q = &r[n];
t = i; /* swap i <-> j */
i = j;
j = t;
hdcpVerify_ArrayMUL(r, x1, q, n);
hdcpVerify_ArraySUB(x2, x2, r, n);
t = x2; /* swap x1 <-> x2 */
x2 = x1;
x1 = t;
hdcpVerify_ArrayMUL(r, y1, q, n);
hdcpVerify_ArraySUB(y2, y2, r, n);
t = y2; /* swap y1 <-> y2 */
y2 = y1;
y1 = t;
} while (hdcpVerify_ArrayTST(j, 0, n) == FALSE);
j[0] = 1;
if (hdcpVerify_ArrayCMP(i, j, n) != 0) {
pr_info("i != 1");
return FALSE;
}
hdcpVerify_ArrayCPY(out, y2, n);
return TRUE;
}
int hdcpVerify_ComputeMOD(uint8_t *dst, const uint8_t *src, const uint8_t *p,
size_t n)
{
uint8_t aux[KSIZE];
uint8_t ext[SIZE + 1];
uint8_t tmp[2 * (KSIZE + 1)];
int i = 0;
if (n > SIZE) {
pr_info("invalid input data");
return FALSE;
}
hdcpVerify_ArrayCPY(aux, src, sizeof(aux));
/* TODO: remove extension */
hdcpVerify_ArrayCPY(ext, p, n);
ext[n] = 0;
for (i = sizeof(aux)-n-1; i >= 0; i--) {
hdcpVerify_ArrayDIV(tmp, &aux[i], ext, n+1);
hdcpVerify_ArrayCPY(&aux[i], tmp, n+1);
}
hdcpVerify_ArrayCPY(dst, aux, n);
return TRUE;
}
int hdcpVerify_ComputeMUL(uint8_t *p, const uint8_t *a, const uint8_t *b,
const uint8_t *m, size_t n)
{
uint8_t aux[2 * KSIZE + 1];
uint8_t ext[KSIZE + 1];
uint8_t tmp[2 * (KSIZE + 1)];
size_t i = 0;
int j = 0;
if (n > KSIZE) {
pr_info("invalid input data");
return FALSE;
}
hdcpVerify_ArraySET(aux, 0, sizeof(aux));
for (i = 0; i < n; i++) {
/* TODO: extension was faster */
aux[n+i] = hdcpVerify_ArrayMAC(&aux[i], a, b[i], n);
}
/* TODO: reuse ComputeMOD */
hdcpVerify_ArrayCPY(ext, m, n);
ext[n] = 0;
for (j = n; j >= 0; j--) {
hdcpVerify_ArrayDIV(tmp, &aux[j], ext, n+1);
hdcpVerify_ArrayCPY(&aux[j], tmp, n+1);
}
hdcpVerify_ArrayCPY(p, aux, n);
return TRUE;
}
int hdcpVerify_KSV(const uint8_t *data, size_t size)
{
size_t i = 0;
struct sha_t sha;
if (data == 0 || size < (HEADER + SHAMAX)) {
pr_info("invalid input data");
return FALSE;
}
sha_Reset(&sha);
sha_Input(&sha, data, size - SHAMAX);
if (sha_Result(&sha) == FALSE) {
pr_info("cannot process SHA digest");
return FALSE;
}
for (i = 0; i < SHAMAX; i++) {
if (data[size - SHAMAX + i] != (uint8_t) (sha.mDigest[i / 4]
>> ((i % 4) * 8))) {
pr_info("SHA digest does not match");
return FALSE;
}
}
return TRUE;
}
int hdcpVerify_SRM(const uint8_t *data, size_t size)
{
if (data == 0 || size < (VRL_HEADER + VRL_NUMBER + 2 * DSAMAX)) {
pr_info("invalid input data");
return FALSE;
}
/* M, n, r, s */
return hdcpVerify_DSA(data, size - 2 * DSAMAX, &data[size - 2 * DSAMAX],
&data[size - DSAMAX]);
}

97
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdcpVerify.h Normal file
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/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdcpVerify.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef HDCPVERIFY_H_
#define HDCPVERIFY_H_
#include <linux/types.h>
#include <linux/printk.h>
#include "hdcp.h"
struct sha_t {
uint8_t mLength[8];
uint8_t mBlock[64];
int mIndex;
int mComputed;
int mCorrupted;
unsigned int mDigest[5];
};
#define KSV_LEN 5
#define KSV_MSK 0x7F
#define VRL_LENGTH 0x05
#define VRL_HEADER 5
#define VRL_NUMBER 3
#define HEADER 10
#define SHAMAX 20
#define DSAMAX 20
void sha_Reset(struct sha_t *sha);
int sha_Result(struct sha_t *sha);
void sha_Input(struct sha_t *sha, const uint8_t *data, size_t size);
void sha_ProcessBlock(struct sha_t *sha);
void sha_PadMessage(struct sha_t *sha);
int hdcpVerify_DSA(const uint8_t *M, size_t n, const uint8_t *r,
const uint8_t *s);
int hdcpVerify_ArrayADD(uint8_t *r, const uint8_t *a, const uint8_t *b,
size_t n);
int hdcpVerify_ArrayCMP(const uint8_t *a, const uint8_t *b, size_t n);
void hdcpVerify_ArrayCPY(uint8_t *dst, const uint8_t *src, size_t n);
int hdcpVerify_ArrayDIV(uint8_t *r, const uint8_t *D, const uint8_t *d,
size_t n);
int hdcpVerify_ArrayMAC(uint8_t *r, const uint8_t *M, const uint8_t m,
size_t n);
int hdcpVerify_ArrayMUL(uint8_t *r, const uint8_t *M, const uint8_t *m,
size_t n);
void hdcpVerify_ArraySET(uint8_t *dst, const uint8_t src, size_t n);
int hdcpVerify_ArraySUB(uint8_t *r, const uint8_t *a, const uint8_t *b,
size_t n);
void hdcpVerify_ArraySWP(uint8_t *r, size_t n);
int hdcpVerify_ArrayTST(const uint8_t *a, const uint8_t b, size_t n);
int hdcpVerify_ComputeEXP(uint8_t *c, const uint8_t *M, const uint8_t *e,
const uint8_t *p, size_t n, size_t nE);
int hdcpVerify_ComputeINV(uint8_t *out, const uint8_t *z, const uint8_t *a,
size_t n);
int hdcpVerify_ComputeMOD(uint8_t *dst, const uint8_t *src, const uint8_t *p,
size_t n);
int hdcpVerify_ComputeMUL(uint8_t *p, const uint8_t *a, const uint8_t *b,
const uint8_t *m, size_t n);
int hdcpVerify_KSV(const uint8_t *data, size_t size);
int hdcpVerify_SRM(const uint8_t *data, size_t size);
#endif /* HDCPVERIFY_H_ */

205
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_ddc.c Normal file
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/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_ddc.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/version.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/mm.h>
#include <linux/major.h>
#include <linux/platform_device.h>
#include <linux/mutex.h>
#include <linux/cdev.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_ddc.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_info_global.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
#include "hdmi_tx_reg.h"
static uint32_t ddc_write_1byte(uint8_t slave, uint8_t offset_addr,
uint8_t data)
{
uint32_t st = 0;
hdmitx_wr_reg(HDMITX_DWC_I2CM_SLAVE, slave);
hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, offset_addr);
hdmitx_wr_reg(HDMITX_DWC_I2CM_DATAO, data);
hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 1 << 4);
mdelay(2);
if (hdmitx_rd_reg(HDMITX_DWC_IH_I2CM_STAT0) & (1 << 0)) {
st = 0;
pr_info("hdmitx: ddc w1b error 0x%02x 0x%02x 0x%02x\n",
slave, offset_addr, data);
} else
st = 1;
hdmitx_wr_reg(HDMITX_DWC_IH_I2CM_STAT0, 0x7);
return st;
}
static uint32_t ddc_readext_8byte(uint8_t slave, uint8_t offset_addr,
uint8_t *data)
{
uint32_t st = 0;
int32_t i;
hdmitx_wr_reg(HDMITX_DWC_I2CM_SLAVE, slave);
hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, offset_addr);
hdmitx_wr_reg(HDMITX_DWC_I2CM_SEGADDR, EDIDSEG_ADR);
hdmitx_wr_reg(HDMITX_DWC_I2CM_SEGPTR, 0x00);
hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 1 << 3);
mdelay(2);
if (hdmitx_rd_reg(HDMITX_DWC_IH_I2CM_STAT0) & (1 << 0)) {
st = 0;
pr_info("hdmitx: ddc rdext8b error 0x%02x 0x%02x\n",
slave, offset_addr);
} else
st = 1;
hdmitx_wr_reg(HDMITX_DWC_IH_I2CM_STAT0, 0x7);
for (i = 0; i < 8; i++)
data[i] = hdmitx_rd_reg(HDMITX_DWC_I2CM_READ_BUFF0 + i);
return st;
}
static uint32_t ddc_read_8byte(uint8_t slave, uint8_t offset_addr,
uint8_t *data)
{
uint32_t st = 0;
int32_t i;
hdmitx_wr_reg(HDMITX_DWC_I2CM_SLAVE, slave);
hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, offset_addr);
hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 1 << 2);
mdelay(2);
if (hdmitx_rd_reg(HDMITX_DWC_IH_I2CM_STAT0) & (1 << 0)) {
st = 0;
pr_info("hdmitx: ddc rd8b error 0x%02x 0x%02x 0x%02x\n",
slave, offset_addr, *data);
} else
st = 1;
hdmitx_wr_reg(HDMITX_DWC_IH_I2CM_STAT0, 0x7);
for (i = 0; i < 8; i++)
data[i] = hdmitx_rd_reg(HDMITX_DWC_I2CM_READ_BUFF0 + i);
return st;
}
static uint32_t ddc_readext_1byte(uint8_t slave, uint8_t address, uint8_t *data)
{
uint32_t st = 0;
hdmitx_wr_reg(HDMITX_DWC_I2CM_SLAVE, slave);
hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, address);
hdmitx_wr_reg(HDMITX_DWC_I2CM_SEGADDR, EDIDSEG_ADR);
hdmitx_wr_reg(HDMITX_DWC_I2CM_SEGPTR, 0x00);
hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 1 << 1);
mdelay(2);
if (hdmitx_rd_reg(HDMITX_DWC_IH_I2CM_STAT0) & (1 << 0)) {
st = 0;
pr_info("hdmitx: ddc rd8b error 0x%02x 0x%02x\n",
slave, address);
} else
st = 1;
hdmitx_wr_reg(HDMITX_DWC_IH_I2CM_STAT0, 0x7);
*data = hdmitx_rd_reg(HDMITX_DWC_I2CM_DATAI);
return st;
}
static uint32_t ddc_read_1byte(uint8_t slave, uint8_t offset_addr,
uint8_t *data)
{
uint32_t st = 0;
hdmitx_wr_reg(HDMITX_DWC_I2CM_SLAVE, slave);
hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, offset_addr);
hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 1 << 0);
mdelay(2);
if (hdmitx_rd_reg(HDMITX_DWC_IH_I2CM_STAT0) & (1 << 0)) {
st = 0;
pr_info("hdmitx: ddc rd8b error 0x%02x 0x%02x\n",
slave, offset_addr);
} else
st = 1;
hdmitx_wr_reg(HDMITX_DWC_IH_I2CM_STAT0, 0x7);
*data = hdmitx_rd_reg(HDMITX_DWC_I2CM_DATAI);
return st;
}
static uint32_t hdcp_rd_bksv(uint8_t *data)
{
if (0)
ddc_readext_8byte(HDCP_SLAVE, HDCP14_BKSV, data);
return ddc_read_8byte(HDCP_SLAVE, HDCP14_BKSV, data);
}
void scdc_rd_sink(uint8_t adr, uint8_t *val)
{
hdmitx_ddc_hw_op(DDC_MUX_DDC);
if (0)
ddc_readext_1byte(SCDC_SLAVE, adr, val);
ddc_read_1byte(SCDC_SLAVE, adr, val);
}
void scdc_wr_sink(uint8_t adr, uint8_t val)
{
hdmitx_ddc_hw_op(DDC_MUX_DDC);
ddc_write_1byte(SCDC_SLAVE, adr, val);
}
uint32_t hdcp_rd_hdcp14_ver(void)
{
int ret = 0;
uint8_t bksv[8] = {0};
hdmitx_ddc_hw_op(DDC_MUX_DDC);
ret = hdcp_rd_bksv(&bksv[0]);
if (ret)
return 1;
ret = hdcp_rd_bksv(&bksv[0]);
if (ret)
return 1;
return 0;
}
uint32_t hdcp_rd_hdcp22_ver(void)
{
uint32_t ret;
uint8_t ver;
hdmitx_ddc_hw_op(DDC_MUX_DDC);
ret = ddc_read_1byte(HDCP_SLAVE, HDCP2_VERSION, &ver);
if (ret)
return ver == 0x04;
ret = ddc_read_1byte(HDCP_SLAVE, HDCP2_VERSION, &ver);
if (ret)
return ver == 0x04;
return 0;
}

4628
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c Normal file
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File diff suppressed because it is too large Load Diff

1059
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_reg.h Normal file
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File diff suppressed because it is too large Load Diff

879
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c Normal file
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@@ -0,0 +1,879 @@
/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/module.h>
#include <linux/printk.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/amlogic/cpu_version.h>
#include "common.h"
#include "mach_reg.h"
#include "hw_clk.h"
static uint32_t frac_rate;
static int sspll_en = 1;
/*
* HDMITX Clock configuration
*/
static inline int check_div(unsigned int div)
{
if (div == -1)
return -1;
switch (div) {
case 1:
div = 0;
break;
case 2:
div = 1;
break;
case 4:
div = 2;
break;
case 6:
div = 3;
break;
case 12:
div = 4;
break;
default:
break;
}
return div;
}
static void set_hdmitx_sys_clk(void)
{
hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 9, 3);
hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 0, 7);
hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 1, 8, 1);
}
static void set_gxb_hpll_clk_out(unsigned int clk)
{
switch (clk) {
case 5940000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x5800027b);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x0, 0, 16);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x135c5091);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x00000e55);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
if (frac_rate)
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4a05, 0, 16);
else
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4c00, 0, 16);
break;
case 5405400:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x58000270);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x0, 0, 16);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x135c5091);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x00000e55);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
if (frac_rate)
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4800, 0, 16);
else
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x49cd, 0, 16);
break;
case 4455000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x5800025c);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x0, 0, 16);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x135c5091);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x00000e55);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
if (frac_rate)
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4b84, 0, 16);
else
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4d00, 0, 16);
break;
case 3712500:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x5800024d);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x0, 0, 16);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x00000e55);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x4, 28, 3);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
if (frac_rate)
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4443, 0, 16);
else
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4580, 0, 16);
break;
case 3450000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x58000247);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x0, 0, 16);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x00000e55);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x4, 28, 3);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4300, 0, 16);
break;
case 3243240:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x58000243);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x0, 0, 16);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x00000e55);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x4, 28, 3);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4300, 0, 16);
if (frac_rate)
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4800, 0, 16);
else
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4914, 0, 16);
break;
case 2970000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x5800023d);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x0, 0, 16);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x00000e55);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x4, 28, 3);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
if (frac_rate)
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4d03, 0, 16);
else
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4e00, 0, 16);
break;
case 4324320:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x5800025a);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x00000e55);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
if (frac_rate)
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x0, 0, 16);
else
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4171, 0, 16);
break;
default:
pr_info("error hpll clk: %d\n", clk);
break;
}
}
static void set_gxtvbb_hpll_clk_out(unsigned int clk)
{
switch (clk) {
case 5940000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x5800027b);
if (frac_rate)
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4281, 0, 16);
else
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4300, 0, 16);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x12dc5081);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x00002e55);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 5405400:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x58000270);
if (frac_rate)
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4200, 0, 16);
else
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4273, 0, 16);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x12dc5081);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x00002e55);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 4455000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x5800025c);
if (frac_rate)
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x42e1, 0, 16);
else
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4340, 0, 16);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x12dc5081);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x00002e55);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 3712500:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x5800024d);
if (frac_rate)
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4111, 0, 16);
else
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4160, 0, 16);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x00002e55);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x4, 28, 3);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 3450000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x58000247);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4300, 0, 16);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x00002e55);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x4, 28, 3);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 3243240:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x58000243);
if (frac_rate)
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4200, 0, 16);
else
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4245, 0, 16);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x00002e55);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x4, 28, 3);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 2970000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x5800023d);
if (frac_rate)
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4341, 0, 16);
else
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4380, 0, 16);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x00002e55);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x4, 28, 3);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4e00, 0, 16);
break;
case 4324320:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x5800025a);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
if (frac_rate)
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x0, 0, 16);
else
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x405c, 0, 16);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x801da72c);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x71486980);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x00002e55);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
default:
pr_info("error hpll clk: %d\n", clk);
break;
}
}
static void set_hpll_clk_out(unsigned int clk)
{
pr_info("config HPLL = %d\n", clk);
switch (get_cpu_type()) {
case MESON_CPU_MAJOR_ID_GXBB:
set_gxb_hpll_clk_out(clk);
break;
case MESON_CPU_MAJOR_ID_GXTVBB:
set_gxtvbb_hpll_clk_out(clk);
break;
case MESON_CPU_MAJOR_ID_GXL:
case MESON_CPU_MAJOR_ID_GXM:
default:
set_gxl_hpll_clk_out(frac_rate, clk);
break;
}
pr_info("config HPLL done\n");
}
static void set_hpll_sspll(enum hdmi_vic vic)
{
switch (get_cpu_type()) {
case MESON_CPU_MAJOR_ID_GXBB:
break;
case MESON_CPU_MAJOR_ID_GXTVBB:
break;
case MESON_CPU_MAJOR_ID_GXL:
case MESON_CPU_MAJOR_ID_GXM:
set_hpll_sspll_gxl(vic);
break;
default:
break;
}
}
static void set_hpll_od1(unsigned int div)
{
switch (get_cpu_type()) {
case MESON_CPU_MAJOR_ID_GXBB:
case MESON_CPU_MAJOR_ID_GXTVBB:
switch (div) {
case 1:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0, 16, 2);
break;
case 2:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 1, 16, 2);
break;
case 4:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 2, 16, 2);
break;
case 8:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 3, 16, 2);
break;
default:
break;
}
break;
case MESON_CPU_MAJOR_ID_GXL:
case MESON_CPU_MAJOR_ID_GXM:
default:
set_hpll_od1_gxl(div);
break;
}
}
static void set_hpll_od2(unsigned int div)
{
switch (get_cpu_type()) {
case MESON_CPU_MAJOR_ID_GXBB:
case MESON_CPU_MAJOR_ID_GXTVBB:
switch (div) {
case 1:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0, 22, 2);
break;
case 2:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 1, 22, 2);
break;
case 4:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 2, 22, 2);
break;
case 8:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 3, 22, 2);
break;
default:
break;
}
break;
case MESON_CPU_MAJOR_ID_GXL:
case MESON_CPU_MAJOR_ID_GXM:
default:
set_hpll_od2_gxl(div);
break;
}
}
static void set_hpll_od3(unsigned int div)
{
switch (get_cpu_type()) {
case MESON_CPU_MAJOR_ID_GXBB:
case MESON_CPU_MAJOR_ID_GXTVBB:
switch (div) {
case 1:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0, 18, 2);
break;
case 2:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 1, 18, 2);
break;
case 4:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 2, 18, 2);
break;
case 8:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 3, 18, 2);
break;
default:
break;
}
break;
case MESON_CPU_MAJOR_ID_GXL:
case MESON_CPU_MAJOR_ID_GXM:
default:
set_hpll_od3_gxl(div);
break;
}
}
/* --------------------------------------------------
* clocks_set_vid_clk_div
* --------------------------------------------------
* wire clk_final_en = control[19];
* wire clk_div1 = control[18];
* wire [1:0] clk_sel = control[17:16];
* wire set_preset = control[15];
* wire [14:0] shift_preset = control[14:0];
*/
static void set_hpll_od3_clk_div(int div_sel)
{
int shift_val = 0;
int shift_sel = 0;
pr_info("%s[%d] div = %d\n", __func__, __LINE__, div_sel);
/* Disable the output clock */
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 18, 2);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
switch (div_sel) {
case VID_PLL_DIV_1:
shift_val = 0xFFFF;
shift_sel = 0;
break;
case VID_PLL_DIV_2:
shift_val = 0x0aaa;
shift_sel = 0;
break;
case VID_PLL_DIV_3:
shift_val = 0x0db6;
shift_sel = 0;
break;
case VID_PLL_DIV_3p5:
shift_val = 0x36cc;
shift_sel = 1;
break;
case VID_PLL_DIV_3p75:
shift_val = 0x6666;
shift_sel = 2;
break;
case VID_PLL_DIV_4:
shift_val = 0x0ccc;
shift_sel = 0;
break;
case VID_PLL_DIV_5:
shift_val = 0x739c;
shift_sel = 2;
break;
case VID_PLL_DIV_6:
shift_val = 0x0e38;
shift_sel = 0;
break;
case VID_PLL_DIV_6p25:
shift_val = 0x0000;
shift_sel = 3;
break;
case VID_PLL_DIV_7:
shift_val = 0x3c78;
shift_sel = 1;
break;
case VID_PLL_DIV_7p5:
shift_val = 0x78f0;
shift_sel = 2;
break;
case VID_PLL_DIV_12:
shift_val = 0x0fc0;
shift_sel = 0;
break;
case VID_PLL_DIV_14:
shift_val = 0x3f80;
shift_sel = 1;
break;
case VID_PLL_DIV_15:
shift_val = 0x7f80;
shift_sel = 2;
break;
case VID_PLL_DIV_2p5:
shift_val = 0x5294;
shift_sel = 2;
break;
default:
pr_info("Error: clocks_set_vid_clk_div: Invalid parameter\n");
break;
}
if (shift_val == 0xffff) /* if divide by 1 */
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 1, 18, 1);
else {
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 18, 1);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 16, 2);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 0, 14);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_sel, 16, 2);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 1, 15, 1);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_val, 0, 14);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
}
/* Enable the final output clock */
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 1, 19, 1);
}
static void set_vid_clk_div(unsigned int div)
{
hd_set_reg_bits(P_HHI_VID_CLK_CNTL, 0, 16, 3);
hd_set_reg_bits(P_HHI_VID_CLK_DIV, div-1, 0, 8);
hd_set_reg_bits(P_HHI_VID_CLK_CNTL, 7, 0, 3);
}
static void set_hdmi_tx_pixel_div(unsigned int div)
{
div = check_div(div);
if (div == -1)
return;
hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, div, 16, 4);
hd_set_reg_bits(P_HHI_VID_CLK_CNTL2, 1, 5, 1);
}
static void set_encp_div(unsigned int div)
{
div = check_div(div);
if (div == -1)
return;
hd_set_reg_bits(P_HHI_VID_CLK_DIV, div, 24, 4);
hd_set_reg_bits(P_HHI_VID_CLK_CNTL2, 1, 2, 1);
hd_set_reg_bits(P_HHI_VID_CLK_CNTL, 1, 19, 1);
}
static void set_enci_div(unsigned int div)
{
div = check_div(div);
if (div == -1)
return;
hd_set_reg_bits(P_HHI_VID_CLK_DIV, div, 28, 4);
hd_set_reg_bits(P_HHI_VID_CLK_CNTL2, 1, 0, 1);
hd_set_reg_bits(P_HHI_VID_CLK_CNTL, 1, 19, 1);
}
/* mode hpll_clk_out od1 od2(PHY) od3
* vid_pll_div vid_clk_div hdmi_tx_pixel_div encp_div enci_div
*/
static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
{{HDMI_720x480i60_16x9,
HDMI_720x576i50_16x9,
HDMI_VIC_END},
4324320, 4, 4, 1, VID_PLL_DIV_5, 1, 2, -1, 2},
{{HDMI_720x576p50_16x9,
HDMI_720x480p60_16x9,
HDMI_VIC_END},
4324320, 4, 4, 1, VID_PLL_DIV_5, 1, 2, 1, -1},
{{HDMI_1280x720p50_16x9,
HDMI_1280x720p60_16x9,
HDMI_VIC_END},
2970000, 4, 1, 1, VID_PLL_DIV_5, 1, 2, 1, -1},
{{HDMI_1920x1080i60_16x9,
HDMI_1920x1080i50_16x9,
HDMI_VIC_END},
2970000, 4, 1, 1, VID_PLL_DIV_5, 1, 2, 1, -1},
{{HDMI_1920x1080p60_16x9,
HDMI_1920x1080p50_16x9,
HDMI_VIC_END},
2970000, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
{{HDMI_1920x1080p30_16x9,
HDMI_1920x1080p24_16x9,
HDMI_1920x1080p25_16x9,
HDMI_VIC_END},
2970000, 2, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
{{HDMI_3840x2160p30_16x9,
HDMI_3840x2160p25_16x9,
HDMI_3840x2160p24_16x9,
HDMI_4096x2160p24_256x135,
HDMI_4096x2160p25_256x135,
HDMI_4096x2160p30_256x135,
HDMI_VIC_END},
5940000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMI_3840x2160p60_16x9,
HDMI_3840x2160p50_16x9,
HDMI_4096x2160p60_256x135,
HDMI_4096x2160p50_256x135,
HDMI_VIC_END},
5940000, 1, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
{{HDMI_4096x2160p60_256x135_Y420,
HDMI_4096x2160p50_256x135_Y420,
HDMI_3840x2160p60_16x9_Y420,
HDMI_3840x2160p50_16x9_Y420,
HDMI_VIC_END},
5940000, 2, 1, 1, VID_PLL_DIV_5, 1, 2, 1, -1},
{{HDMI_VIC_FAKE,
HDMI_VIC_END},
3450000, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
};
/* mode hpll_clk_out od1 od2(PHY) od3
* vid_pll_div vid_clk_div hdmi_tx_pixel_div encp_div enci_div
*/
static struct hw_enc_clk_val_group setting_enc_clk_val_30[] = {
{{HDMI_720x480i60_16x9,
HDMI_720x576i50_16x9,
HDMI_VIC_END},
5405400, 4, 4, 1, VID_PLL_DIV_6p25, 1, 2, -1, 2},
{{HDMI_720x576p50_16x9,
HDMI_720x480p60_16x9,
HDMI_VIC_END},
5405400, 4, 4, 1, VID_PLL_DIV_6p25, 1, 2, 1, -1},
{{HDMI_1280x720p50_16x9,
HDMI_1280x720p60_16x9,
HDMI_VIC_END},
3712500, 4, 1, 1, VID_PLL_DIV_6p25, 1, 2, 1, -1},
{{HDMI_1920x1080i60_16x9,
HDMI_1920x1080i50_16x9,
HDMI_VIC_END},
3712500, 4, 1, 1, VID_PLL_DIV_6p25, 1, 2, 1, -1},
{{HDMI_1920x1080p60_16x9,
HDMI_1920x1080p50_16x9,
HDMI_VIC_END},
3712500, 1, 2, 2, VID_PLL_DIV_6p25, 1, 1, 1, -1},
{{HDMI_1920x1080p30_16x9,
HDMI_1920x1080p24_16x9,
HDMI_1920x1080p25_16x9,
HDMI_VIC_END},
3712500, 2, 2, 2, VID_PLL_DIV_6p25, 1, 1, 1, -1},
{{HDMI_4096x2160p60_256x135_Y420,
HDMI_4096x2160p50_256x135_Y420,
HDMI_3840x2160p60_16x9_Y420,
HDMI_3840x2160p50_16x9_Y420,
HDMI_VIC_END},
3712500, 1, 1, 1, VID_PLL_DIV_6p25, 1, 2, 1, -1},
{{HDMI_3840x2160p24_16x9,
HDMI_3840x2160p25_16x9,
HDMI_3840x2160p30_16x9,
HDMI_4096x2160p24_256x135,
HDMI_4096x2160p25_256x135,
HDMI_4096x2160p30_256x135,
HDMI_VIC_END},
3712500, 1, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
{{HDMI_VIC_FAKE,
HDMI_VIC_END},
3450000, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
};
static struct hw_enc_clk_val_group setting_enc_clk_val_36[] = {
{{HDMI_720x480i60_16x9,
HDMI_720x576i50_16x9,
HDMI_VIC_END},
3243240, 2, 4, 1, VID_PLL_DIV_7p5, 1, 2, -1, 2},
{{HDMI_720x576p50_16x9,
HDMI_720x480p60_16x9,
HDMI_VIC_END},
3243240, 2, 4, 1, VID_PLL_DIV_7p5, 1, 2, 1, -1},
{{HDMI_1280x720p50_16x9,
HDMI_1280x720p60_16x9,
HDMI_VIC_END},
4455000, 4, 1, 1, VID_PLL_DIV_7p5, 1, 2, 1, -1},
{{HDMI_1920x1080i60_16x9,
HDMI_1920x1080i50_16x9,
HDMI_VIC_END},
4455000, 4, 1, 1, VID_PLL_DIV_7p5, 1, 2, 1, -1},
{{HDMI_1920x1080p60_16x9,
HDMI_1920x1080p50_16x9,
HDMI_VIC_END},
4455000, 1, 2, 2, VID_PLL_DIV_7p5, 1, 1, 1, -1},
{{HDMI_1920x1080p30_16x9,
HDMI_1920x1080p24_16x9,
HDMI_1920x1080p25_16x9,
HDMI_VIC_END},
4455000, 2, 2, 2, VID_PLL_DIV_7p5, 1, 1, 1, -1},
{{HDMI_4096x2160p60_256x135_Y420,
HDMI_4096x2160p50_256x135_Y420,
HDMI_3840x2160p60_16x9_Y420,
HDMI_3840x2160p50_16x9_Y420,
HDMI_VIC_END},
4455000, 1, 1, 1, VID_PLL_DIV_7p5, 1, 2, 1, -1},
{{HDMI_3840x2160p24_16x9,
HDMI_3840x2160p25_16x9,
HDMI_3840x2160p30_16x9,
HDMI_4096x2160p24_256x135,
HDMI_4096x2160p25_256x135,
HDMI_4096x2160p30_256x135,
HDMI_VIC_END},
4455000, 1, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
{{HDMI_VIC_FAKE,
HDMI_VIC_END},
3450000, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
};
static struct hw_enc_clk_val_group setting_3dfp_enc_clk_val[] = {
{{HDMI_1920x1080p60_16x9,
HDMI_1920x1080p50_16x9,
HDMI_VIC_END},
2970000, 1, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
{{HDMI_1280x720p50_16x9,
HDMI_1280x720p60_16x9,
HDMI_1920x1080p30_16x9,
HDMI_1920x1080p24_16x9,
HDMI_1920x1080p25_16x9,
HDMI_VIC_END},
2970000, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
{{HDMI_VIC_FAKE,
HDMI_VIC_END},
3450000, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
};
static void hdmitx_set_clk_(enum hdmi_vic vic, enum hdmi_color_depth cd)
{
int i = 0;
int j = 0;
struct hw_enc_clk_val_group *p_enc = NULL;
if (cd == COLORDEPTH_24B) {
p_enc = &setting_enc_clk_val_24[0];
for (j = 0; j < sizeof(setting_enc_clk_val_24)
/ sizeof(struct hw_enc_clk_val_group); j++) {
for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i]
!= HDMI_VIC_END)); i++) {
if (vic == p_enc[j].group[i])
goto next;
}
}
if (j == sizeof(setting_enc_clk_val_24)
/ sizeof(struct hw_enc_clk_val_group)) {
pr_info("Not find VIC = %d for hpll setting\n", vic);
return;
}
} else if (cd == COLORDEPTH_30B) {
p_enc = &setting_enc_clk_val_30[0];
for (j = 0; j < sizeof(setting_enc_clk_val_30)
/ sizeof(struct hw_enc_clk_val_group); j++) {
for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i]
!= HDMI_VIC_END)); i++) {
if (vic == p_enc[j].group[i])
goto next;
}
}
if (j == sizeof(setting_enc_clk_val_30) /
sizeof(struct hw_enc_clk_val_group)) {
pr_info("Not find VIC = %d for hpll setting\n", vic);
return;
}
} else if (cd == COLORDEPTH_36B) {
p_enc = &setting_enc_clk_val_36[0];
for (j = 0; j < sizeof(setting_enc_clk_val_36)
/ sizeof(struct hw_enc_clk_val_group); j++) {
for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i]
!= HDMI_VIC_END)); i++) {
if (vic == p_enc[j].group[i])
goto next;
}
}
if (j == sizeof(setting_enc_clk_val_36) /
sizeof(struct hw_enc_clk_val_group)) {
pr_info("Not find VIC = %d for hpll setting\n", vic);
return;
}
} else {
pr_info("not support colordepth 48bits\n");
return;
}
next:
set_hdmitx_sys_clk();
set_hpll_clk_out(p_enc[j].hpll_clk_out);
if ((cd == COLORDEPTH_24B) && sspll_en)
set_hpll_sspll(vic);
set_hpll_od1(p_enc[j].od1);
set_hpll_od2(p_enc[j].od2);
set_hpll_od3(p_enc[j].od3);
set_hpll_od3_clk_div(p_enc[j].vid_pll_div);
pr_info("j = %d vid_clk_div = %d\n", j, p_enc[j].vid_clk_div);
set_vid_clk_div(p_enc[j].vid_clk_div);
set_hdmi_tx_pixel_div(p_enc[j].hdmi_tx_pixel_div);
set_encp_div(p_enc[j].encp_div);
set_enci_div(p_enc[j].enci_div);
}
static void hdmitx_set_3dfp_clk(enum hdmi_vic vic)
{
int i = 0;
int j = 0;
struct hw_enc_clk_val_group *p_enc = NULL;
p_enc = &setting_3dfp_enc_clk_val[0];
for (j = 0; j < sizeof(setting_3dfp_enc_clk_val)
/ sizeof(struct hw_enc_clk_val_group); j++) {
for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i]
!= HDMI_VIC_END)); i++) {
if (vic == p_enc[j].group[i])
goto next;
}
}
if (j == sizeof(setting_3dfp_enc_clk_val)
/ sizeof(struct hw_enc_clk_val_group)) {
pr_info("Not find VIC = %d for hpll setting\n", vic);
return;
}
next:
set_hdmitx_sys_clk();
set_hpll_clk_out(p_enc[j].hpll_clk_out);
set_hpll_sspll(vic);
set_hpll_od1(p_enc[j].od1);
set_hpll_od2(p_enc[j].od2);
set_hpll_od3(p_enc[j].od3);
set_hpll_od3_clk_div(p_enc[j].vid_pll_div);
pr_info("j = %d vid_clk_div = %d\n", j, p_enc[j].vid_clk_div);
set_vid_clk_div(p_enc[j].vid_clk_div);
set_hdmi_tx_pixel_div(p_enc[j].hdmi_tx_pixel_div);
set_encp_div(p_enc[j].encp_div);
set_enci_div(p_enc[j].enci_div);
}
static int likely_frac_rate_mode(char *m)
{
if (strstr(m, "24hz") || strstr(m, "30hz") || strstr(m, "60hz")
|| strstr(m, "120hz") || strstr(m, "240hz"))
return 1;
else
return 0;
}
void hdmitx_set_clk(struct hdmitx_dev *hdev)
{
enum hdmi_vic vic = hdev->cur_VIC;
struct hdmi_format_para *para = NULL;
frac_rate = hdev->frac_rate_policy;
pr_info("hdmitx: set clk: VIC = %d cd = %d frac_rate = %d\n", vic,
hdev->para->cd, frac_rate);
para = hdmi_get_fmt_paras(vic);
if (para && (para->name) && likely_frac_rate_mode(para->name))
;
else {
pr_info("hdmitx: %s doesn't have frac_rate\n", para->name);
frac_rate = 0;
}
if (hdev->flag_3dfp) {
hdmitx_set_3dfp_clk(vic);
return;
}
if (hdev->para->cs != COLORSPACE_YUV422)
hdmitx_set_clk_(vic, hdev->para->cd);
else
hdmitx_set_clk_(vic, COLORDEPTH_24B);
}
MODULE_PARM_DESC(sspll_en, "\n hdmitx sspll_en\n");
module_param(sspll_en, int, 0664);

58
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.h Normal file
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@@ -0,0 +1,58 @@
/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __HW_ENC_CLK_CONFIG_H__
#define __HW_ENC_CLK_CONFIG_H__
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_common.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
#include <linux/amlogic/media/vout/vinfo.h>
#define VID_PLL_DIV_1 0
#define VID_PLL_DIV_2 1
#define VID_PLL_DIV_3 2
#define VID_PLL_DIV_3p5 3
#define VID_PLL_DIV_3p75 4
#define VID_PLL_DIV_4 5
#define VID_PLL_DIV_5 6
#define VID_PLL_DIV_6 7
#define VID_PLL_DIV_6p25 8
#define VID_PLL_DIV_7 9
#define VID_PLL_DIV_7p5 10
#define VID_PLL_DIV_12 11
#define VID_PLL_DIV_14 12
#define VID_PLL_DIV_15 13
#define VID_PLL_DIV_2p5 14
#define GROUP_MAX 8
struct hw_enc_clk_val_group {
enum hdmi_vic group[GROUP_MAX];
unsigned int hpll_clk_out; /* Unit: kHz */
unsigned int od1;
unsigned int od2; /* HDMI_CLK_TODIG */
unsigned int od3;
unsigned int vid_pll_div;
unsigned int vid_clk_div;
unsigned int hdmi_tx_pixel_div;
unsigned int encp_div;
unsigned int enci_div;
};
void hdmitx_set_clk(struct hdmitx_dev *hdev);
#endif

92
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_gxbb.c Normal file
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@@ -0,0 +1,92 @@
/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_gxbb.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/printk.h>
#include "common.h"
#include "mach_reg.h"
/*
* NAME PAD PINMUX GPIO
* HPD GPIOH_0 reg1[26] GPIO1[16]
* SCL GPIOH_2 reg1[24] GPIO1[18[
* SDA GPIOH_1 reg7[25] GPIO1[17]
*/
int hdmitx_hpd_hw_op_gxbb(enum hpd_op cmd)
{
int ret = 0;
switch (cmd) {
case HPD_INIT_DISABLE_PULLUP:
hd_set_reg_bits(P_PAD_PULL_UP_REG1, 0, 20, 1);
break;
case HPD_INIT_SET_FILTER:
hdmitx_wr_reg(HDMITX_TOP_HPD_FILTER,
((0xa << 12) | (0xa0 << 0)));
break;
case HPD_IS_HPD_MUXED:
ret = !!(hd_read_reg(P_PERIPHS_PIN_MUX_1) & (1 << 26));
break;
case HPD_MUX_HPD:
/* GPIOH_5 input */
hd_set_reg_bits(P_PREG_PAD_GPIO1_EN_N, 1, 21, 1);
/* clear other pinmux */
hd_set_reg_bits(P_PERIPHS_PIN_MUX_1, 0, 19, 1);
hd_set_reg_bits(P_PERIPHS_PIN_MUX_1, 1, 26, 1);
break;
case HPD_UNMUX_HPD:
hd_set_reg_bits(P_PERIPHS_PIN_MUX_1, 0, 26, 1);
/* GPIOH_5 input */
hd_set_reg_bits(P_PREG_PAD_GPIO1_EN_N, 1, 21, 1);
break;
case HPD_READ_HPD_GPIO:
ret = !!(hd_read_reg(P_PREG_PAD_GPIO1_I) & (1 << 20));
break;
default:
pr_info("error hpd cmd %d\n", cmd);
break;
}
return ret;
}
int read_hpd_gpio_gxbb(void)
{
return !!(hd_read_reg(P_PREG_PAD_GPIO1_I) & (1 << 20));
}
int hdmitx_ddc_hw_op_gxbb(enum ddc_op cmd)
{
int ret = 0;
switch (cmd) {
case DDC_INIT_DISABLE_PULL_UP_DN:
hd_set_reg_bits(P_PAD_PULL_UP_EN_REG1, 0, 21, 2);
hd_set_reg_bits(P_PAD_PULL_UP_REG1, 0, 21, 2);
break;
case DDC_MUX_DDC:
hd_set_reg_bits(P_PREG_PAD_GPIO1_EN_N, 3, 21, 2);
hd_set_reg_bits(P_PERIPHS_PIN_MUX_1, 3, 24, 2);
break;
case DDC_UNMUX_DDC:
hd_set_reg_bits(P_PREG_PAD_GPIO1_EN_N, 3, 21, 2);
hd_set_reg_bits(P_PERIPHS_PIN_MUX_1, 0, 24, 2);
break;
default:
pr_info("error ddc cmd %d\n", cmd);
}
return ret;
}

330
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_gxl.c Normal file
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@@ -0,0 +1,330 @@
/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_gxl.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/printk.h>
#include "common.h"
#include "mach_reg.h"
/*
* From GXL chips, registers names changes.
* Added new HHI_HDMI_PLL_CNTL1 but addessed as 0xc9.
* It's different with HHI_HDMI_PLL_CNTL2 0xc9 in previouse chips.
*/
#ifdef P_HHI_HDMI_PLL_CNTL2
#undef P_HHI_HDMI_PLL_CNTL2
#endif
#ifdef P_HHI_HDMI_PLL_CNTL3
#undef P_HHI_HDMI_PLL_CNTL3
#endif
#ifdef P_HHI_HDMI_PLL_CNTL4
#undef P_HHI_HDMI_PLL_CNTL4
#endif
#ifdef P_HHI_HDMI_PLL_CNTL5
#undef P_HHI_HDMI_PLL_CNTL5
#endif
#ifdef P_HHI_HDMI_PLL_CNTL6
#undef P_HHI_HDMI_PLL_CNTL6
#endif
#define P_HHI_HDMI_PLL_CNTL1 (0xc883c000 + (0xc9 << 2))
#define P_HHI_HDMI_PLL_CNTL2 (0xc883c000 + (0xca << 2))
#define P_HHI_HDMI_PLL_CNTL3 (0xc883c000 + (0xcb << 2))
#define P_HHI_HDMI_PLL_CNTL4 (0xc883c000 + (0xcc << 2))
#define P_HHI_HDMI_PLL_CNTL5 (0xc883c000 + (0xcd << 2))
/*
* NAME PAD PINMUX GPIO
* HPD GPIOH_0 reg6[31] GPIO1[20]
* SCL GPIOH_2 reg6[29] GPIO1[22[
* SDA GPIOH_1 reg6[30] GPIO1[21]
*/
int hdmitx_hpd_hw_op_gxl(enum hpd_op cmd)
{
int ret = 0;
switch (cmd) {
case HPD_INIT_DISABLE_PULLUP:
hd_set_reg_bits(P_PAD_PULL_UP_REG1, 0, 25, 1);
break;
case HPD_INIT_SET_FILTER:
hdmitx_wr_reg(HDMITX_TOP_HPD_FILTER,
((0xa << 12) | (0xa0 << 0)));
break;
case HPD_IS_HPD_MUXED:
ret = !!(hd_read_reg(P_PERIPHS_PIN_MUX_6) & (1 << 31));
break;
case HPD_MUX_HPD:
hd_set_reg_bits(P_PREG_PAD_GPIO1_EN_N, 1, 20, 1);
hd_set_reg_bits(P_PERIPHS_PIN_MUX_6, 1, 31, 1);
break;
case HPD_UNMUX_HPD:
hd_set_reg_bits(P_PERIPHS_PIN_MUX_6, 0, 31, 1);
hd_set_reg_bits(P_PREG_PAD_GPIO1_EN_N, 1, 20, 1);
break;
case HPD_READ_HPD_GPIO:
ret = !!(hd_read_reg(P_PREG_PAD_GPIO1_I) & (1 << 20));
break;
default:
pr_info("error hpd cmd %d\n", cmd);
break;
}
return ret;
}
int read_hpd_gpio_gxl(void)
{
return !!(hd_read_reg(P_PREG_PAD_GPIO1_I) & (1 << 20));
}
int hdmitx_ddc_hw_op_gxl(enum ddc_op cmd)
{
int ret = 0;
switch (cmd) {
case DDC_INIT_DISABLE_PULL_UP_DN:
hd_set_reg_bits(P_PAD_PULL_UP_EN_REG1, 0, 23, 2);
hd_set_reg_bits(P_PAD_PULL_UP_REG1, 0, 23, 2);
break;
case DDC_MUX_DDC:
hd_set_reg_bits(P_PREG_PAD_GPIO1_EN_N, 3, 21, 2);
hd_set_reg_bits(P_PERIPHS_PIN_MUX_6, 3, 29, 2);
break;
case DDC_UNMUX_DDC:
hd_set_reg_bits(P_PREG_PAD_GPIO1_EN_N, 3, 21, 2);
hd_set_reg_bits(P_PERIPHS_PIN_MUX_6, 0, 29, 2);
break;
default:
pr_info("error ddc cmd %d\n", cmd);
}
return ret;
}
void set_gxl_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
{
switch (clk) {
case 5940000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x4000027b);
if (frac_rate)
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb281);
else
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb300);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0xc60f30e0);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 5405400:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002e1);
if (frac_rate)
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb000);
else
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb0e6);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 4455000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002b9);
if (frac_rate)
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb1c2);
else
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb280);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 3712500:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x4000029a);
if (frac_rate)
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb222);
else
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb2c0);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 3450000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x4000028f);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb300);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 3243240:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x40000287);
if (frac_rate)
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb000);
else
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb08a);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 2970000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x4000027b);
if (frac_rate)
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb281);
else
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb300);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
case 4324320:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002b4);
if (frac_rate)
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb000);
else
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb0b8);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
break;
default:
pr_info("error hpll clk: %d\n", clk);
break;
}
}
void set_hpll_sspll_gxl(enum hdmi_vic vic)
{
switch (vic) {
case HDMI_1920x1080p60_16x9:
case HDMI_1920x1080p50_16x9:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x68b48c4, 0, 30);
break;
case HDMI_1280x720p60_16x9:
case HDMI_1280x720p50_16x9:
case HDMI_1920x1080i60_16x9:
case HDMI_1920x1080i50_16x9:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x64348c4, 0, 30);
break;
case HDMI_3840x2160p50_16x9:
case HDMI_3840x2160p60_16x9:
case HDMI_4096x2160p50_256x135:
case HDMI_4096x2160p60_256x135:
break;
case HDMI_3840x2160p50_16x9_Y420:
case HDMI_3840x2160p60_16x9_Y420:
case HDMI_4096x2160p50_256x135_Y420:
case HDMI_4096x2160p60_256x135_Y420:
case HDMI_3840x2160p30_16x9:
case HDMI_3840x2160p25_16x9:
case HDMI_3840x2160p24_16x9:
case HDMI_4096x2160p30_256x135:
case HDMI_4096x2160p25_256x135:
case HDMI_4096x2160p24_256x135:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x62b44c4, 0, 30);
break;
default:
break;
}
}
void set_hpll_od1_gxl(unsigned int div)
{
switch (div) {
case 1:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0, 21, 2);
break;
case 2:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 1, 21, 2);
break;
case 4:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 2, 21, 2);
break;
default:
pr_info("Err %s[%d]\n", __func__, __LINE__);
break;
}
}
void set_hpll_od2_gxl(unsigned int div)
{
switch (div) {
case 1:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0, 23, 2);
break;
case 2:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 1, 23, 2);
break;
case 4:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 2, 23, 2);
break;
default:
pr_info("Err %s[%d]\n", __func__, __LINE__);
break;
}
}
void set_hpll_od3_gxl(unsigned int div)
{
switch (div) {
case 1:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0, 19, 2);
break;
case 2:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 1, 19, 2);
break;
case 4:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 2, 19, 2);
break;
default:
pr_info("Err %s[%d]\n", __func__, __LINE__);
break;
}
}

90
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_gxtvbb.c Normal file
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@@ -0,0 +1,90 @@
/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_gxtvbb.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/printk.h>
#include <linux/kernel.h>
#include "common.h"
#include "mach_reg.h"
/*
* NAME PAD PINMUX GPIO
* HPD GPIOH_5 reg7[21] GPIO1[25]
* SCL GPIOH_4 reg7[20] GPIO1[24[
* SDA GPIOH_3 reg7[19] GPIO1[23]
*/
int hdmitx_hpd_hw_op_gxtvbb(enum hpd_op cmd)
{
int ret = 0;
switch (cmd) {
case HPD_INIT_DISABLE_PULLUP:
hd_set_reg_bits(P_PAD_PULL_UP_REG1, 0, 25, 1);
break;
case HPD_INIT_SET_FILTER:
hdmitx_wr_reg(HDMITX_TOP_HPD_FILTER,
((0xa << 12) | (0xa0 << 0)));
break;
case HPD_IS_HPD_MUXED:
ret = !!(hd_read_reg(P_PERIPHS_PIN_MUX_7) & (1 << 21));
break;
case HPD_MUX_HPD:
hd_set_reg_bits(P_PREG_PAD_GPIO1_EN_N, 1, 25, 1);
hd_set_reg_bits(P_PERIPHS_PIN_MUX_7, 0, 23, 1);
hd_set_reg_bits(P_PERIPHS_PIN_MUX_7, 1, 21, 1);
break;
case HPD_UNMUX_HPD:
hd_set_reg_bits(P_PERIPHS_PIN_MUX_7, 0, 21, 1);
hd_set_reg_bits(P_PREG_PAD_GPIO1_EN_N, 1, 25, 1);
break;
case HPD_READ_HPD_GPIO:
ret = !!(hd_read_reg(P_PREG_PAD_GPIO1_I) & (1 << 25));
break;
default:
pr_info("error hpd cmd %d\n", cmd);
break;
}
return ret;
}
int read_hpd_gpio_gxtvbb(void)
{
return !!(hd_read_reg(P_PREG_PAD_GPIO1_I) & (1 << 25));
}
int hdmitx_ddc_hw_op_gxtvbb(enum ddc_op cmd)
{
int ret = 0;
switch (cmd) {
case DDC_INIT_DISABLE_PULL_UP_DN:
hd_set_reg_bits(P_PAD_PULL_UP_EN_REG1, 0, 23, 2);
hd_set_reg_bits(P_PAD_PULL_UP_REG1, 0, 23, 2);
break;
case DDC_MUX_DDC:
hd_set_reg_bits(P_PREG_PAD_GPIO1_EN_N, 3, 24, 2);
hd_set_reg_bits(P_PERIPHS_PIN_MUX_7, 3, 19, 2);
break;
case DDC_UNMUX_DDC:
hd_set_reg_bits(P_PREG_PAD_GPIO1_EN_N, 3, 24, 2);
hd_set_reg_bits(P_PERIPHS_PIN_MUX_7, 0, 19, 2);
break;
default:
pr_info("error ddc cmd %d\n", cmd);
}
return ret;
}

834
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/mach_reg.h Normal file
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@@ -0,0 +1,834 @@
/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/mach_reg.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __MACH_REG_H__
#define __MACH_REG_H__
#include <linux/amlogic/iomap.h>
#include <linux/delay.h>
struct reg_s {
unsigned int reg;
unsigned int val;
};
#define OFFSET 24
#define CBUS_REG_ADDR(reg) ((IO_CBUS_BASE << OFFSET) + (reg << 2))
#define nCBUS_REG_ADDR(reg) (0xc8834400 + (reg << 2))
#define VCBUS_REG_ADDR(reg) (0xd0100000 + (reg << 2))
#define AOBUS_REG_ADDR(reg) ((IO_AOBUS_BASE << OFFSET) + reg)
#define APB_REG_ADDR(reg) ((IO_APB_BUS_BASE << OFFSET) + reg)
unsigned int hd_read_reg(unsigned int addr);
void hd_write_reg(unsigned int addr, unsigned int val);
void hd_set_reg_bits(unsigned int addr, unsigned int value, unsigned int offset,
unsigned int len);
void sec_reg_write(unsigned int *addr, unsigned int value);
unsigned int sec_reg_read(unsigned int *addr);
void init_reg_map(void);
#define WAIT_FOR_PLL_LOCKED(reg) \
do { \
unsigned int st = 0, cnt = 10; \
while (cnt--) { \
udelay(5); \
st = !!(hd_read_reg(reg) & (1 << 31)); \
if (st) \
break; \
else { \
/* reset hpll */ \
hd_set_reg_bits(reg, 1, 28, 1); \
hd_set_reg_bits(reg, 0, 28, 1); \
} \
} \
if (cnt < 9) \
pr_info("pll[0x%x] reset %d times\n", reg, 9 - cnt);\
} while (0)
#define P_PREG_PAD_GPIO6_EN_N nCBUS_REG_ADDR(0x08)
#define P_PREG_PAD_GPIO6_O nCBUS_REG_ADDR(0x09)
#define P_PREG_PAD_GPIO6_I nCBUS_REG_ADDR(0x0a)
#define P_PREG_JTAG_GPIO_ADDR nCBUS_REG_ADDR(0x0b)
#define P_PREG_PAD_GPIO0_EN_N nCBUS_REG_ADDR(0x0c)
#define P_PREG_PAD_GPIO0_O nCBUS_REG_ADDR(0x0d)
#define P_PREG_PAD_GPIO0_I nCBUS_REG_ADDR(0x0e)
#define P_PREG_PAD_GPIO1_EN_N nCBUS_REG_ADDR(0x0f)
#define P_PREG_PAD_GPIO1_O nCBUS_REG_ADDR(0x10)
#define P_PREG_PAD_GPIO1_I nCBUS_REG_ADDR(0x11)
#define P_PREG_PAD_GPIO2_EN_N nCBUS_REG_ADDR(0x12)
#define P_PREG_PAD_GPIO2_O nCBUS_REG_ADDR(0x13)
#define P_PREG_PAD_GPIO2_I nCBUS_REG_ADDR(0x14)
#define P_PREG_PAD_GPIO3_EN_N nCBUS_REG_ADDR(0x15)
#define P_PREG_PAD_GPIO3_O nCBUS_REG_ADDR(0x16)
#define P_PREG_PAD_GPIO3_I nCBUS_REG_ADDR(0x17)
#define P_PREG_PAD_GPIO4_EN_N nCBUS_REG_ADDR(0x18)
#define P_PREG_PAD_GPIO4_O nCBUS_REG_ADDR(0x19)
#define P_PREG_PAD_GPIO4_I nCBUS_REG_ADDR(0x1a)
#define P_PREG_PAD_GPIO5_EN_N nCBUS_REG_ADDR(0x1b)
#define P_PREG_PAD_GPIO5_O nCBUS_REG_ADDR(0x1c)
#define P_PREG_PAD_GPIO5_I nCBUS_REG_ADDR(0x1d)
#define PERIPHS_PIN_MUX_0 0x2c /* register.h:419 */
#define P_PERIPHS_PIN_MUX_0 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_0)
#define PERIPHS_PIN_MUX_1 0x2d /* register.h:420 */
#define P_PERIPHS_PIN_MUX_1 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
#define PERIPHS_PIN_MUX_2 0x2e /* register.h:421 */
#define P_PERIPHS_PIN_MUX_2 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
#define PERIPHS_PIN_MUX_3 0x2f /* register.h:422 */
#define P_PERIPHS_PIN_MUX_3 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_3)
#define PERIPHS_PIN_MUX_4 0x30 /* register.h:423 */
#define P_PERIPHS_PIN_MUX_4 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_4)
#define PERIPHS_PIN_MUX_5 0x31 /* register.h:424 */
#define P_PERIPHS_PIN_MUX_5 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_5)
#define PERIPHS_PIN_MUX_6 0x32 /* register.h:425 */
#define P_PERIPHS_PIN_MUX_6 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_6)
#define PERIPHS_PIN_MUX_7 0x33 /* register.h:426 */
#define P_PERIPHS_PIN_MUX_7 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_7)
#define PERIPHS_PIN_MUX_8 0x34 /* register.h:427 */
#define P_PERIPHS_PIN_MUX_8 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_8)
#define PERIPHS_PIN_MUX_9 0x35 /* register.h:428 */
#define P_PERIPHS_PIN_MUX_9 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_9)
#define PERIPHS_PIN_MUX_10 0x36 /* register.h:429 */
#define P_PERIPHS_PIN_MUX_10 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_10)
#define PERIPHS_PIN_MUX_11 0x37 /* register.h:430 */
#define P_PERIPHS_PIN_MUX_11 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_11)
#define PERIPHS_PIN_MUX_12 0x38 /* register.h:431 */
#define P_PERIPHS_PIN_MUX_12 nCBUS_REG_ADDR(PERIPHS_PIN_MUX_12)
#define PAD_PULL_UP_REG0 0x3a
#define P_PAD_PULL_UP_REG0 nCBUS_REG_ADDR(PAD_PULL_UP_REG0)
#define PAD_PULL_UP_REG1 0x3d
#define P_PAD_PULL_UP_REG1 nCBUS_REG_ADDR(PAD_PULL_UP_REG1)
#define PAD_PULL_UP_REG2 0x3c
#define P_PAD_PULL_UP_REG2 nCBUS_REG_ADDR(PAD_PULL_UP_REG2)
#define PAD_PULL_UP_REG3 0x3d
#define P_PAD_PULL_UP_REG3 nCBUS_REG_ADDR(PAD_PULL_UP_REG3)
#define PAD_PULL_UP_REG4 0x3d
#define P_PAD_PULL_UP_REG4 nCBUS_REG_ADDR(PAD_PULL_UP_REG4)
#define PAD_PULL_UP_EN_REG0 0x48
#define P_PAD_PULL_UP_EN_REG0 nCBUS_REG_ADDR(PAD_PULL_UP_EN_REG0)
#define PAD_PULL_UP_EN_REG1 0x49
#define P_PAD_PULL_UP_EN_REG1 nCBUS_REG_ADDR(PAD_PULL_UP_EN_REG1)
#define PAD_PULL_UP_EN_REG2 0x4a
#define P_PAD_PULL_UP_EN_REG2 nCBUS_REG_ADDR(PAD_PULL_UP_EN_REG2)
#define PAD_PULL_UP_EN_REG3 0x4b
#define P_PAD_PULL_UP_EN_REG3 nCBUS_REG_ADDR(PAD_PULL_UP_EN_REG3)
#define PAD_PULL_UP_EN_REG4 0x4c
#define P_PAD_PULL_UP_EN_REG4 nCBUS_REG_ADDR(PAD_PULL_UP_EN_REG4)
#define P_HHI_MEM_PD_REG0 (0xc883c000 + (0x40 << 2))
#define P_HHI_VPU_MEM_PD_REG0 (0xc883c000 + (0x41 << 2))
#define P_HHI_VPU_MEM_PD_REG1 (0xc883c000 + (0x42 << 2))
#define P_HHI_AUD_DAC_CTRL (0xc883c000 + (0x44 << 2))
#define P_HHI_VIID_CLK_DIV (0xc883c000 + (0x4a << 2))
/* [19] -enable clk_div0 */
/* [18:16] - cntl_clk_in_sel */
#define P_HHI_VIID_CLK_CNTL (0xc883c000 + (0x4b << 2))
#define P_HHI_VIID_DIVIDER_CNTL (0xc883c000 + (0x4c << 2))
/*
*========================================================================
* Global Control Registers (12'h000 - 12'h0ff)
*
*========================================================================
* -----------------------------------------------
* CBUS_BASE: RESET_CBUS_BASE = 0x11
* -----------------------------------------------
*/
#define P_VERSION_CTRL ((0x00 << 2) + 0xc1104400)
#define P_RESET0_REGISTER ((0x01 << 2) + 0xc1104400)
#define P_RESET1_REGISTER ((0x02 << 2) + 0xc1104400)
#define P_RESET2_REGISTER ((0x03 << 2) + 0xc1104400)
#define P_RESET3_REGISTER ((0x04 << 2) + 0xc1104400)
#define P_RESET4_REGISTER ((0x05 << 2) + 0xc1104400)
#define P_RESET5_REGISTER ((0x06 << 2) + 0xc1104400)
#define P_RESET6_REGISTER ((0x07 << 2) + 0xc1104400)
#define P_RESET7_REGISTER ((0x08 << 2) + 0xc1104400)
#define P_RESET0_MASK ((0x10 << 2) + 0xc1104400)
#define P_RESET1_MASK ((0x11 << 2) + 0xc1104400)
#define P_RESET2_MASK ((0x12 << 2) + 0xc1104400)
#define P_RESET3_MASK ((0x13 << 2) + 0xc1104400)
#define P_RESET4_MASK ((0x14 << 2) + 0xc1104400)
#define P_RESET5_MASK ((0x15 << 2) + 0xc1104400)
#define P_RESET6_MASK ((0x16 << 2) + 0xc1104400)
/* Gated clock enables.
* There are 64 enables for the MPEG clocks and 32 enables for other
* clock domains.
*/
#define P_HHI_GCLK_MPEG0 (0xc883c000 + (0x50 << 2))
#define P_HHI_GCLK_MPEG1 (0xc883c000 + (0x51 << 2))
#define P_HHI_GCLK_MPEG2 (0xc883c000 + (0x52 << 2))
#define P_HHI_GCLK_OTHER (0xc883c000 + (0x54 << 2))
#define P_HHI_GCLK_AO (0xc883c000 + (0x55 << 2))
#define P_HHI_SYS_OSCIN_CNTL (0xc883c000 + (0x56 << 2))
#define P_HHI_SYS_CPU_CLK_CNTL1 (0xc883c000 + (0x57 << 2))
#define P_HHI_SYS_CPU_RESET_CNTL (0xc883c000 + (0x58 << 2))
/* [7:0] - cntl_xd0 */
#define P_HHI_VID_CLK_DIV (0xc883c000 + (0x59 << 2))
#define P_HHI_MPEG_CLK_CNTL (0xc883c000 + (0x5d << 2))
#define P_HHI_AUD_CLK_CNTL (0xc883c000 + (0x5e << 2))
/* [18:16] - cntl_clk_in_sel */
#define P_HHI_VID_CLK_CNTL (0xc883c000 + (0x5f << 2))
#define P_HHI_WIFI_CLK_CNTL (0xc883c000 + (0x60 << 2))
#define P_HHI_WIFI_PLL_CNTL (0xc883c000 + (0x61 << 2))
#define P_HHI_WIFI_PLL_CNTL2 (0xc883c000 + (0x62 << 2))
#define P_HHI_WIFI_PLL_CNTL3 (0xc883c000 + (0x63 << 2))
#define P_HHI_AUD_CLK_CNTL2 (0xc883c000 + (0x64 << 2))
#define P_HHI_VID_CLK_CNTL2 (0xc883c000 + (0x65 << 2))
#define P_HHI_VID_DIVIDER_CNTL (0xc883c000 + (0x66 << 2))
#define P_HHI_SYS_CPU_CLK_CNTL (0xc883c000 + (0x67 << 2))
#define P_HHI_VID_PLL_CLK_DIV (0xc883c000 + (0x68 << 2))
#define P_HHI_AUD_CLK_CNTL3 (0xc883c000 + (0x69 << 2))
#define P_HHI_MALI_CLK_CNTL (0xc883c000 + (0x6c << 2))
#define P_HHI_MIPI_PHY_CLK_CNTL (0xc883c000 + (0x6e << 2))
#define P_HHI_VPU_CLK_CNTL (0xc883c000 + (0x6f << 2))
#define P_HHI_OTHER_PLL_CNTL (0xc883c000 + (0x70 << 2))
#define P_HHI_OTHER_PLL_CNTL2 (0xc883c000 + (0x71 << 2))
#define P_HHI_OTHER_PLL_CNTL3 (0xc883c000 + (0x72 << 2))
#define P_HHI_HDMI_CLK_CNTL (0xc883c000 + (0x73 << 2))
#define P_HHI_DEMOD_CLK_CNTL (0xc883c000 + (0x74 << 2))
#define P_HHI_SATA_CLK_CNTL (0xc883c000 + (0x75 << 2))
#define P_HHI_ETH_CLK_CNTL (0xc883c000 + (0x76 << 2))
#define P_HHI_CLK_DOUBLE_CNTL (0xc883c000 + (0x77 << 2))
#define P_HHI_VDEC_CLK_CNTL (0xc883c000 + (0x78 << 2))
#define P_HHI_VDEC2_CLK_CNTL (0xc883c000 + (0x79 << 2))
#define P_HHI_VDEC3_CLK_CNTL (0xc883c000 + (0x7a << 2))
#define P_HHI_VDEC4_CLK_CNTL (0xc883c000 + (0x7b << 2))
#define P_HHI_HDCP22_CLK_CNTL (0xc883c000 + (0x7c << 2))
#define P_HHI_VAPBCLK_CNTL (0xc883c000 + (0x7d << 2))
#define P_HHI_VP9DEC_CLK_CNTL (0xc883c000 + (0x7e << 2))
#define P_HHI_HDMI_AFC_CNTL (0xc883c000 + (0x7f << 2))
#define P_HHI_HDMIRX_CLK_CNTL (0xc883c000 + (0x80 << 2))
#define P_HHI_HDMIRX_AUD_CLK_CNTL (0xc883c000 + (0x81 << 2))
#define P_HHI_EDP_APB_CLK_CNTL (0xc883c000 + (0x82 << 2))
#define P_HHI_VPU_CLKB_CNTL (0xc883c000 + (0x83 << 2))
#define P_HHI_VID_PLL_MOD_CNTL0 (0xc883c000 + (0x84 << 2))
#define P_HHI_VID_PLL_MOD_LOW_TCNT (0xc883c000 + (0x85 << 2))
#define P_HHI_VID_PLL_MOD_HIGH_TCNT (0xc883c000 + (0x86 << 2))
#define P_HHI_VID_PLL_MOD_NOM_TCNT (0xc883c000 + (0x87 << 2))
#define P_HHI_USB_CLK_CNTL (0xc883c000 + (0x88 << 2))
#define P_HHI_32K_CLK_CNTL (0xc883c000 + (0x89 << 2))
#define P_HHI_GEN_CLK_CNTL (0xc883c000 + (0x8a << 2))
#define P_HHI_GEN_CLK_CNTL2 (0xc883c000 + (0x8b << 2))
#define P_HHI_JTAG_CONFIG (0xc883c000 + (0x8e << 2))
#define P_HHI_VAFE_CLKXTALIN_CNTL (0xc883c000 + (0x8f << 2))
#define P_HHI_VAFE_CLKOSCIN_CNTL (0xc883c000 + (0x90 << 2))
#define P_HHI_VAFE_CLKIN_CNTL (0xc883c000 + (0x91 << 2))
#define P_HHI_TVFE_AUTOMODE_CLK_CNTL (0xc883c000 + (0x92 << 2))
#define P_HHI_VAFE_CLKPI_CNTL (0xc883c000 + (0x93 << 2))
#define P_HHI_VDIN_MEAS_CLK_CNTL (0xc883c000 + (0x94 << 2))
#define P_HHI_PCM_CLK_CNTL (0xc883c000 + (0x96 << 2))
#define P_HHI_NAND_CLK_CNTL (0xc883c000 + (0x97 << 2))
#define P_HHI_ISP_LED_CLK_CNTL (0xc883c000 + (0x98 << 2))
#define P_HHI_SD_EMMC_CLK_CNTL (0xc883c000 + (0x99 << 2))
#define P_HHI_EDP_TX_PHY_CNTL0 (0xc883c000 + (0x9c << 2))
#define P_HHI_EDP_TX_PHY_CNTL1 (0xc883c000 + (0x9d << 2))
#define P_HHI_MPLL_CNTL (0xc883c000 + (0xa0 << 2))
#define P_HHI_MPLL_CNTL2 (0xc883c000 + (0xa1 << 2))
#define P_HHI_MPLL_CNTL3 (0xc883c000 + (0xa2 << 2))
#define P_HHI_MPLL_CNTL4 (0xc883c000 + (0xa3 << 2))
#define P_HHI_MPLL_CNTL5 (0xc883c000 + (0xa4 << 2))
#define P_HHI_MPLL_CNTL6 (0xc883c000 + (0xa5 << 2))
#define P_HHI_MPLL_CNTL7 (0xc883c000 + (0xa6 << 2))
#define P_HHI_MPLL_CNTL8 (0xc883c000 + (0xa7 << 2))
#define P_HHI_MPLL_CNTL9 (0xc883c000 + (0xa8 << 2))
#define P_HHI_MPLL_CNTL10 (0xc883c000 + (0xa9 << 2))
#define P_HHI_ADC_PLL_CNTL (0xc883c000 + (0xaa << 2))
#define P_HHI_ADC_PLL_CNTL2 (0xc883c000 + (0xab << 2))
#define P_HHI_ADC_PLL_CNTL3 (0xc883c000 + (0xac << 2))
#define P_HHI_ADC_PLL_CNTL4 (0xc883c000 + (0xad << 2))
#define P_HHI_ADC_PLL_CNTL_I (0xc883c000 + (0xae << 2))
#define P_HHI_AUDCLK_PLL_CNTL (0xc883c000 + (0xb0 << 2))
#define P_HHI_AUDCLK_PLL_CNTL2 (0xc883c000 + (0xb1 << 2))
#define P_HHI_AUDCLK_PLL_CNTL3 (0xc883c000 + (0xb2 << 2))
#define P_HHI_AUDCLK_PLL_CNTL4 (0xc883c000 + (0xb3 << 2))
#define P_HHI_AUDCLK_PLL_CNTL5 (0xc883c000 + (0xb4 << 2))
#define P_HHI_AUDCLK_PLL_CNTL6 (0xc883c000 + (0xb5 << 2))
#define P_HHI_L2_DDR_CLK_CNTL (0xc883c000 + (0xb6 << 2))
#define P_HHI_MPLL3_CNTL0 (0xc883c000 + (0xb8 << 2))
#define P_HHI_MPLL3_CNTL1 (0xc883c000 + (0xb9 << 2))
#define P_HHI_VDAC_CNTL0 (0xc883c000 + (0xbd << 2))
#define P_HHI_VDAC_CNTL1 (0xc883c000 + (0xbe << 2))
#define P_HHI_SYS_PLL_CNTL (0xc883c000 + (0xc0 << 2))
#define P_HHI_SYS_PLL_CNTL2 (0xc883c000 + (0xc1 << 2))
#define P_HHI_SYS_PLL_CNTL3 (0xc883c000 + (0xc2 << 2))
#define P_HHI_SYS_PLL_CNTL4 (0xc883c000 + (0xc3 << 2))
#define P_HHI_SYS_PLL_CNTL5 (0xc883c000 + (0xc4 << 2))
#define P_HHI_DPLL_TOP_I (0xc883c000 + (0xc6 << 2))
#define P_HHI_DPLL_TOP2_I (0xc883c000 + (0xc7 << 2))
#define P_HHI_HDMI_PLL_CNTL (0xc883c000 + (0xc8 << 2))
#define P_HHI_HDMI_PLL_CNTL2 (0xc883c000 + (0xc9 << 2))
#define P_HHI_HDMI_PLL_CNTL3 (0xc883c000 + (0xca << 2))
#define P_HHI_HDMI_PLL_CNTL4 (0xc883c000 + (0xcb << 2))
#define P_HHI_HDMI_PLL_CNTL5 (0xc883c000 + (0xcc << 2))
#define P_HHI_HDMI_PLL_CNTL6 (0xc883c000 + (0xcd << 2))
#define P_HHI_HDMI_PLL_CNTL_I (0xc883c000 + (0xce << 2))
#define P_HHI_HDMI_PLL_CNTL7 (0xc883c000 + (0xcf << 2))
#define P_HHI_DSI_LVDS_EDP_CNTL0 (0xc883c000 + (0xd1 << 2))
#define P_HHI_DSI_LVDS_EDP_CNTL1 (0xc883c000 + (0xd2 << 2))
#define P_HHI_CSI_PHY_CNTL0 (0xc883c000 + (0xd3 << 2))
#define P_HHI_CSI_PHY_CNTL1 (0xc883c000 + (0xd4 << 2))
#define P_HHI_CSI_PHY_CNTL2 (0xc883c000 + (0xd5 << 2))
#define P_HHI_CSI_PHY_CNTL3 (0xc883c000 + (0xd6 << 2))
#define P_HHI_CSI_PHY_CNTL4 (0xc883c000 + (0xd7 << 2))
#define P_HHI_DIF_CSI_PHY_CNTL0 (0xc883c000 + (0xd8 << 2))
#define P_HHI_DIF_CSI_PHY_CNTL1 (0xc883c000 + (0xd9 << 2))
#define P_HHI_DIF_CSI_PHY_CNTL2 (0xc883c000 + (0xda << 2))
#define P_HHI_DIF_CSI_PHY_CNTL3 (0xc883c000 + (0xdb << 2))
#define P_HHI_DIF_CSI_PHY_CNTL4 (0xc883c000 + (0xdc << 2))
#define P_HHI_DIF_CSI_PHY_CNTL5 (0xc883c000 + (0xdd << 2))
#define P_HHI_LVDS_TX_PHY_CNTL0 (0xc883c000 + (0xde << 2))
#define P_HHI_LVDS_TX_PHY_CNTL1 (0xc883c000 + (0xdf << 2))
#define P_HHI_VID2_PLL_CNTL (0xc883c000 + (0xe0 << 2))
#define P_HHI_VID2_PLL_CNTL2 (0xc883c000 + (0xe1 << 2))
#define P_HHI_VID2_PLL_CNTL3 (0xc883c000 + (0xe2 << 2))
#define P_HHI_VID2_PLL_CNTL4 (0xc883c000 + (0xe3 << 2))
#define P_HHI_VID2_PLL_CNTL5 (0xc883c000 + (0xe4 << 2))
#define P_HHI_VID2_PLL_CNTL_I (0xc883c000 + (0xe5 << 2))
#define P_HHI_HDMI_PHY_CNTL0 (0xc883c000 + (0xe8 << 2))
#define P_HHI_HDMI_PHY_CNTL1 (0xc883c000 + (0xe9 << 2))
#define P_HHI_HDMI_PHY_CNTL2 (0xc883c000 + (0xea << 2))
#define P_HHI_HDMI_PHY_CNTL3 (0xc883c000 + (0xeb << 2))
#define P_HHI_VID_LOCK_CLK_CNTL (0xc883c000 + (0xf2 << 2))
#define P_HHI_ATV_DMD_SYS_CLK_CNTL (0xc883c000 + (0xf3 << 2))
#define P_HHI_BT656_CLK_CNTL (0xc883c000 + (0xf5 << 2))
#define P_HHI_SAR_CLK_CNTL (0xc883c000 + (0xf6 << 2))
#define P_HHI_HDMIRX_AUD_PLL_CNTL (0xc883c000 + (0xf8 << 2))
#define P_HHI_HDMIRX_AUD_PLL_CNTL2 (0xc883c000 + (0xf9 << 2))
#define P_HHI_HDMIRX_AUD_PLL_CNTL3 (0xc883c000 + (0xfa << 2))
#define P_HHI_HDMIRX_AUD_PLL_CNTL4 (0xc883c000 + (0xfb << 2))
#define P_HHI_HDMIRX_AUD_PLL_CNTL5 (0xc883c000 + (0xfc << 2))
#define P_HHI_HDMIRX_AUD_PLL_CNTL6 (0xc883c000 + (0xfd << 2))
#define P_HHI_HDMIRX_AUD_PLL_CNTL_I (0xc883c000 + (0xfe << 2))
#define AIU_HDMI_CLK_DATA_CTRL 0x152a /* register.h:2466 */
#define P_AIU_HDMI_CLK_DATA_CTRL CBUS_REG_ADDR(AIU_HDMI_CLK_DATA_CTRL)
#define ISA_DEBUG_REG0 0x2600
#define P_ISA_DEBUG_REG0 CBUS_REG_ADDR(ISA_DEBUG_REG0)
#define VENC_DVI_SETTING 0x1b62 /* register.h:8014 */
#define P_VENC_DVI_SETTING VCBUS_REG_ADDR(VENC_DVI_SETTING)
#define VENC_VIDEO_TST_EN 0x1b70
#define P_VENC_VIDEO_TST_EN VCBUS_REG_ADDR(VENC_VIDEO_TST_EN)
#define VENC_VIDEO_TST_MDSEL 0x1b71
#define P_VENC_VIDEO_TST_MDSEL VCBUS_REG_ADDR(VENC_VIDEO_TST_MDSEL)
#define VENC_VIDEO_TST_Y 0x1b72
#define P_VENC_VIDEO_TST_Y VCBUS_REG_ADDR(VENC_VIDEO_TST_Y)
#define VENC_VIDEO_TST_CB 0x1b73
#define P_VENC_VIDEO_TST_CB VCBUS_REG_ADDR(VENC_VIDEO_TST_CB)
#define VENC_VIDEO_TST_CR 0x1b74
#define P_VENC_VIDEO_TST_CR VCBUS_REG_ADDR(VENC_VIDEO_TST_CR)
#define VENC_VIDEO_TST_CLRBAR_STRT 0x1b75
#define P_VENC_VIDEO_TST_CLRBAR_STRT VCBUS_REG_ADDR(VENC_VIDEO_TST_CLRBAR_STRT)
#define VENC_VIDEO_TST_CLRBAR_WIDTH 0x1b76
#define P_VENC_VIDEO_TST_CLRBAR_WIDTH \
VCBUS_REG_ADDR(VENC_VIDEO_TST_CLRBAR_WIDTH)
#define VENC_VIDEO_TST_VDCNT_STSET 0x1b77
#define P_VENC_VIDEO_TST_VDCNT_STSET VCBUS_REG_ADDR(VENC_VIDEO_TST_VDCNT_STSET)
#define VENC_VDAC_SETTING 0x1b7e
#define P_VENC_VDAC_SETTING VCBUS_REG_ADDR(VENC_VDAC_SETTING)
#define ENCP_VIDEO_EN 0x1b80 /* register.h:8078 */
#define P_ENCP_VIDEO_EN VCBUS_REG_ADDR(ENCP_VIDEO_EN)
#define ENCP_VIDEO_SYNC_MODE 0x1b81 /* register.h:8079 */
#define P_ENCP_VIDEO_SYNC_MODE VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_MODE)
#define ENCP_MACV_EN 0x1b82 /* register.h:8080 */
#define P_ENCP_MACV_EN VCBUS_REG_ADDR(ENCP_MACV_EN)
#define ENCP_VIDEO_Y_SCL 0x1b83 /* register.h:8081 */
#define P_ENCP_VIDEO_Y_SCL VCBUS_REG_ADDR(ENCP_VIDEO_Y_SCL)
#define ENCP_VIDEO_PB_SCL 0x1b84 /* register.h:8082 */
#define P_ENCP_VIDEO_PB_SCL VCBUS_REG_ADDR(ENCP_VIDEO_PB_SCL)
#define ENCP_VIDEO_PR_SCL 0x1b85 /* register.h:8083 */
#define P_ENCP_VIDEO_PR_SCL VCBUS_REG_ADDR(ENCP_VIDEO_PR_SCL)
#define ENCP_VIDEO_SYNC_SCL 0x1b86 /* register.h:8084 */
#define P_ENCP_VIDEO_SYNC_SCL VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_SCL)
#define ENCP_VIDEO_MACV_SCL 0x1b87 /* register.h:8085 */
#define P_ENCP_VIDEO_MACV_SCL VCBUS_REG_ADDR(ENCP_VIDEO_MACV_SCL)
#define ENCP_VIDEO_Y_OFFST 0x1b88 /* register.h:8086 */
#define P_ENCP_VIDEO_Y_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_Y_OFFST)
#define ENCP_VIDEO_PB_OFFST 0x1b89 /* register.h:8087 */
#define P_ENCP_VIDEO_PB_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_PB_OFFST)
#define ENCP_VIDEO_PR_OFFST 0x1b8a /* register.h:8088 */
#define P_ENCP_VIDEO_PR_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_PR_OFFST)
#define ENCP_VIDEO_SYNC_OFFST 0x1b8b /* register.h:8089 */
#define P_ENCP_VIDEO_SYNC_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_OFFST)
#define ENCP_VIDEO_MACV_OFFST 0x1b8c /* register.h:8090 */
#define P_ENCP_VIDEO_MACV_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_MACV_OFFST)
#define ENCP_VIDEO_MODE 0x1b8d /* register.h:8092 */
#define P_ENCP_VIDEO_MODE VCBUS_REG_ADDR(ENCP_VIDEO_MODE)
#define ENCP_VIDEO_MODE_ADV 0x1b8e /* register.h:8093 */
#define P_ENCP_VIDEO_MODE_ADV VCBUS_REG_ADDR(ENCP_VIDEO_MODE_ADV)
#define ENCP_DBG_PX_RST 0x1b90 /* register.h:8095 */
#define P_ENCP_DBG_PX_RST VCBUS_REG_ADDR(ENCP_DBG_PX_RST)
#define ENCP_DBG_LN_RST 0x1b91 /* register.h:8096 */
#define P_ENCP_DBG_LN_RST VCBUS_REG_ADDR(ENCP_DBG_LN_RST)
#define ENCP_DBG_PX_INT 0x1b92 /* register.h:8097 */
#define P_ENCP_DBG_PX_INT VCBUS_REG_ADDR(ENCP_DBG_PX_INT)
#define ENCP_DBG_LN_INT 0x1b93 /* register.h:8098 */
#define P_ENCP_DBG_LN_INT VCBUS_REG_ADDR(ENCP_DBG_LN_INT)
#define ENCP_VIDEO_YFP1_HTIME 0x1b94 /* register.h:8100 */
#define P_ENCP_VIDEO_YFP1_HTIME VCBUS_REG_ADDR(ENCP_VIDEO_YFP1_HTIME)
#define ENCP_VIDEO_YFP2_HTIME 0x1b95 /* register.h:8101 */
#define P_ENCP_VIDEO_YFP2_HTIME VCBUS_REG_ADDR(ENCP_VIDEO_YFP2_HTIME)
#define ENCP_VIDEO_YC_DLY 0x1b96 /* register.h:8102 */
#define P_ENCP_VIDEO_YC_DLY VCBUS_REG_ADDR(ENCP_VIDEO_YC_DLY)
#define ENCP_VIDEO_MAX_PXCNT 0x1b97 /* register.h:8103 */
#define P_ENCP_VIDEO_MAX_PXCNT VCBUS_REG_ADDR(ENCP_VIDEO_MAX_PXCNT)
#define ENCP_VIDEO_HSPULS_BEGIN 0x1b98 /* register.h:8104 */
#define P_ENCP_VIDEO_HSPULS_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_HSPULS_BEGIN)
#define ENCP_VIDEO_HSPULS_END 0x1b99 /* register.h:8105 */
#define P_ENCP_VIDEO_HSPULS_END VCBUS_REG_ADDR(ENCP_VIDEO_HSPULS_END)
#define ENCP_VIDEO_HSPULS_SWITCH 0x1b9a /* register.h:8106 */
#define P_ENCP_VIDEO_HSPULS_SWITCH VCBUS_REG_ADDR(ENCP_VIDEO_HSPULS_SWITCH)
#define ENCP_VIDEO_VSPULS_BEGIN 0x1b9b /* register.h:8107 */
#define P_ENCP_VIDEO_VSPULS_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_VSPULS_BEGIN)
#define ENCP_VIDEO_VSPULS_END 0x1b9c /* register.h:8108 */
#define P_ENCP_VIDEO_VSPULS_END VCBUS_REG_ADDR(ENCP_VIDEO_VSPULS_END)
#define ENCP_VIDEO_VSPULS_BLINE 0x1b9d /* register.h:8109 */
#define P_ENCP_VIDEO_VSPULS_BLINE VCBUS_REG_ADDR(ENCP_VIDEO_VSPULS_BLINE)
#define ENCP_VIDEO_VSPULS_ELINE 0x1b9e /* register.h:8110 */
#define P_ENCP_VIDEO_VSPULS_ELINE VCBUS_REG_ADDR(ENCP_VIDEO_VSPULS_ELINE)
#define ENCP_VIDEO_EQPULS_BEGIN 0x1b9f /* register.h:8111 */
#define P_ENCP_VIDEO_EQPULS_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_EQPULS_BEGIN)
#define ENCP_VIDEO_EQPULS_END 0x1ba0 /* register.h:8112 */
#define P_ENCP_VIDEO_EQPULS_END VCBUS_REG_ADDR(ENCP_VIDEO_EQPULS_END)
#define ENCP_VIDEO_EQPULS_BLINE 0x1ba1 /* register.h:8113 */
#define P_ENCP_VIDEO_EQPULS_BLINE VCBUS_REG_ADDR(ENCP_VIDEO_EQPULS_BLINE)
#define ENCP_VIDEO_EQPULS_ELINE 0x1ba2 /* register.h:8114 */
#define P_ENCP_VIDEO_EQPULS_ELINE VCBUS_REG_ADDR(ENCP_VIDEO_EQPULS_ELINE)
#define ENCP_VIDEO_HAVON_END 0x1ba3 /* register.h:8115 */
#define P_ENCP_VIDEO_HAVON_END VCBUS_REG_ADDR(ENCP_VIDEO_HAVON_END)
#define ENCP_VIDEO_HAVON_BEGIN 0x1ba4 /* register.h:8116 */
#define P_ENCP_VIDEO_HAVON_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_HAVON_BEGIN)
#define ENCP_VIDEO_VAVON_ELINE 0x1baf /* register.h:8117 */
#define P_ENCP_VIDEO_VAVON_ELINE VCBUS_REG_ADDR(ENCP_VIDEO_VAVON_ELINE)
#define ENCP_VIDEO_VAVON_BLINE 0x1ba6 /* register.h:8118 */
#define P_ENCP_VIDEO_VAVON_BLINE VCBUS_REG_ADDR(ENCP_VIDEO_VAVON_BLINE)
#define ENCP_VIDEO_HSO_BEGIN 0x1ba7 /* register.h:8119 */
#define P_ENCP_VIDEO_HSO_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_HSO_BEGIN)
#define ENCP_VIDEO_HSO_END 0x1ba8 /* register.h:8120 */
#define P_ENCP_VIDEO_HSO_END VCBUS_REG_ADDR(ENCP_VIDEO_HSO_END)
#define ENCP_VIDEO_VSO_BEGIN 0x1ba9 /* register.h:8121 */
#define P_ENCP_VIDEO_VSO_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_VSO_BEGIN)
#define ENCP_VIDEO_VSO_END 0x1baa /* register.h:8122 */
#define P_ENCP_VIDEO_VSO_END VCBUS_REG_ADDR(ENCP_VIDEO_VSO_END)
#define ENCP_VIDEO_VSO_BLINE 0x1bab /* register.h:8123 */
#define P_ENCP_VIDEO_VSO_BLINE VCBUS_REG_ADDR(ENCP_VIDEO_VSO_BLINE)
#define ENCP_VIDEO_VSO_ELINE 0x1bac /* register.h:8124 */
#define P_ENCP_VIDEO_VSO_ELINE VCBUS_REG_ADDR(ENCP_VIDEO_VSO_ELINE)
#define ENCP_VIDEO_SYNC_WAVE_CURVE 0x1bad /* register.h:8125 */
#define P_ENCP_VIDEO_SYNC_WAVE_CURVE VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_WAVE_CURVE)
#define ENCP_VIDEO_MAX_LNCNT 0x1bae /* register.h:8126 */
#define P_ENCP_VIDEO_MAX_LNCNT VCBUS_REG_ADDR(ENCP_VIDEO_MAX_LNCNT)
#define ENCP_VIDEO_SY_VAL 0x1bb0 /* register.h:8127 */
#define P_ENCP_VIDEO_SY_VAL VCBUS_REG_ADDR(ENCP_VIDEO_SY_VAL)
#define ENCP_VIDEO_SY2_VAL 0x1bb1 /* register.h:8128 */
#define P_ENCP_VIDEO_SY2_VAL VCBUS_REG_ADDR(ENCP_VIDEO_SY2_VAL)
#define ENCP_VIDEO_BLANKY_VAL 0x1bb2 /* register.h:8129 */
#define P_ENCP_VIDEO_BLANKY_VAL VCBUS_REG_ADDR(ENCP_VIDEO_BLANKY_VAL)
#define ENCP_VIDEO_BLANKPB_VAL 0x1bb3 /* register.h:8130 */
#define P_ENCP_VIDEO_BLANKPB_VAL VCBUS_REG_ADDR(ENCP_VIDEO_BLANKPB_VAL)
#define ENCP_VIDEO_BLANKPR_VAL 0x1bb4 /* register.h:8131 */
#define P_ENCP_VIDEO_BLANKPR_VAL VCBUS_REG_ADDR(ENCP_VIDEO_BLANKPR_VAL)
#define ENCP_VIDEO_HOFFST 0x1bb5 /* register.h:8132 */
#define P_ENCP_VIDEO_HOFFST VCBUS_REG_ADDR(ENCP_VIDEO_HOFFST)
#define ENCP_VIDEO_VOFFST 0x1bb6 /* register.h:8133 */
#define P_ENCP_VIDEO_VOFFST VCBUS_REG_ADDR(ENCP_VIDEO_VOFFST)
#define ENCP_VIDEO_RGB_CTRL 0x1bb7 /* register.h:8134 */
#define P_ENCP_VIDEO_RGB_CTRL VCBUS_REG_ADDR(ENCP_VIDEO_RGB_CTRL)
#define ENCP_VIDEO_FILT_CTRL 0x1bb8 /* register.h:8135 */
#define P_ENCP_VIDEO_FILT_CTRL VCBUS_REG_ADDR(ENCP_VIDEO_FILT_CTRL)
#define ENCP_VIDEO_OFLD_VPEQ_OFST 0x1bb9 /* register.h:8136 */
#define P_ENCP_VIDEO_OFLD_VPEQ_OFST VCBUS_REG_ADDR(ENCP_VIDEO_OFLD_VPEQ_OFST)
#define ENCP_VIDEO_OFLD_VOAV_OFST 0x1bba /* register.h:8137 */
#define P_ENCP_VIDEO_OFLD_VOAV_OFST VCBUS_REG_ADDR(ENCP_VIDEO_OFLD_VOAV_OFST)
#define ENCP_VIDEO_MATRIX_CB 0x1bbb /* register.h:8138 */
#define P_ENCP_VIDEO_MATRIX_CB VCBUS_REG_ADDR(ENCP_VIDEO_MATRIX_CB)
#define ENCP_VIDEO_MATRIX_CR 0x1bbc /* register.h:8139 */
#define P_ENCP_VIDEO_MATRIX_CR VCBUS_REG_ADDR(ENCP_VIDEO_MATRIX_CR)
#define ENCP_VIDEO_RGBIN_CTRL 0x1bbd /* register.h:8140 */
#define P_ENCP_VIDEO_RGBIN_CTRL VCBUS_REG_ADDR(ENCP_VIDEO_RGBIN_CTRL)
#define ENCP_MACV_BLANKY_VAL 0x1bc0 /* register.h:8142 */
#define P_ENCP_MACV_BLANKY_VAL VCBUS_REG_ADDR(ENCP_MACV_BLANKY_VAL)
#define ENCP_MACV_MAXY_VAL 0x1bc1 /* register.h:8143 */
#define P_ENCP_MACV_MAXY_VAL VCBUS_REG_ADDR(ENCP_MACV_MAXY_VAL)
#define ENCP_MACV_1ST_PSSYNC_STRT 0x1bc2 /* register.h:8144 */
#define P_ENCP_MACV_1ST_PSSYNC_STRT VCBUS_REG_ADDR(ENCP_MACV_1ST_PSSYNC_STRT)
#define ENCP_MACV_PSSYNC_STRT 0x1bc3 /* register.h:8145 */
#define P_ENCP_MACV_PSSYNC_STRT VCBUS_REG_ADDR(ENCP_MACV_PSSYNC_STRT)
#define ENCP_MACV_AGC_STRT 0x1bc4 /* register.h:8146 */
#define P_ENCP_MACV_AGC_STRT VCBUS_REG_ADDR(ENCP_MACV_AGC_STRT)
#define ENCP_MACV_AGC_END 0x1bc5 /* register.h:8147 */
#define P_ENCP_MACV_AGC_END VCBUS_REG_ADDR(ENCP_MACV_AGC_END)
#define ENCP_MACV_WAVE_END 0x1bc6 /* register.h:8148 */
#define P_ENCP_MACV_WAVE_END VCBUS_REG_ADDR(ENCP_MACV_WAVE_END)
#define ENCP_MACV_STRTLINE 0x1bc7 /* register.h:8149 */
#define P_ENCP_MACV_STRTLINE VCBUS_REG_ADDR(ENCP_MACV_STRTLINE)
#define ENCP_MACV_ENDLINE 0x1bc8 /* register.h:8150 */
#define P_ENCP_MACV_ENDLINE VCBUS_REG_ADDR(ENCP_MACV_ENDLINE)
#define ENCP_MACV_TS_CNT_MAX_L 0x1bc9 /* register.h:8151 */
#define P_ENCP_MACV_TS_CNT_MAX_L VCBUS_REG_ADDR(ENCP_MACV_TS_CNT_MAX_L)
#define ENCP_MACV_TS_CNT_MAX_H 0x1bca /* register.h:8152 */
#define P_ENCP_MACV_TS_CNT_MAX_H VCBUS_REG_ADDR(ENCP_MACV_TS_CNT_MAX_H)
#define ENCP_MACV_TIME_DOWN 0x1bcb /* register.h:8153 */
#define P_ENCP_MACV_TIME_DOWN VCBUS_REG_ADDR(ENCP_MACV_TIME_DOWN)
#define ENCP_MACV_TIME_LO 0x1bcc /* register.h:8154 */
#define P_ENCP_MACV_TIME_LO VCBUS_REG_ADDR(ENCP_MACV_TIME_LO)
#define ENCP_MACV_TIME_UP 0x1bcd /* register.h:8155 */
#define P_ENCP_MACV_TIME_UP VCBUS_REG_ADDR(ENCP_MACV_TIME_UP)
#define ENCP_MACV_TIME_RST 0x1bce /* register.h:8156 */
#define P_ENCP_MACV_TIME_RST VCBUS_REG_ADDR(ENCP_MACV_TIME_RST)
#define ENCP_VBI_CTRL 0x1bd0 /* register.h:8158 */
#define P_ENCP_VBI_CTRL VCBUS_REG_ADDR(ENCP_VBI_CTRL)
#define ENCP_VBI_SETTING 0x1bd1 /* register.h:8159 */
#define P_ENCP_VBI_SETTING VCBUS_REG_ADDR(ENCP_VBI_SETTING)
#define ENCP_VBI_BEGIN 0x1bd2 /* register.h:8160 */
#define P_ENCP_VBI_BEGIN VCBUS_REG_ADDR(ENCP_VBI_BEGIN)
#define ENCP_VBI_WIDTH 0x1bd3 /* register.h:8161 */
#define P_ENCP_VBI_WIDTH VCBUS_REG_ADDR(ENCP_VBI_WIDTH)
#define ENCP_VBI_HVAL 0x1bd4 /* register.h:8162 */
#define P_ENCP_VBI_HVAL VCBUS_REG_ADDR(ENCP_VBI_HVAL)
#define ENCP_VBI_DATA0 0x1bd5 /* register.h:8163 */
#define P_ENCP_VBI_DATA0 VCBUS_REG_ADDR(ENCP_VBI_DATA0)
#define ENCP_VBI_DATA1 0x1bd6 /* register.h:8164 */
#define P_ENCP_VBI_DATA1 VCBUS_REG_ADDR(ENCP_VBI_DATA1)
#define ENCI_VIDEO_MODE 0x1b00 /* register.h:8185 */
#define P_ENCI_VIDEO_MODE VCBUS_REG_ADDR(ENCI_VIDEO_MODE)
#define ENCI_VIDEO_MODE_ADV 0x1b01 /* register.h:8186 */
#define P_ENCI_VIDEO_MODE_ADV VCBUS_REG_ADDR(ENCI_VIDEO_MODE_ADV)
#define ENCI_VIDEO_FSC_ADJ 0x1b02 /* register.h:8187 */
#define P_ENCI_VIDEO_FSC_ADJ VCBUS_REG_ADDR(ENCI_VIDEO_FSC_ADJ)
#define ENCI_VIDEO_BRIGHT 0x1b03 /* register.h:8188 */
#define P_ENCI_VIDEO_BRIGHT VCBUS_REG_ADDR(ENCI_VIDEO_BRIGHT)
#define ENCI_VIDEO_CONT 0x1b04 /* register.h:8189 */
#define P_ENCI_VIDEO_CONT VCBUS_REG_ADDR(ENCI_VIDEO_CONT)
#define ENCI_VIDEO_SAT 0x1b05 /* register.h:8190 */
#define P_ENCI_VIDEO_SAT VCBUS_REG_ADDR(ENCI_VIDEO_SAT)
#define ENCI_VIDEO_HUE 0x1b06 /* register.h:8191 */
#define P_ENCI_VIDEO_HUE VCBUS_REG_ADDR(ENCI_VIDEO_HUE)
#define ENCI_VIDEO_SCH 0x1b07 /* register.h:8192 */
#define P_ENCI_VIDEO_SCH VCBUS_REG_ADDR(ENCI_VIDEO_SCH)
#define ENCI_SYNC_MODE 0x1b08 /* register.h:8193 */
#define P_ENCI_SYNC_MODE VCBUS_REG_ADDR(ENCI_SYNC_MODE)
#define ENCI_SYNC_CTRL 0x1b09 /* register.h:8194 */
#define P_ENCI_SYNC_CTRL VCBUS_REG_ADDR(ENCI_SYNC_CTRL)
#define ENCI_SYNC_HSO_BEGIN 0x1b0a /* register.h:8195 */
#define P_ENCI_SYNC_HSO_BEGIN VCBUS_REG_ADDR(ENCI_SYNC_HSO_BEGIN)
#define ENCI_SYNC_HSO_END 0x1b0b /* register.h:8196 */
#define P_ENCI_SYNC_HSO_END VCBUS_REG_ADDR(ENCI_SYNC_HSO_END)
#define ENCI_SYNC_VSO_EVN 0x1b0c /* register.h:8197 */
#define P_ENCI_SYNC_VSO_EVN VCBUS_REG_ADDR(ENCI_SYNC_VSO_EVN)
#define ENCI_SYNC_VSO_ODD 0x1b0d /* register.h:8198 */
#define P_ENCI_SYNC_VSO_ODD VCBUS_REG_ADDR(ENCI_SYNC_VSO_ODD)
#define ENCI_SYNC_VSO_EVNLN 0x1b0e /* register.h:8199 */
#define P_ENCI_SYNC_VSO_EVNLN VCBUS_REG_ADDR(ENCI_SYNC_VSO_EVNLN)
#define ENCI_SYNC_VSO_ODDLN 0x1b0f /* register.h:8200 */
#define P_ENCI_SYNC_VSO_ODDLN VCBUS_REG_ADDR(ENCI_SYNC_VSO_ODDLN)
#define ENCI_SYNC_HOFFST 0x1b10 /* register.h:8201 */
#define P_ENCI_SYNC_HOFFST VCBUS_REG_ADDR(ENCI_SYNC_HOFFST)
#define ENCI_SYNC_VOFFST 0x1b11 /* register.h:8202 */
#define P_ENCI_SYNC_VOFFST VCBUS_REG_ADDR(ENCI_SYNC_VOFFST)
#define ENCI_SYNC_ADJ 0x1b12 /* register.h:8203 */
#define P_ENCI_SYNC_ADJ VCBUS_REG_ADDR(ENCI_SYNC_ADJ)
#define ENCI_RGB_SETTING 0x1b13 /* register.h:8204 */
#define P_ENCI_RGB_SETTING VCBUS_REG_ADDR(ENCI_RGB_SETTING)
#define ENCI_DE_H_BEGIN 0x1b16 /* register.h:8207 */
#define P_ENCI_DE_H_BEGIN VCBUS_REG_ADDR(ENCI_DE_H_BEGIN)
#define ENCI_DE_H_END 0x1b17 /* register.h:8208 */
#define P_ENCI_DE_H_END VCBUS_REG_ADDR(ENCI_DE_H_END)
#define ENCI_DE_V_BEGIN_EVEN 0x1b18 /* register.h:8209 */
#define P_ENCI_DE_V_BEGIN_EVEN VCBUS_REG_ADDR(ENCI_DE_V_BEGIN_EVEN)
#define ENCI_DE_V_END_EVEN 0x1b19 /* register.h:8210 */
#define P_ENCI_DE_V_END_EVEN VCBUS_REG_ADDR(ENCI_DE_V_END_EVEN)
#define ENCI_DE_V_BEGIN_ODD 0x1b1a /* register.h:8211 */
#define P_ENCI_DE_V_BEGIN_ODD VCBUS_REG_ADDR(ENCI_DE_V_BEGIN_ODD)
#define ENCI_DE_V_END_ODD 0x1b1b /* register.h:8212 */
#define P_ENCI_DE_V_END_ODD VCBUS_REG_ADDR(ENCI_DE_V_END_ODD)
#define ENCI_VBI_SETTING 0x1b20 /* register.h:8213 */
#define P_ENCI_VBI_SETTING VCBUS_REG_ADDR(ENCI_VBI_SETTING)
#define ENCI_VBI_CCDT_EVN 0x1b21 /* register.h:8214 */
#define P_ENCI_VBI_CCDT_EVN VCBUS_REG_ADDR(ENCI_VBI_CCDT_EVN)
#define ENCI_VBI_CCDT_ODD 0x1b22 /* register.h:8215 */
#define P_ENCI_VBI_CCDT_ODD VCBUS_REG_ADDR(ENCI_VBI_CCDT_ODD)
#define ENCI_VBI_CC525_LN 0x1b23 /* register.h:8216 */
#define P_ENCI_VBI_CC525_LN VCBUS_REG_ADDR(ENCI_VBI_CC525_LN)
#define ENCI_VBI_CC625_LN 0x1b24 /* register.h:8217 */
#define P_ENCI_VBI_CC625_LN VCBUS_REG_ADDR(ENCI_VBI_CC625_LN)
#define ENCI_VBI_WSSDT 0x1b25 /* register.h:8218 */
#define P_ENCI_VBI_WSSDT VCBUS_REG_ADDR(ENCI_VBI_WSSDT)
#define ENCI_VBI_WSS_LN 0x1b26 /* register.h:8219 */
#define P_ENCI_VBI_WSS_LN VCBUS_REG_ADDR(ENCI_VBI_WSS_LN)
#define ENCI_VBI_CGMSDT_L 0x1b27 /* register.h:8220 */
#define P_ENCI_VBI_CGMSDT_L VCBUS_REG_ADDR(ENCI_VBI_CGMSDT_L)
#define ENCI_VBI_CGMSDT_H 0x1b28 /* register.h:8221 */
#define P_ENCI_VBI_CGMSDT_H VCBUS_REG_ADDR(ENCI_VBI_CGMSDT_H)
#define ENCI_VBI_CGMS_LN 0x1b29 /* register.h:8222 */
#define P_ENCI_VBI_CGMS_LN VCBUS_REG_ADDR(ENCI_VBI_CGMS_LN)
#define ENCI_VBI_TTX_HTIME 0x1b2a /* register.h:8223 */
#define P_ENCI_VBI_TTX_HTIME VCBUS_REG_ADDR(ENCI_VBI_TTX_HTIME)
#define ENCI_VBI_TTX_LN 0x1b2b /* register.h:8224 */
#define P_ENCI_VBI_TTX_LN VCBUS_REG_ADDR(ENCI_VBI_TTX_LN)
#define ENCI_VBI_TTXDT0 0x1b2c /* register.h:8225 */
#define P_ENCI_VBI_TTXDT0 VCBUS_REG_ADDR(ENCI_VBI_TTXDT0)
#define ENCI_VBI_TTXDT1 0x1b2d /* register.h:8226 */
#define P_ENCI_VBI_TTXDT1 VCBUS_REG_ADDR(ENCI_VBI_TTXDT1)
#define ENCI_VBI_TTXDT2 0x1b2e /* register.h:8227 */
#define P_ENCI_VBI_TTXDT2 VCBUS_REG_ADDR(ENCI_VBI_TTXDT2)
#define ENCI_VBI_TTXDT3 0x1b2f /* register.h:8228 */
#define P_ENCI_VBI_TTXDT3 VCBUS_REG_ADDR(ENCI_VBI_TTXDT3)
#define ENCI_MACV_N0 0x1b30 /* register.h:8229 */
#define P_ENCI_MACV_N0 VCBUS_REG_ADDR(ENCI_MACV_N0)
#define ENCI_MACV_N1 0x1b31 /* register.h:8230 */
#define P_ENCI_MACV_N1 VCBUS_REG_ADDR(ENCI_MACV_N1)
#define ENCI_MACV_N2 0x1b32 /* register.h:8231 */
#define P_ENCI_MACV_N2 VCBUS_REG_ADDR(ENCI_MACV_N2)
#define ENCI_MACV_N3 0x1b33 /* register.h:8232 */
#define P_ENCI_MACV_N3 VCBUS_REG_ADDR(ENCI_MACV_N3)
#define ENCI_MACV_N4 0x1b34 /* register.h:8233 */
#define P_ENCI_MACV_N4 VCBUS_REG_ADDR(ENCI_MACV_N4)
#define ENCI_MACV_N5 0x1b35 /* register.h:8234 */
#define P_ENCI_MACV_N5 VCBUS_REG_ADDR(ENCI_MACV_N5)
#define ENCI_MACV_N6 0x1b36 /* register.h:8235 */
#define P_ENCI_MACV_N6 VCBUS_REG_ADDR(ENCI_MACV_N6)
#define ENCI_MACV_N7 0x1b37 /* register.h:8236 */
#define P_ENCI_MACV_N7 VCBUS_REG_ADDR(ENCI_MACV_N7)
#define ENCI_MACV_N8 0x1b38 /* register.h:8237 */
#define P_ENCI_MACV_N8 VCBUS_REG_ADDR(ENCI_MACV_N8)
#define ENCI_MACV_N9 0x1b39 /* register.h:8238 */
#define P_ENCI_MACV_N9 VCBUS_REG_ADDR(ENCI_MACV_N9)
#define ENCI_MACV_N10 0x1b3a /* register.h:8239 */
#define P_ENCI_MACV_N10 VCBUS_REG_ADDR(ENCI_MACV_N10)
#define ENCI_MACV_N11 0x1b3b /* register.h:8240 */
#define P_ENCI_MACV_N11 VCBUS_REG_ADDR(ENCI_MACV_N11)
#define ENCI_MACV_N12 0x1b3c /* register.h:8241 */
#define P_ENCI_MACV_N12 VCBUS_REG_ADDR(ENCI_MACV_N12)
#define ENCI_MACV_N13 0x1b3d /* register.h:8242 */
#define P_ENCI_MACV_N13 VCBUS_REG_ADDR(ENCI_MACV_N13)
#define ENCI_MACV_N14 0x1b3e /* register.h:8243 */
#define P_ENCI_MACV_N14 VCBUS_REG_ADDR(ENCI_MACV_N14)
#define ENCI_MACV_N15 0x1b3f /* register.h:8244 */
#define P_ENCI_MACV_N15 VCBUS_REG_ADDR(ENCI_MACV_N15)
#define ENCI_MACV_N16 0x1b40 /* register.h:8245 */
#define P_ENCI_MACV_N16 VCBUS_REG_ADDR(ENCI_MACV_N16)
#define ENCI_MACV_N17 0x1b41 /* register.h:8246 */
#define P_ENCI_MACV_N17 VCBUS_REG_ADDR(ENCI_MACV_N17)
#define ENCI_MACV_N18 0x1b42 /* register.h:8247 */
#define P_ENCI_MACV_N18 VCBUS_REG_ADDR(ENCI_MACV_N18)
#define ENCI_MACV_N19 0x1b43 /* register.h:8248 */
#define P_ENCI_MACV_N19 VCBUS_REG_ADDR(ENCI_MACV_N19)
#define ENCI_MACV_N20 0x1b44 /* register.h:8249 */
#define P_ENCI_MACV_N20 VCBUS_REG_ADDR(ENCI_MACV_N20)
#define ENCI_MACV_N21 0x1b45 /* register.h:8250 */
#define P_ENCI_MACV_N21 VCBUS_REG_ADDR(ENCI_MACV_N21)
#define ENCI_MACV_N22 0x1b46 /* register.h:8251 */
#define P_ENCI_MACV_N22 VCBUS_REG_ADDR(ENCI_MACV_N22)
#define ENCI_DBG_PX_RST 0x1b48 /* register.h:8253 */
#define P_ENCI_DBG_PX_RST VCBUS_REG_ADDR(ENCI_DBG_PX_RST)
#define ENCI_DBG_FLDLN_RST 0x1b49 /* register.h:8254 */
#define P_ENCI_DBG_FLDLN_RST VCBUS_REG_ADDR(ENCI_DBG_FLDLN_RST)
#define ENCI_DBG_PX_INT 0x1b4a /* register.h:8255 */
#define P_ENCI_DBG_PX_INT VCBUS_REG_ADDR(ENCI_DBG_PX_INT)
#define ENCI_DBG_FLDLN_INT 0x1b4b /* register.h:8256 */
#define P_ENCI_DBG_FLDLN_INT VCBUS_REG_ADDR(ENCI_DBG_FLDLN_INT)
#define ENCI_DBG_MAXPX 0x1b4c /* register.h:8257 */
#define P_ENCI_DBG_MAXPX VCBUS_REG_ADDR(ENCI_DBG_MAXPX)
#define ENCI_DBG_MAXLN 0x1b4d /* register.h:8258 */
#define P_ENCI_DBG_MAXLN VCBUS_REG_ADDR(ENCI_DBG_MAXLN)
#define ENCI_MACV_MAX_AMP 0x1b50 /* register.h:8259 */
#define P_ENCI_MACV_MAX_AMP VCBUS_REG_ADDR(ENCI_MACV_MAX_AMP)
#define ENCI_MACV_PULSE_LO 0x1b51 /* register.h:8260 */
#define P_ENCI_MACV_PULSE_LO VCBUS_REG_ADDR(ENCI_MACV_PULSE_LO)
#define ENCI_MACV_PULSE_HI 0x1b52 /* register.h:8261 */
#define P_ENCI_MACV_PULSE_HI VCBUS_REG_ADDR(ENCI_MACV_PULSE_HI)
#define ENCI_MACV_BKP_MAX 0x1b53 /* register.h:8262 */
#define P_ENCI_MACV_BKP_MAX VCBUS_REG_ADDR(ENCI_MACV_BKP_MAX)
#define ENCI_CFILT_CTRL 0x1b54 /* register.h:8263 */
#define P_ENCI_CFILT_CTRL VCBUS_REG_ADDR(ENCI_CFILT_CTRL)
#define ENCI_CFILT7 0x1b55 /* register.h:8264 */
#define P_ENCI_CFILT7 VCBUS_REG_ADDR(ENCI_CFILT7)
#define ENCI_YC_DELAY 0x1b56 /* register.h:8265 */
#define P_ENCI_YC_DELAY VCBUS_REG_ADDR(ENCI_YC_DELAY)
#define ENCI_VIDEO_EN 0x1b57 /* register.h:8266 */
#define P_ENCI_VIDEO_EN VCBUS_REG_ADDR(ENCI_VIDEO_EN)
#define VENC_VIDEO_PROG_MODE 0x1b68 /* /../ucode/register.h:8023 */
#define P_VENC_VIDEO_PROG_MODE VCBUS_REG_ADDR(VENC_VIDEO_PROG_MODE)
#define ENCI_DVI_HSO_BEGIN 0x1c00 /* register.h:8280 */
#define P_ENCI_DVI_HSO_BEGIN VCBUS_REG_ADDR(ENCI_DVI_HSO_BEGIN)
#define ENCI_DVI_HSO_END 0x1c01 /* register.h:8281 */
#define P_ENCI_DVI_HSO_END VCBUS_REG_ADDR(ENCI_DVI_HSO_END)
#define ENCI_DVI_VSO_BLINE_EVN 0x1c02 /* register.h:8282 */
#define P_ENCI_DVI_VSO_BLINE_EVN VCBUS_REG_ADDR(ENCI_DVI_VSO_BLINE_EVN)
#define ENCI_DVI_VSO_BLINE_ODD 0x1c03 /* register.h:8283 */
#define P_ENCI_DVI_VSO_BLINE_ODD VCBUS_REG_ADDR(ENCI_DVI_VSO_BLINE_ODD)
#define ENCI_DVI_VSO_ELINE_EVN 0x1c04 /* register.h:8284 */
#define P_ENCI_DVI_VSO_ELINE_EVN VCBUS_REG_ADDR(ENCI_DVI_VSO_ELINE_EVN)
#define ENCI_DVI_VSO_ELINE_ODD 0x1c05 /* register.h:8285 */
#define P_ENCI_DVI_VSO_ELINE_ODD VCBUS_REG_ADDR(ENCI_DVI_VSO_ELINE_ODD)
#define ENCI_DVI_VSO_BEGIN_EVN 0x1c06 /* register.h:8286 */
#define P_ENCI_DVI_VSO_BEGIN_EVN VCBUS_REG_ADDR(ENCI_DVI_VSO_BEGIN_EVN)
#define ENCI_DVI_VSO_BEGIN_ODD 0x1c07 /* register.h:8287 */
#define P_ENCI_DVI_VSO_BEGIN_ODD VCBUS_REG_ADDR(ENCI_DVI_VSO_BEGIN_ODD)
#define ENCI_DVI_VSO_END_EVN 0x1c08 /* register.h:8288 */
#define P_ENCI_DVI_VSO_END_EVN VCBUS_REG_ADDR(ENCI_DVI_VSO_END_EVN)
#define ENCI_DVI_VSO_END_ODD 0x1c09 /* register.h:8289 */
#define P_ENCI_DVI_VSO_END_ODD VCBUS_REG_ADDR(ENCI_DVI_VSO_END_ODD)
#define ENCI_CFILT_CTRL2 0x1c0a /* register.h:8295 */
#define P_ENCI_CFILT_CTRL2 VCBUS_REG_ADDR(ENCI_CFILT_CTRL2)
#define ENCI_DACSEL_0 0x1c0b /* register.h:8296 */
#define P_ENCI_DACSEL_0 VCBUS_REG_ADDR(ENCI_DACSEL_0)
#define ENCI_DACSEL_1 0x1c0c /* register.h:8297 */
#define P_ENCI_DACSEL_1 VCBUS_REG_ADDR(ENCI_DACSEL_1)
#define ENCP_DACSEL_0 0x1c0d /* register.h:8298 */
#define P_ENCP_DACSEL_0 VCBUS_REG_ADDR(ENCP_DACSEL_0)
#define ENCP_DACSEL_1 0x1c0e /* register.h:8299 */
#define P_ENCP_DACSEL_1 VCBUS_REG_ADDR(ENCP_DACSEL_1)
#define ENCP_MAX_LINE_SWITCH_POINT 0x1c0f /* register.h:8300 */
#define P_ENCP_MAX_LINE_SWITCH_POINT VCBUS_REG_ADDR(ENCP_MAX_LINE_SWITCH_POINT)
#define ENCI_TST_EN 0x1c10 /* register.h:8301 */
#define P_ENCI_TST_EN VCBUS_REG_ADDR(ENCI_TST_EN)
#define ENCI_TST_MDSEL 0x1c11 /* register.h:8302 */
#define P_ENCI_TST_MDSEL VCBUS_REG_ADDR(ENCI_TST_MDSEL)
#define ENCI_TST_Y 0x1c12 /* register.h:8303 */
#define P_ENCI_TST_Y VCBUS_REG_ADDR(ENCI_TST_Y)
#define ENCI_TST_CB 0x1c13 /* register.h:8304 */
#define P_ENCI_TST_CB VCBUS_REG_ADDR(ENCI_TST_CB)
#define ENCI_TST_CR 0x1c14 /* register.h:8305 */
#define P_ENCI_TST_CR VCBUS_REG_ADDR(ENCI_TST_CR)
#define ENCI_TST_CLRBAR_STRT 0x1c15 /* register.h:8306 */
#define P_ENCI_TST_CLRBAR_STRT VCBUS_REG_ADDR(ENCI_TST_CLRBAR_STRT)
#define ENCI_TST_CLRBAR_WIDTH 0x1c16 /* register.h:8307 */
#define P_ENCI_TST_CLRBAR_WIDTH VCBUS_REG_ADDR(ENCI_TST_CLRBAR_WIDTH)
#define ENCI_TST_VDCNT_STSET 0x1c17 /* register.h:8308 */
#define P_ENCI_TST_VDCNT_STSET VCBUS_REG_ADDR(ENCI_TST_VDCNT_STSET)
#define ENCI_VFIFO2VD_CTL 0x1c18 /* register.h:8313 */
#define P_ENCI_VFIFO2VD_CTL VCBUS_REG_ADDR(ENCI_VFIFO2VD_CTL)
#define ENCI_VFIFO2VD_PIXEL_START 0x1c19 /* register.h:8315 */
#define P_ENCI_VFIFO2VD_PIXEL_START \
VCBUS_REG_ADDR(ENCI_VFIFO2VD_PIXEL_START)
#define ENCI_VFIFO2VD_PIXEL_END 0x1c1a /* register.h:8317 */
#define P_ENCI_VFIFO2VD_PIXEL_END VCBUS_REG_ADDR(ENCI_VFIFO2VD_PIXEL_END)
#define ENCI_VFIFO2VD_LINE_TOP_START 0x1c1b /* register.h:8319 */
#define P_ENCI_VFIFO2VD_LINE_TOP_START \
VCBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_TOP_START)
#define ENCI_VFIFO2VD_LINE_TOP_END 0x1c1c /* register.h:8321 */
#define P_ENCI_VFIFO2VD_LINE_TOP_END \
VCBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_TOP_END)
#define ENCI_VFIFO2VD_LINE_BOT_START 0x1c1d /* register.h:8323 */
#define P_ENCI_VFIFO2VD_LINE_BOT_START \
VCBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_BOT_START)
#define ENCI_VFIFO2VD_LINE_BOT_END 0x1c1e /* register.h:8325 */
#define P_ENCI_VFIFO2VD_LINE_BOT_END \
VCBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_BOT_END)
#define ENCI_VFIFO2VD_CTL2 0x1c1f /* register.h:8326 */
#define P_ENCI_VFIFO2VD_CTL2 VCBUS_REG_ADDR(ENCI_VFIFO2VD_CTL2)
#define ENCP_DVI_HSO_BEGIN 0x1c30 /* register.h:8354 */
#define P_ENCP_DVI_HSO_BEGIN VCBUS_REG_ADDR(ENCP_DVI_HSO_BEGIN)
#define ENCP_DVI_HSO_END 0x1c31 /* register.h:8355 */
#define P_ENCP_DVI_HSO_END VCBUS_REG_ADDR(ENCP_DVI_HSO_END)
#define ENCP_DVI_VSO_BLINE_EVN 0x1c32 /* register.h:8356 */
#define P_ENCP_DVI_VSO_BLINE_EVN VCBUS_REG_ADDR(ENCP_DVI_VSO_BLINE_EVN)
#define ENCP_DVI_VSO_BLINE_ODD 0x1c33 /* register.h:8357 */
#define P_ENCP_DVI_VSO_BLINE_ODD VCBUS_REG_ADDR(ENCP_DVI_VSO_BLINE_ODD)
#define ENCP_DVI_VSO_ELINE_EVN 0x1c34 /* register.h:8358 */
#define P_ENCP_DVI_VSO_ELINE_EVN VCBUS_REG_ADDR(ENCP_DVI_VSO_ELINE_EVN)
#define ENCP_DVI_VSO_ELINE_ODD 0x1c35 /* register.h:8359 */
#define P_ENCP_DVI_VSO_ELINE_ODD VCBUS_REG_ADDR(ENCP_DVI_VSO_ELINE_ODD)
#define ENCP_DVI_VSO_BEGIN_EVN 0x1c36 /* register.h:8360 */
#define P_ENCP_DVI_VSO_BEGIN_EVN VCBUS_REG_ADDR(ENCP_DVI_VSO_BEGIN_EVN)
#define ENCP_DVI_VSO_BEGIN_ODD 0x1c37 /* register.h:8361 */
#define P_ENCP_DVI_VSO_BEGIN_ODD VCBUS_REG_ADDR(ENCP_DVI_VSO_BEGIN_ODD)
#define ENCP_DVI_VSO_END_EVN 0x1c38 /* register.h:8362 */
#define P_ENCP_DVI_VSO_END_EVN VCBUS_REG_ADDR(ENCP_DVI_VSO_END_EVN)
#define ENCP_DVI_VSO_END_ODD 0x1c39 /* register.h:8363 */
#define P_ENCP_DVI_VSO_END_ODD VCBUS_REG_ADDR(ENCP_DVI_VSO_END_ODD)
#define ENCP_DE_H_BEGIN 0x1c3a /* register.h:8364 */
#define P_ENCP_DE_H_BEGIN VCBUS_REG_ADDR(ENCP_DE_H_BEGIN)
#define ENCP_DE_H_END 0x1c3b /* register.h:8365 */
#define P_ENCP_DE_H_END VCBUS_REG_ADDR(ENCP_DE_H_END)
#define ENCP_DE_V_BEGIN_EVEN 0x1c3c /* register.h:8366 */
#define P_ENCP_DE_V_BEGIN_EVEN VCBUS_REG_ADDR(ENCP_DE_V_BEGIN_EVEN)
#define ENCP_DE_V_END_EVEN 0x1c3d /* register.h:8367 */
#define P_ENCP_DE_V_END_EVEN VCBUS_REG_ADDR(ENCP_DE_V_END_EVEN)
#define ENCP_DE_V_BEGIN_ODD 0x1c3e /* register.h:8368 */
#define P_ENCP_DE_V_BEGIN_ODD VCBUS_REG_ADDR(ENCP_DE_V_BEGIN_ODD)
#define ENCP_DE_V_END_ODD 0x1c3f /* register.h:8369 */
#define P_ENCP_DE_V_END_ODD VCBUS_REG_ADDR(ENCP_DE_V_END_ODD)
#define ENCI_SYNC_LINE_LENGTH 0x1c40 /* register.h:8372 */
#define P_ENCI_SYNC_LINE_LENGTH VCBUS_REG_ADDR(ENCI_SYNC_LINE_LENGTH)
#define ENCI_SYNC_PIXEL_EN 0x1c41 /* register.h:8375 */
#define P_ENCI_SYNC_PIXEL_EN VCBUS_REG_ADDR(ENCI_SYNC_PIXEL_EN)
#define ENCI_SYNC_TO_LINE_EN 0x1c42 /* register.h:8382 */
#define P_ENCI_SYNC_TO_LINE_EN VCBUS_REG_ADDR(ENCI_SYNC_TO_LINE_EN)
#define ENCI_SYNC_TO_PIXEL 0x1c43 /* register.h:8384 */
#define P_ENCI_SYNC_TO_PIXEL VCBUS_REG_ADDR(ENCI_SYNC_TO_PIXEL)
#define ENCP_SYNC_LINE_LENGTH 0x1c44 /* register.h:8387 */
#define P_ENCP_SYNC_LINE_LENGTH VCBUS_REG_ADDR(ENCP_SYNC_LINE_LENGTH)
#define ENCP_SYNC_PIXEL_EN 0x1c45 /* register.h:8390 */
#define P_ENCP_SYNC_PIXEL_EN VCBUS_REG_ADDR(ENCP_SYNC_PIXEL_EN)
#define ENCP_SYNC_TO_LINE_EN 0x1c46 /* register.h:8397 */
#define P_ENCP_SYNC_TO_LINE_EN VCBUS_REG_ADDR(ENCP_SYNC_TO_LINE_EN)
#define ENCP_SYNC_TO_PIXEL 0x1c47 /* register.h:8399 */
#define P_ENCP_SYNC_TO_PIXEL VCBUS_REG_ADDR(ENCP_SYNC_TO_PIXEL)
/* [3:2] cntl_viu2_sel_venc: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT. */
/* [1:0] cntl_viu1_sel_venc: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT. */
#define VPU_VIU_VENC_MUX_CTRL 0x271a /* register.h:9214 */
#define P_VPU_VIU_VENC_MUX_CTRL VCBUS_REG_ADDR(VPU_VIU_VENC_MUX_CTRL)
#define VPU_HDMI_SETTING 0x271b /* register.h:9229 */
#define P_VPU_HDMI_SETTING VCBUS_REG_ADDR(VPU_HDMI_SETTING)
#define VPU_HDMI_DATA_OVR 0x2727 /* register.h:9270 */
#define P_VPU_HDMI_DATA_OVR VCBUS_REG_ADDR(VPU_HDMI_DATA_OVR)
#define VPU_HDMI_FMT_CTRL 0x2743
#define P_VPU_HDMI_FMT_CTRL VCBUS_REG_ADDR(VPU_HDMI_FMT_CTRL)
/* For GXM and later */
#define VPU_HDMI_DITH_CNTL 0x27fc
#define P_VPU_HDMI_DITH_CNTL VCBUS_REG_ADDR(VPU_HDMI_DITH_CNTL)
/* c_always_on_pointer.h:71 */
#define AO_RTI_PULL_UP_REG ((0x00 << 10) | (0x0B << 2))
#define P_AO_RTI_PULL_UP_REG AOBUS_REG_ADDR(AO_RTI_PULL_UP_REG)
#define AO_RTI_PIN_MUX_REG ((0x00 << 10) | (0x05 << 2))
#define P_AO_RTI_PIN_MUX_REG AOBUS_REG_ADDR(AO_RTI_PIN_MUX_REG)
#define AO_RTI_PIN_MUX_REG2 ((0x00 << 10) | (0x06 << 2))
#define P_AO_RTI_PIN_MUX_REG2 AOBUS_REG_ADDR(AO_RTI_PIN_MUX_REG2)
#define AO_CRT_CLK_CNTL1 ((0x00 << 10) | (0x1A << 2))
#define P_AO_CRT_CLK_CNTL1 AOBUS_REG_ADDR(AO_CRT_CLK_CNTL1)
#define AO_DEBUG_REG0 ((0x00 << 10) | (0x28 << 2))
#define P_AO_DEBUG_REG0 AOBUS_REG_ADDR(AO_DEBUG_REG0)
#define AO_DEBUG_REG1 ((0x00 << 10) | (0x29 << 2))
#define P_AO_DEBUG_REG1 AOBUS_REG_ADDR(AO_DEBUG_REG1)
#define AO_DEBUG_REG2 ((0x00 << 10) | (0x2a << 2))
#define P_AO_DEBUG_REG2 AOBUS_REG_ADDR(AO_DEBUG_REG2)
#define AO_DEBUG_REG3 ((0x00 << 10) | (0x2b << 2))
#define P_AO_DEBUG_REG3 AOBUS_REG_ADDR(AO_DEBUG_REG3)
#define P_AO_RTI_GEN_PWR_SLEEP0 (0xc8100000 + (0x3a << 2))
#define P_HDMITX_ADDR_PORT_SEC 0xda83a000
#define P_HDMITX_DATA_PORT_SEC 0xda83a004
#define P_HDMITX_CTRL_PORT_SEC 0xda83a008
/* secure address P_HDMITX_ADDR_PORT 0xda83a000 */
#define P_HDMITX_ADDR_PORT 0xc883a000
#define P_HDMITX_DATA_PORT 0xc883a004
#define P_HDMITX_CTRL_PORT 0xc883a008
#define P_ELP_ESM_HPI_REG_BASE 0xd0044000
#endif

305
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/reg_ops.c Normal file
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/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/reg_ops.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/version.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/mm.h>
#include <linux/major.h>
#include <linux/platform_device.h>
#include <linux/mutex.h>
#include <linux/cdev.h>
#include <linux/io.h>
#include "mach_reg.h"
#include "hdmi_tx_reg.h"
static int dbg_en;
/*
* RePacket HDMI related registers rd/wr
*/
struct reg_map {
unsigned int phy_addr;
unsigned int size;
void __iomem *p;
int flag;
};
static struct reg_map reg_maps[] = {
{ /* CBUS */
.phy_addr = 0xc0800000,
.size = 0xa00000,
},
{ /* RESET */
.phy_addr = 0xc1104400,
.size = 0x100,
},
{ /* RTI */
.phy_addr = 0xc8100000,
.size = 0x100000,
},
{ /* PERIPHS */
.phy_addr = 0xc8834000,
.size = 0x2000,
},
{ /* HDMITX NON-SECURE*/
.phy_addr = 0xc883a000,
.size = 0x2000,
},
{ /* HIU */
.phy_addr = 0xc883c000,
.size = 0x2000,
},
{ /* VPU */
.phy_addr = 0xd0100000,
.size = 0x40000,
},
{ /* HDMITX SECURE */
.phy_addr = 0xda83a000,
.size = 0x2000,
},
};
static int in_reg_maps_idx(unsigned int addr)
{
int i;
for (i = 0; i < ARRAY_SIZE(reg_maps); i++) {
if ((addr >= reg_maps[i].phy_addr) &&
(addr < (reg_maps[i].phy_addr + reg_maps[i].size))) {
return i;
}
}
return -1;
}
static int check_map_flag(unsigned int addr)
{
int idx;
idx = in_reg_maps_idx(addr);
if ((idx != -1) && (reg_maps[idx].flag))
return 1;
return 0;
}
void init_reg_map(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(reg_maps); i++) {
reg_maps[i].p = ioremap(reg_maps[i].phy_addr, reg_maps[i].size);
if (!reg_maps[i].p) {
pr_info("hdmitx20: failed Mapped PHY: 0x%x\n",
reg_maps[i].phy_addr);
} else {
reg_maps[i].flag = 1;
pr_info("hdmitx20: Mapped PHY: 0x%x\n",
reg_maps[i].phy_addr);
}
}
}
unsigned int hd_read_reg(unsigned int addr)
{
int ret = 0;
int idx = in_reg_maps_idx(addr);
unsigned int val = 0;
unsigned int type = (addr >> OFFSET);
unsigned int reg = addr & ((1 << OFFSET) - 1);
if ((idx != -1) && check_map_flag(addr)) {
val = readl(reg_maps[idx].p + (addr - reg_maps[idx].phy_addr));
goto end;
}
ret = aml_reg_read(type, reg, &val);
if (ret < 0) {
pr_info("Rd[0x%x] Error\n", addr);
return val;
}
end:
if (dbg_en)
pr_info("Rd[0x%x] 0x%x\n", addr, val);
return val;
}
void hd_write_reg(unsigned int addr, unsigned int val)
{
int ret = 0;
int idx = in_reg_maps_idx(addr);
unsigned int type = (addr >> OFFSET);
unsigned int reg = addr & ((1 << OFFSET) - 1);
if ((idx != -1) && check_map_flag(addr)) {
writel(val, reg_maps[idx].p + (addr - reg_maps[idx].phy_addr));
goto end;
}
ret = aml_reg_write(type, reg, val);
if (ret < 0) {
pr_info("Wr[0x%x] 0x%x Error\n", addr, val);
return;
}
end:
if (dbg_en)
pr_info("Wr[0x%x] 0x%x\n", addr, val);
}
void hd_set_reg_bits(unsigned int addr, unsigned int value,
unsigned int offset, unsigned int len)
{
unsigned int data32 = 0;
data32 = hd_read_reg(addr);
data32 &= ~(((1 << len) - 1) << offset);
data32 |= (value & ((1 << len) - 1)) << offset;
hd_write_reg(addr, data32);
}
static DEFINE_SPINLOCK(reg_lock);
unsigned int hdmitx_rd_reg(unsigned int addr)
{
unsigned int data = 0;
unsigned long offset = (addr & DWC_OFFSET_MASK) >> 24;
unsigned long flags, fiq_flag;
if (addr & SEC_OFFSET) {
addr = addr & 0xffff;
sec_reg_write((unsigned int *)(unsigned long)
(P_HDMITX_ADDR_PORT_SEC + offset), addr);
sec_reg_write((unsigned int *)(unsigned long)
(P_HDMITX_ADDR_PORT_SEC + offset), addr);
data = sec_reg_read((unsigned int *)(unsigned long)
(P_HDMITX_DATA_PORT_SEC + offset));
} else {
addr = addr & 0xffff;
spin_lock_irqsave(&reg_lock, flags);
raw_local_save_flags(fiq_flag);
local_fiq_disable();
/*
* If addr is located at 0x5020 ~ 0x667e in DWC,
* then should operate twice
*/
hd_write_reg(P_HDMITX_ADDR_PORT + offset, addr);
hd_write_reg(P_HDMITX_ADDR_PORT + offset, addr);
data = hd_read_reg(P_HDMITX_DATA_PORT + offset);
data = hd_read_reg(P_HDMITX_DATA_PORT + offset);
raw_local_irq_restore(fiq_flag);
spin_unlock_irqrestore(&reg_lock, flags);
}
if (dbg_en)
pr_info("%s rd[0x%x] 0x%x\n", offset ? "DWC" : "TOP",
addr, data);
return data;
}
void hdmitx_wr_reg(unsigned int addr, unsigned int data)
{
unsigned long flags, fiq_flag;
unsigned long offset = (addr & DWC_OFFSET_MASK) >> 24;
if (addr & SEC_OFFSET) {
addr = addr & 0xffff;
sec_reg_write((unsigned int *)(unsigned long)
(P_HDMITX_ADDR_PORT_SEC + offset), addr);
sec_reg_write((unsigned int *)(unsigned long)
(P_HDMITX_ADDR_PORT_SEC + offset), addr);
sec_reg_write((unsigned int *)(unsigned long)
(P_HDMITX_DATA_PORT_SEC + offset), data);
} else {
addr = addr & 0xffff;
spin_lock_irqsave(&reg_lock, flags);
raw_local_save_flags(fiq_flag);
local_fiq_disable();
hd_write_reg(P_HDMITX_ADDR_PORT + offset, addr);
hd_write_reg(P_HDMITX_ADDR_PORT + offset, addr);
hd_write_reg(P_HDMITX_DATA_PORT + offset, data);
raw_local_irq_restore(fiq_flag);
spin_unlock_irqrestore(&reg_lock, flags);
}
if (dbg_en)
pr_info("%s wr[0x%x] 0x%x\n", offset ? "DWC" : "TOP",
addr, data);
}
void hdmitx_set_reg_bits(unsigned int addr, unsigned int value,
unsigned int offset, unsigned int len)
{
unsigned int data32 = 0;
data32 = hdmitx_rd_reg(addr);
data32 &= ~(((1 << len) - 1) << offset);
data32 |= (value & ((1 << len) - 1)) << offset;
hdmitx_wr_reg(addr, data32);
}
void hdmitx_poll_reg(unsigned int addr, unsigned int val, unsigned long timeout)
{
unsigned long time = 0;
time = jiffies;
while ((!(hdmitx_rd_reg(addr) & val)) &&
time_before(jiffies, time + timeout)) {
mdelay(2);
}
if (time_after(jiffies, time + timeout))
pr_info("hdmitx poll:0x%x val:0x%x T1=%lu t=%lu T2=%lu timeout\n",
addr, val, time, timeout, jiffies);
}
void hdmitx_rd_check_reg(unsigned int addr, unsigned int exp_data,
unsigned int mask)
{
unsigned long rd_data;
rd_data = hdmitx_rd_reg(addr);
if ((rd_data | mask) != (exp_data | mask)) {
pr_info("HDMITX-DWC addr=0x%04x rd_data=0x%02x\n",
(unsigned int)addr, (unsigned int)rd_data);
pr_info("Error: HDMITX-DWC exp_data=0x%02x mask=0x%02x\n",
(unsigned int)exp_data, (unsigned int)mask);
}
}
void hdcp22_wr_reg(uint32_t addr, uint32_t data)
{
sec_reg_write((unsigned int *)(unsigned long)
(P_ELP_ESM_HPI_REG_BASE + addr), data);
}
uint32_t hdcp22_rd_reg(uint32_t addr)
{
return (uint32_t)sec_reg_read((unsigned int *)(unsigned long)
(P_ELP_ESM_HPI_REG_BASE + addr));
}
MODULE_PARM_DESC(dbg_en, "\n debug_level\n");
module_param(dbg_en, int, 0664);

60
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/sec_ops.c Normal file
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/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/sec_ops.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/version.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/mm.h>
#include <linux/major.h>
#include <linux/mutex.h>
#include <linux/cdev.h>
#include "mach_reg.h"
#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
void sec_reg_write(unsigned int *addr, unsigned int value)
{
register long x0 asm("x0") = 0x82000019;
register long x1 asm("x1") = (unsigned long)addr;
register long x2 asm("x2") = value;
asm volatile(
__asmeq("%0", "x0")
__asmeq("%1", "x1")
__asmeq("%2", "x2")
"smc #0\n"
: : "r"(x0), "r"(x1), "r"(x2)
);
}
unsigned int sec_reg_read(unsigned int *addr)
{
register long x0 asm("x0") = 0x82000018;
register long x1 asm("x1") = (unsigned long)addr;
asm volatile(
__asmeq("%0", "x0")
__asmeq("%1", "x1")
"smc #0\n"
: "+r"(x0) : "r"(x1)
);
return (unsigned int)(x0&0xffffffff);
}

21
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/tvenc_conf.h Normal file
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/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/tvenc_conf.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_info_global.h>
void set_vmode_enc_hw(enum hdmi_vic vic);
void set_vmode_3dfp_enc_hw(enum hdmi_vic vic); /* For 3D Frame Packing */

50
include/linux/amlogic/media/vout/hdmi_tx/enc_clk_config.h Normal file
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@@ -0,0 +1,50 @@
/*
* include/linux/amlogic/media/vout/hdmi_tx/enc_clk_config.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __ENC_CLK_CONFIG_H__
#define __ENC_CLK_CONFIG_H__
enum Viu_Type {
VIU_ENCL = 0, VIU_ENCI, VIU_ENCP, VIU_ENCT,
};
extern int set_viu_path(unsigned int viu_channel_sel,
enum Viu_Type viu_type_sel);
extern void set_enci_clk(unsigned int clk);
extern void set_encp_clk(unsigned int clk);
/* extern void set_vmode_clk(vmode_t mode); */
struct enc_clk_val {
enum vmode_e mode;
unsigned int hpll_clk_out;
unsigned int hpll_hdmi_od;
unsigned int hpll_lvds_od;
unsigned int viu_path;
enum Viu_Type viu_type;
unsigned int vid_pll_div;
unsigned int clk_final_div;
unsigned int hdmi_tx_pixel_div;
unsigned int encp_div;
unsigned int enci_div;
unsigned int enct_div;
unsigned int encl_div;
unsigned int vdac0_div;
unsigned int vdac1_div;
unsigned int unused; /* prevent compile error */
};
#endif

578
include/linux/amlogic/media/vout/hdmi_tx/hdmi_common.h Normal file
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/*
* include/linux/amlogic/media/vout/hdmi_tx/hdmi_common.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __HDMI_COMMON_H__
#define __HDMI_COMMON_H__
#include <linux/amlogic/media/vout/vinfo.h>
/* HDMI VIC definitions */
/* HDMITX_VIC420_OFFSET and HDMITX_VIC_MASK are associated with
* VIC_MAX_VALID_MODE and VIC_MAX_NUM in hdmi_tx_module.h
*/
#define HDMITX_VIC420_OFFSET 0x100
#define HDMITX_VIC420_FAKE_OFFSET 0x200
#define HDMITX_VIC_MASK 0xff
enum hdmi_vic {
/* Refer to CEA 861-D */
HDMI_Unknown = 0,
HDMI_640x480p60_4x3 = 1,
HDMI_720x480p60_4x3 = 2,
HDMI_720x480p60_16x9 = 3,
HDMI_1280x720p60_16x9 = 4,
HDMI_1920x1080i60_16x9 = 5,
HDMI_720x480i60_4x3 = 6,
HDMI_720x480i60_16x9 = 7,
HDMI_720x240p60_4x3 = 8,
HDMI_720x240p60_16x9 = 9,
HDMI_2880x480i60_4x3 = 10,
HDMI_2880x480i60_16x9 = 11,
HDMI_2880x240p60_4x3 = 12,
HDMI_2880x240p60_16x9 = 13,
HDMI_1440x480p60_4x3 = 14,
HDMI_1440x480p60_16x9 = 15,
HDMI_1920x1080p60_16x9 = 16,
HDMI_720x576p50_4x3 = 17,
HDMI_720x576p50_16x9 = 18,
HDMI_1280x720p50_16x9 = 19,
HDMI_1920x1080i50_16x9 = 20,
HDMI_720x576i50_4x3 = 21,
HDMI_720x576i50_16x9 = 22,
HDMI_720x288p_4x3 = 23,
HDMI_720x288p_16x9 = 24,
HDMI_2880x576i50_4x3 = 25,
HDMI_2880x576i50_16x9 = 26,
HDMI_2880x288p50_4x3 = 27,
HDMI_2880x288p50_16x9 = 28,
HDMI_1440x576p_4x3 = 29,
HDMI_1440x576p_16x9 = 30,
HDMI_1920x1080p50_16x9 = 31,
HDMI_1920x1080p24_16x9 = 32,
HDMI_1920x1080p25_16x9 = 33,
HDMI_1920x1080p30_16x9 = 34,
HDMI_2880x480p60_4x3 = 35,
HDMI_2880x480p60_16x9 = 36,
HDMI_2880x576p50_4x3 = 37,
HDMI_2880x576p50_16x9 = 38,
HDMI_1920x1080i_t1250_50_16x9 = 39,
HDMI_1920x1080i100_16x9 = 40,
HDMI_1280x720p100_16x9 = 41,
HDMI_720x576p100_4x3 = 42,
HDMI_720x576p100_16x9 = 43,
HDMI_720x576i100_4x3 = 44,
HDMI_720x576i100_16x9 = 45,
HDMI_1920x1080i120_16x9 = 46,
HDMI_1280x720p120_16x9 = 47,
HDMI_720x480p120_4x3 = 48,
HDMI_720x480p120_16x9 = 49,
HDMI_720x480i120_4x3 = 50,
HDMI_720x480i120_16x9 = 51,
HDMI_720x576p200_4x3 = 52,
HDMI_720x576p200_16x9 = 53,
HDMI_720x576i200_4x3 = 54,
HDMI_720x576i200_16x9 = 55,
HDMI_720x480p240_4x3 = 56,
HDMI_720x480p240_16x9 = 57,
HDMI_720x480i240_4x3 = 58,
HDMI_720x480i240_16x9 = 59,
/* Refet to CEA 861-F */
HDMI_1280x720p24_16x9 = 60,
HDMI_1280x720p25_16x9 = 61,
HDMI_1280x720p30_16x9 = 62,
HDMI_1920x1080p120_16x9 = 63,
HDMI_1920x1080p100_16x9 = 64,
HDMI_1280x720p24_64x27 = 65,
HDMI_1280x720p25_64x27 = 66,
HDMI_1280x720p30_64x27 = 67,
HDMI_1280x720p50_64x27 = 68,
HDMI_1280x720p60_64x27 = 69,
HDMI_1280x720p100_64x27 = 70,
HDMI_1280x720p120_64x27 = 71,
HDMI_1920x1080p24_64x27 = 72,
HDMI_1920x1080p25_64x27 = 73,
HDMI_1920x1080p30_64x27 = 74,
HDMI_1920x1080p50_64x27 = 75,
HDMI_1920x1080p60_64x27 = 76,
HDMI_1920x1080p100_64x27 = 77,
HDMI_1920x1080p120_64x27 = 78,
HDMI_1680x720p24_64x27 = 79,
HDMI_1680x720p25_64x27 = 80,
HDMI_1680x720p30_64x27 = 81,
HDMI_1680x720p50_64x27 = 82,
HDMI_1680x720p60_64x27 = 83,
HDMI_1680x720p100_64x27 = 84,
HDMI_1680x720p120_64x27 = 85,
HDMI_2560x1080p24_64x27 = 86,
HDMI_2560x1080p25_64x27 = 87,
HDMI_2560x1080p30_64x27 = 88,
HDMI_2560x1080p50_64x27 = 89,
HDMI_2560x1080p60_64x27 = 90,
HDMI_2560x1080p100_64x27 = 91,
HDMI_2560x1080p120_64x27 = 92,
HDMI_3840x2160p24_16x9 = 93,
HDMI_3840x2160p25_16x9 = 94,
HDMI_3840x2160p30_16x9 = 95,
HDMI_3840x2160p50_16x9 = 96,
HDMI_3840x2160p60_16x9 = 97,
HDMI_4096x2160p24_256x135 = 98,
HDMI_4096x2160p25_256x135 = 99,
HDMI_4096x2160p30_256x135 = 100,
HDMI_4096x2160p50_256x135 = 101,
HDMI_4096x2160p60_256x135 = 102,
HDMI_3840x2160p24_64x27 = 103,
HDMI_3840x2160p25_64x27 = 104,
HDMI_3840x2160p30_64x27 = 105,
HDMI_3840x2160p50_64x27 = 106,
HDMI_3840x2160p60_64x27 = 107,
HDMI_RESERVED = 108,
HDMI_3840x1080p120hz = 109,
HDMI_3840x1080p100hz,
HDMI_3840x540p240hz,
HDMI_3840x540p200hz,
/*
* the following vic is for those y420 mode
* they are all beyond OFFSET_HDMITX_VIC420(0x1000)
* and they has same vic with normal vic in the lower bytes.
*/
HDMI_VIC_Y420 =
HDMITX_VIC420_OFFSET,
HDMI_3840x2160p50_16x9_Y420 =
HDMITX_VIC420_OFFSET + HDMI_3840x2160p50_16x9,
HDMI_3840x2160p60_16x9_Y420 =
HDMITX_VIC420_OFFSET + HDMI_3840x2160p60_16x9,
HDMI_4096x2160p50_256x135_Y420 =
HDMITX_VIC420_OFFSET + HDMI_4096x2160p50_256x135,
HDMI_4096x2160p60_256x135_Y420 =
HDMITX_VIC420_OFFSET + HDMI_4096x2160p60_256x135,
HDMI_3840x2160p50_64x27_Y420 =
HDMITX_VIC420_OFFSET + HDMI_3840x2160p50_64x27,
HDMI_3840x2160p60_64x27_Y420 =
HDMITX_VIC420_OFFSET + HDMI_3840x2160p60_64x27,
HDMI_VIC_Y420_MAX,
HDMI_VIC_FAKE = HDMITX_VIC420_FAKE_OFFSET,
HDMI_VIC_END,
};
/* Compliance with old definitions */
#define HDMI_640x480p60 HDMI_640x480p60_4x3
#define HDMI_480p60 HDMI_720x480p60_4x3
#define HDMI_480p60_16x9 HDMI_720x480p60_16x9
#define HDMI_720p60 HDMI_1280x720p60_16x9
#define HDMI_1080i60 HDMI_1920x1080i60_16x9
#define HDMI_480i60 HDMI_720x480i60_4x3
#define HDMI_480i60_16x9 HDMI_720x480i60_16x9
#define HDMI_480i60_16x9_rpt HDMI_2880x480i60_16x9
#define HDMI_1440x480p60 HDMI_1440x480p60_4x3
#define HDMI_1440x480p60_16x9 HDMI_1440x480p60_16x9
#define HDMI_1080p60 HDMI_1920x1080p60_16x9
#define HDMI_576p50 HDMI_720x576p50_4x3
#define HDMI_576p50_16x9 HDMI_720x576p50_16x9
#define HDMI_720p50 HDMI_1280x720p50_16x9
#define HDMI_1080i50 HDMI_1920x1080i50_16x9
#define HDMI_576i50 HDMI_720x576i50_4x3
#define HDMI_576i50_16x9 HDMI_720x576i50_16x9
#define HDMI_576i50_16x9_rpt HDMI_2880x576i50_16x9
#define HDMI_1080p50 HDMI_1920x1080p50_16x9
#define HDMI_1080p24 HDMI_1920x1080p24_16x9
#define HDMI_1080p25 HDMI_1920x1080p25_16x9
#define HDMI_1080p30 HDMI_1920x1080p30_16x9
#define HDMI_480p60_16x9_rpt HDMI_2880x480p60_16x9
#define HDMI_576p50_16x9_rpt HDMI_2880x576p50_16x9
#define HDMI_4k2k_24 HDMI_3840x2160p24_16x9
#define HDMI_4k2k_25 HDMI_3840x2160p25_16x9
#define HDMI_4k2k_30 HDMI_3840x2160p30_16x9
#define HDMI_4k2k_50 HDMI_3840x2160p50_16x9
#define HDMI_4k2k_60 HDMI_3840x2160p60_16x9
#define HDMI_4k2k_smpte_24 HDMI_4096x2160p24_256x135
#define HDMI_4k2k_smpte_50 HDMI_4096x2160p50_256x135
#define HDMI_4k2k_smpte_60 HDMI_4096x2160p60_256x135
/* for Y420 modes*/
#define HDMI_4k2k_50_y420 HDMI_3840x2160p50_16x9_Y420
#define HDMI_4k2k_60_y420 HDMI_3840x2160p60_16x9_Y420
#define HDMI_4k2k_smpte_50_y420 HDMI_4096x2160p50_256x135_Y420
#define HDMI_4k2k_smpte_60_y420 HDMI_4096x2160p60_256x135_Y420
enum hdmi_audio_fs;
struct dtd;
/* CEA TIMING STRUCT DEFINITION */
struct hdmi_cea_timing {
unsigned int pixel_freq; /* Unit: 1000 */
unsigned int frac_freq; /* 1.001 shift */
unsigned int h_freq; /* Unit: Hz */
unsigned int v_freq; /* Unit: 0.001 Hz */
unsigned int vsync_polarity:1;
unsigned int hsync_polarity:1;
unsigned short h_active;
unsigned short h_total;
unsigned short h_blank;
unsigned short h_front;
unsigned short h_sync;
unsigned short h_back;
unsigned short v_active;
unsigned short v_total;
unsigned short v_blank;
unsigned short v_front;
unsigned short v_sync;
unsigned short v_back;
unsigned short v_sync_ln;
};
enum hdmi_color_depth {
COLORDEPTH_24B = 4,
COLORDEPTH_30B = 5,
COLORDEPTH_36B = 6,
COLORDEPTH_48B = 7,
};
enum hdmi_color_space {
COLORSPACE_RGB444 = 0,
COLORSPACE_YUV422 = 1,
COLORSPACE_YUV444 = 2,
COLORSPACE_YUV420 = 3,
COLORSPACE_RESERVED,
};
enum hdmi_color_range {
COLORRANGE_LIM,
COLORRANGE_FUL,
};
enum hdmi_3d_type {
T3D_FRAME_PACKING = 0,
T3D_FIELD_ALTER = 1,
T3D_LINE_ALTER = 2,
T3D_SBS_FULL = 3,
T3D_L_DEPTH = 4,
T3D_L_DEPTH_GRAPHICS = 5,
T3D_TAB = 6, /* Top and Buttom */
T3D_RSVD = 7,
T3D_SBS_HALF = 8,
T3D_DISABLE,
};
/* get hdmi cea timing */
/* t: struct hdmi_cea_timing * */
#define GET_TIMING(name) (t->name)
struct hdmi_format_para {
enum hdmi_vic vic;
unsigned char *name;
unsigned char *sname;
char ext_name[32];
enum hdmi_color_depth cd; /* cd8, cd10 or cd12 */
enum hdmi_color_space cs; /* rgb, y444, y422, y420 */
enum hdmi_color_range cr; /* limit, full */
unsigned int pixel_repetition_factor;
unsigned int progress_mode:1;
unsigned int scrambler_en:1;
unsigned int tmds_clk_div40:1;
unsigned int tmds_clk; /* Unit: 1000 */
struct hdmi_cea_timing timing;
struct vinfo_s hdmitx_vinfo;
};
/* HDMI Packet Type Definitions */
#define PT_NULL_PKT 0x00
#define PT_AUD_CLK_REGENERATION 0x01
#define PT_AUD_SAMPLE 0x02
#define PT_GENERAL_CONTROL 0x03
#define PT_ACP 0x04
#define PT_ISRC1 0x05
#define PT_ISRC2 0x06
#define PT_ONE_BIT_AUD_SAMPLE 0x07
#define PT_DST_AUD 0x08
#define PT_HBR_AUD_STREAM 0x09
#define PT_GAMUT_METADATA 0x0A
#define PT_3D_AUD_SAMPLE 0x0B
#define PT_ONE_BIT_3D_AUD_SAMPLE 0x0C
#define PT_AUD_METADATA 0x0D
#define PT_MULTI_SREAM_AUD_SAMPLE 0x0E
#define PT_ONE_BIT_MULTI_SREAM_AUD_SAMPLE 0x0F
/* Infoframe Packet */
#define PT_IF_VENDOR_SEPCIFIC 0x81
#define PT_IF_AVI 0x82
#define PT_IF_SPD 0x83
#define PT_IF_AUD 0x84
#define PT_IF_MPEG_SOURCE 0x85
/* Old definitions */
#define TYPE_AVI_INFOFRAMES 0x82
#define AVI_INFOFRAMES_VERSION 0x02
#define AVI_INFOFRAMES_LENGTH 0x0D
struct hdmi_csc_coef_table {
unsigned char input_format;
unsigned char output_format;
unsigned char color_depth;
unsigned char color_format; /* 0 for ITU601, 1 for ITU709 */
unsigned char coef_length;
unsigned char *coef;
};
enum hdmi_audio_packet {
hdmi_audio_packet_SMP = 0x02,
hdmi_audio_packet_1BT = 0x07,
hdmi_audio_packet_DST = 0x08,
hdmi_audio_packet_HBR = 0x09,
};
enum hdmi_aspect_ratio {
ASPECT_RATIO_SAME_AS_SOURCE = 0x8,
TV_ASPECT_RATIO_4_3 = 0x9,
TV_ASPECT_RATIO_16_9 = 0xA,
TV_ASPECT_RATIO_14_9 = 0xB,
TV_ASPECT_RATIO_MAX
};
struct hdmi_format_para *hdmi_get_fmt_paras(enum hdmi_vic vic);
struct hdmi_format_para *hdmi_match_dtd_paras(struct dtd *t);
void check_detail_fmt(void);
unsigned int hdmi_get_csc_coef(
unsigned int input_format, unsigned int output_format,
unsigned int color_depth, unsigned int color_format,
unsigned char **coef_array, unsigned int *coef_length);
struct hdmi_format_para *hdmi_get_fmt_name(char const *name, char const *attr);
struct vinfo_s *hdmi_get_valid_vinfo(char *mode);
const char *hdmi_get_str_cd(struct hdmi_format_para *para);
const char *hdmi_get_str_cs(struct hdmi_format_para *para);
const char *hdmi_get_str_cr(struct hdmi_format_para *para);
unsigned int hdmi_get_aud_n_paras(enum hdmi_audio_fs fs,
enum hdmi_color_depth cd, unsigned int tmds_clk);
/* HDMI Audio Parmeters */
/* Refer to CEA-861-D Page 88 */
#define DTS_HD_TYPE_MASK 0xff00
#define DTS_HD_MA (0X1 << 8)
enum hdmi_audio_type {
CT_REFER_TO_STREAM = 0,
CT_PCM,
CT_AC_3, /* DD */
CT_MPEG1,
CT_MP3,
CT_MPEG2,
CT_AAC,
CT_DTS,
CT_ATRAC,
CT_ONE_BIT_AUDIO,
CT_DOLBY_D, /* DDP or DD+ */
CT_DTS_HD,
CT_MAT, /* TrueHD */
CT_DST,
CT_WMA,
CT_DTS_HD_MA = CT_DTS_HD + (DTS_HD_MA),
CT_MAX,
};
enum hdmi_audio_chnnum {
CC_REFER_TO_STREAM = 0,
CC_2CH,
CC_3CH,
CC_4CH,
CC_5CH,
CC_6CH,
CC_7CH,
CC_8CH,
CC_MAX_CH
};
enum hdmi_audio_format {
AF_SPDIF = 0, AF_I2S, AF_DSD, AF_HBR, AT_MAX
};
enum hdmi_audio_sampsize {
SS_REFER_TO_STREAM = 0, SS_16BITS, SS_20BITS, SS_24BITS, SS_MAX
};
struct size_map {
unsigned int sample_bits;
enum hdmi_audio_sampsize ss;
};
/* FL-- Front Left */
/* FC --Front Center */
/* FR --Front Right */
/* FLC-- Front Left Center */
/* FRC-- Front RiQhtCenter */
/* RL-- Rear Left */
/* RC --Rear Center */
/* RR-- Rear Right */
/* RLC-- Rear Left Center */
/* RRC --Rear RiQhtCenter */
/* LFE-- Low Frequency Effect */
enum hdmi_speak_location {
CA_FR_FL = 0,
CA_LFE_FR_FL,
CA_FC_FR_FL,
CA_FC_LFE_FR_FL,
CA_RC_FR_FL,
CA_RC_LFE_FR_FL,
CA_RC_FC_FR_FL,
CA_RC_FC_LFE_FR_FL,
CA_RR_RL_FR_FL,
CA_RR_RL_LFE_FR_FL,
CA_RR_RL_FC_FR_FL,
CA_RR_RL_FC_LFE_FR_FL,
CA_RC_RR_RL_FR_FL,
CA_RC_RR_RL_LFE_FR_FL,
CA_RC_RR_RL_FC_FR_FL,
CA_RC_RR_RL_FC_LFE_FR_FL,
CA_RRC_RC_RR_RL_FR_FL,
CA_RRC_RC_RR_RL_LFE_FR_FL,
CA_RRC_RC_RR_RL_FC_FR_FL,
CA_RRC_RC_RR_RL_FC_LFE_FR_FL,
CA_FRC_RLC_FR_FL,
CA_FRC_RLC_LFE_FR_FL,
CA_FRC_RLC_FC_FR_FL,
CA_FRC_RLC_FC_LFE_FR_FL,
CA_FRC_RLC_RC_FR_FL,
CA_FRC_RLC_RC_LFE_FR_FL,
CA_FRC_RLC_RC_FC_FR_FL,
CA_FRC_RLC_RC_FC_LFE_FR_FL,
CA_FRC_RLC_RR_RL_FR_FL,
CA_FRC_RLC_RR_RL_LFE_FR_FL,
CA_FRC_RLC_RR_RL_FC_FR_FL,
CA_FRC_RLC_RR_RL_FC_LFE_FR_FL,
};
enum hdmi_audio_downmix {
LSV_0DB = 0,
LSV_1DB,
LSV_2DB,
LSV_3DB,
LSV_4DB,
LSV_5DB,
LSV_6DB,
LSV_7DB,
LSV_8DB,
LSV_9DB,
LSV_10DB,
LSV_11DB,
LSV_12DB,
LSV_13DB,
LSV_14DB,
LSV_15DB,
};
enum hdmi_rx_audio_state {
STATE_AUDIO__MUTED = 0,
STATE_AUDIO__REQUEST_AUDIO = 1,
STATE_AUDIO__AUDIO_READY = 2,
STATE_AUDIO__ON = 3,
};
/* Sampling Freq Fs:
* 0 - Refer to Stream Header;
* 1 - 32KHz;
* 2 - 44.1KHz;
* 3 - 48KHz;
* 4 - 88.2KHz...
*/
enum hdmi_audio_fs {
FS_REFER_TO_STREAM = 0,
FS_32K = 1,
FS_44K1 = 2,
FS_48K = 3,
FS_88K2 = 4,
FS_96K = 5,
FS_176K4 = 6,
FS_192K = 7,
FS_768K = 8,
FS_MAX,
};
struct rate_map_fs {
unsigned int rate;
enum hdmi_audio_fs fs;
};
struct hdmi_rx_audioinfo {
/* !< Signal decoding type -- TvAudioType */
enum hdmi_audio_type type;
enum hdmi_audio_format format;
/* !< active audio channels bit mask. */
enum hdmi_audio_chnnum channels;
enum hdmi_audio_fs fs; /* !< Signal sample rate in Hz */
enum hdmi_audio_sampsize ss;
enum hdmi_speak_location speak_loc;
enum hdmi_audio_downmix lsv;
unsigned int N_value;
unsigned int CTS;
};
#define AUDIO_PARA_MAX_NUM 14
struct hdmi_audio_fs_ncts {
struct {
unsigned int tmds_clk;
unsigned int n; /* 24 or 30 bit */
unsigned int cts; /* 24 or 30 bit */
unsigned int n_36bit;
unsigned int cts_36bit;
unsigned int n_48bit;
unsigned int cts_48bit;
} array[AUDIO_PARA_MAX_NUM];
unsigned int def_n;
};
struct parse_cd {
enum hdmi_color_depth cd;
const char *name;
};
struct parse_cs {
enum hdmi_color_space cs;
const char *name;
};
struct parse_cr {
enum hdmi_color_range cr;
const char *name;
};
/* Refer CEA861-D Page 116 Table 55 */
struct dtd {
unsigned short pixel_clock;
unsigned short h_active;
unsigned short h_blank;
unsigned short v_active;
unsigned short v_blank;
unsigned short h_sync_offset;
unsigned short h_sync;
unsigned short v_sync_offset;
unsigned short v_sync;
unsigned char h_image_size;
unsigned char v_image_size;
unsigned char h_border;
unsigned char v_border;
unsigned char flags;
enum hdmi_vic vic;
};
#endif

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/*
* include/linux/amlogic/media/vout/hdmi_tx/hdmi_config.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __PLAT_MESON_HDMI_CONFIG_H
#define __PLAT_MESON_HDMI_CONFIG_H
struct hdmi_phy_set_data {
unsigned long freq;
unsigned long addr;
unsigned long data;
};
struct vendor_info_data {
unsigned char *vendor_name; /* Max Chars: 8 */
/* vendor_id, 3 Bytes, Refer to
* http://standards.ieee.org/develop/regauth/oui/oui.txt
*/
unsigned char *product_desc; /* Max Chars: 16 */
unsigned char *cec_osd_string; /* Max Chars: 14 */
unsigned int cec_config; /* 4 bytes: use to control cec switch on/off */
unsigned int vendor_id;
};
enum pwr_type {
NONE = 0, CPU_GPO = 1, PMU,
};
struct pwr_cpu_gpo {
unsigned int pin;
unsigned int val;
};
struct pwr_pmu {
unsigned int pin;
unsigned int val;
};
struct pwr_ctl_var {
enum pwr_type type;
union {
struct pwr_cpu_gpo gpo;
struct pwr_pmu pmu;
} var;
};
struct hdmi_pwr_ctl {
struct pwr_ctl_var pwr_5v_on;
struct pwr_ctl_var pwr_5v_off;
struct pwr_ctl_var pwr_3v3_on;
struct pwr_ctl_var pwr_3v3_off;
struct pwr_ctl_var pwr_hpll_vdd_on;
struct pwr_ctl_var pwr_hpll_vdd_off;
int pwr_level;
};
struct hdmi_config_platform_data {
void (*hdmi_sspll_ctrl)(unsigned int level); /* SSPLL control level */
/* For some boards, HDMI PHY setting may diff from ref board. */
struct hdmi_phy_set_data *phy_data;
struct vendor_info_data *vend_data;
struct hdmi_pwr_ctl *pwr_ctl;
};
#endif /* __PLAT_MESON_HDMI_CONFIG_H */

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/*
* include/linux/amlogic/media/vout/hdmi_tx/hdmi_info_global.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef _HDMI_INFO_GLOBAL_H
#define _HDMI_INFO_GLOBAL_H
#include "hdmi_common.h"
/* old definitions move to hdmi_common.h */
enum hdmi_rx_video_state {
STATE_VIDEO__POWERDOWN = 0,
STATE_VIDEO__MUTED = 1,
STATE_VIDEO__UNMUTE = 2,
STATE_VIDEO__ON = 3,
};
struct pixel_num {
short H; /* Number of horizontal pixels */
short V; /* Number of vertical pixels */
};
enum hdmi_pixel_repeat {
NO_REPEAT = 0,
HDMI_2_TIMES_REPEAT,
HDMI_3_TIMES_REPEAT,
HDMI_4_TIMES_REPEAT,
HDMI_5_TIMES_REPEAT,
HDMI_6_TIMES_REPEAT,
HDMI_7_TIMES_REPEAT,
HDMI_8_TIMES_REPEAT,
HDMI_9_TIMES_REPEAT,
HDMI_10_TIMES_REPEAT,
MAX_TIMES_REPEAT,
};
enum hdmi_scan {
SS_NO_DATA = 0,
/* where some active pixelsand lines at the edges are not displayed. */
SS_SCAN_OVER,
/* where all active pixels&lines are displayed,
* with or withouta border.
*/
SS_SCAN_UNDER,
SS_RSV
};
enum hdmi_barinfo {
B_UNVALID = 0, B_BAR_VERT, /* Vert. Bar Infovalid */
B_BAR_HORIZ, /* Horiz. Bar Infovalid */
B_BAR_VERT_HORIZ,
/* Vert.and Horiz. Bar Info valid */
};
enum hdmi_colorimetry {
CC_NO_DATA = 0, CC_ITU601, CC_ITU709, CC_XVYCC601, CC_XVYCC709,
};
enum hdmi_slacing {
SC_NO_UINFORM = 0,
/* Picture has been scaled horizontally */
SC_SCALE_HORIZ,
SC_SCALE_VERT, /* Picture has been scaled verticallv */
SC_SCALE_HORIZ_VERT,
/* Picture has been scaled horizontally & SC_SCALE_H_V */
};
struct hdmi_videoinfo {
enum hdmi_vic VIC;
enum hdmi_color_space color;
enum hdmi_color_depth color_depth;
enum hdmi_barinfo bar_info;
enum hdmi_pixel_repeat repeat_time;
enum hdmi_aspect_ratio aspect_ratio;
enum hdmi_colorimetry cc;
enum hdmi_scan ss;
enum hdmi_slacing sc;
};
/* -------------------HDMI VIDEO END---------------------------- */
/* -------------------HDMI AUDIO-------------------------------- */
#define TYPE_AUDIO_INFOFRAMES 0x84
#define AUDIO_INFOFRAMES_VERSION 0x01
#define AUDIO_INFOFRAMES_LENGTH 0x0A
#define HDMI_E_NONE 0x0
/* HPD Event & Status */
#define E_HPD_PULG_IN 0x1
#define E_HPD_PLUG_OUT 0x2
#define S_HPD_PLUG_IN 0x1
#define S_HPD_PLUG_OUT 0x0
#define E_HDCP_CHK_BKSV 0x1
/* -------------------HDMI AUDIO END---------------------- */
/* -------------------HDCP-------------------------------- */
/* HDCP keys from Efuse are encrypted by default, in this test HDCP keys
* are written by CPU with encryption manually added
*/
#define ENCRYPT_KEY 0xbe
enum hdcp_authstate {
HDCP_NO_AUTH = 0,
HDCP_NO_DEVICE_WITH_SLAVE_ADDR,
HDCP_BCAP_ERROR,
HDCP_BKSV_ERROR,
HDCP_R0S_ARE_MISSMATCH,
HDCP_RIS_ARE_MISSMATCH,
HDCP_REAUTHENTATION_REQ,
HDCP_REQ_AUTHENTICATION,
HDCP_NO_ACK_FROM_DEV,
HDCP_NO_RSEN,
HDCP_AUTHENTICATED,
HDCP_REPEATER_AUTH_REQ,
HDCP_REQ_SHA_CALC,
HDCP_REQ_SHA_HW_CALC,
HDCP_FAILED_ViERROR,
HDCP_MAX
};
/* -----------------------HDCP END---------------------------------------- */
/* -----------------------HDMI TX---------------------------------- */
enum hdmitx_disptype {
CABLE_UNPLUG = 0,
CABLE_PLUGIN_CHECK_EDID_I2C_ERROR,
CABLE_PLUGIN_CHECK_EDID_HEAD_ERROR,
CABLE_PLUGIN_CHECK_EDID_CHECKSUM_ERROR,
CABLE_PLUGIN_DVI_OUT,
CABLE_PLUGIN_HDMI_OUT,
CABLE_MAX
};
struct hdmitx_supstatus {
int hpd_state:1;
int support_480i:1;
int support_576i:1;
int support_480p:1;
int support_576p:1;
int support_720p_60hz:1;
int support_720p_50hz:1;
int support_1080i_60hz:1;
int support_1080i_50hz:1;
int support_1080p_60hz:1;
int support_1080p_50hz:1;
int support_1080p_24hz:1;
int support_1080p_25hz:1;
int support_1080p_30hz:1;
};
struct hdmitx_suplpcminfo {
int support_flag:1;
int max_channel_num:3;
int _192k:1;
int _176k:1;
int _96k:1;
int _88k:1;
int _48k:1;
int _44k:1;
int _32k:1;
int _24bit:1;
int _20bit:1;
int _16bit:1;
};
struct hdmitx_supcompressedinfo {
int support_flag:1;
int max_channel_num:3;
int _192k:1;
int _176k:1;
int _96k:1;
int _88k:1;
int _48k:1;
int _44k:1;
int _32k:1;
int _max_bit:10;
};
struct hdmitx_supspeakerformat {
int rlc_rrc:1;
int flc_frc:1;
int rc:1;
int rl_rr:1;
int fc:1;
int lfe:1;
int fl_fr:1;
};
struct hdmitx_vidpara {
unsigned int VIC;
enum hdmi_color_space color_prefer;
enum hdmi_color_space color;
enum hdmi_color_depth color_depth;
enum hdmi_barinfo bar_info;
enum hdmi_pixel_repeat repeat_time;
enum hdmi_aspect_ratio aspect_ratio;
enum hdmi_colorimetry cc;
enum hdmi_scan ss;
enum hdmi_slacing sc;
};
struct hdmitx_audpara {
enum hdmi_audio_type type;
enum hdmi_audio_chnnum channel_num;
enum hdmi_audio_fs sample_rate;
enum hdmi_audio_sampsize sample_size;
};
struct hdmitx_supaudinfo {
struct hdmitx_suplpcminfo _60958_PCM;
struct hdmitx_supcompressedinfo _AC3;
struct hdmitx_supcompressedinfo _MPEG1;
struct hdmitx_supcompressedinfo _MP3;
struct hdmitx_supcompressedinfo _MPEG2;
struct hdmitx_supcompressedinfo _AAC;
struct hdmitx_supcompressedinfo _DTS;
struct hdmitx_supcompressedinfo _ATRAC;
struct hdmitx_supcompressedinfo _One_Bit_Audio;
struct hdmitx_supcompressedinfo _Dolby;
struct hdmitx_supcompressedinfo _DTS_HD;
struct hdmitx_supcompressedinfo _MAT;
struct hdmitx_supcompressedinfo _DST;
struct hdmitx_supcompressedinfo _WMA;
struct hdmitx_supspeakerformat speaker_allocation;
};
/* ACR packet CTS parameters have 3 types: */
/* 1. HW auto calculated */
/* 2. Fixed values defined by Spec */
/* 3. Calculated by clock meter */
enum hdmitx_audcts {
AUD_CTS_AUTO = 0, AUD_CTS_FIXED, AUD_CTS_CALC,
};
struct dispmode_vic {
const char *disp_mode;
enum hdmi_vic VIC;
};
struct hdmitx_audinfo {
/* !< Signal decoding type -- TvAudioType */
enum hdmi_audio_type type;
enum hdmi_audio_format format;
/* !< active audio channels bit mask. */
enum hdmi_audio_chnnum channels;
enum hdmi_audio_fs fs; /* !< Signal sample rate in Hz */
enum hdmi_audio_sampsize ss;
};
/* -----------------Source Physical Address--------------- */
struct vsdb_phyaddr {
unsigned char a:4;
unsigned char b:4;
unsigned char c:4;
unsigned char d:4;
unsigned char valid;
};
struct hdmitx_clk {
enum hdmi_vic vic;
uint64_t clk_sys;
uint64_t clk_phy;
uint64_t clk_vid;
uint64_t clk_encp;
uint64_t clk_enci;
uint64_t clk_pixel;
};
#define Y420CMDB_MAX 32
struct hdmitx_info {
struct hdmi_rx_audioinfo audio_info;
struct hdmitx_supaudinfo tv_audio_info;
/* Hdmi_tx_video_info_t video_info; */
enum hdcp_authstate auth_state;
enum hdmitx_disptype output_state;
/* -----------------Source Physical Address--------------- */
struct vsdb_phyaddr vsdb_phy_addr;
/* ------------------------------------------------------- */
unsigned video_out_changing_flag:1;
unsigned support_underscan_flag:1;
unsigned support_ycbcr444_flag:1;
unsigned support_ycbcr422_flag:1;
unsigned tx_video_input_stable_flag:1;
unsigned auto_hdcp_ri_flag:1;
unsigned hw_sha_calculator_flag:1;
unsigned need_sup_cec:1;
/* ------------------------------------------------------- */
unsigned audio_out_changing_flag:1;
unsigned audio_flag:1;
unsigned support_basic_audio_flag:1;
unsigned audio_fifo_overflow:1;
unsigned audio_fifo_underflow:1;
unsigned audio_cts_status_err_flag:1;
unsigned support_ai_flag:1;
unsigned hdmi_sup_480i:1;
/* ------------------------------------------------------- */
unsigned hdmi_sup_576i:1;
unsigned hdmi_sup_480p:1;
unsigned hdmi_sup_576p:1;
unsigned hdmi_sup_720p_60hz:1;
unsigned hdmi_sup_720p_50hz:1;
unsigned hdmi_sup_1080i_60hz:1;
unsigned hdmi_sup_1080i_50hz:1;
unsigned hdmi_sup_1080p_60hz:1;
/* ------------------------------------------------------- */
unsigned hdmi_sup_1080p_50hz:1;
unsigned hdmi_sup_1080p_24hz:1;
unsigned hdmi_sup_1080p_25hz:1;
unsigned hdmi_sup_1080p_30hz:1;
/* ------------------------------------------------------- */
/* for total = 32*8 = 256 VICs */
/* for Y420CMDB bitmap */
unsigned char bitmap_valid;
unsigned char bitmap_length;
unsigned char y420_all_vic;
unsigned char y420cmdb_bitmap[Y420CMDB_MAX];
/* ------------------------------------------------------- */
};
#endif /* _HDMI_RX_GLOBAL_H */

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/*
* include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_cec_20.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef _TX_CEC_H_
#define _TX_CEC_H_
#include <linux/irq.h>
#include <linux/amlogic/cpu_version.h>
#include "hdmi_info_global.h"
#include "hdmi_tx_module.h"
#define CEC0_LOG_ADDR 4 /* MBX logical address */
#define TV_CEC_INTERVAL (HZ*3)
#define CEC_VERSION "v1.3"
#define _RX_DATA_BUF_SIZE_ 16
#define AO_CEC /* for switch between aocec and hdmi cec2.0 */
#define MAX_MSG 16
#define MAX_NUM_OF_DEV 16
enum _cec_log_dev_addr_e {
CEC_TV_ADDR = 0x00,
CEC_RECORDING_DEVICE_1_ADDR,
CEC_RECORDING_DEVICE_2_ADDR,
CEC_TUNER_1_ADDR,
CEC_PLAYBACK_DEVICE_1_ADDR,
CEC_AUDIO_SYSTEM_ADDR,
CEC_TUNER_2_ADDR,
CEC_TUNER_3_ADDR,
CEC_PLAYBACK_DEVICE_2_ADDR,
CEC_RECORDING_DEVICE_3_ADDR,
CEC_TUNER_4_ADDR,
CEC_PLAYBACK_DEVICE_3_ADDR,
CEC_RESERVED_1_ADDR,
CEC_RESERVED_2_ADDR,
CEC_FREE_USE_ADDR,
CEC_UNREGISTERED_ADDR
};
#define CEC_BROADCAST_ADDR CEC_UNREGISTERED_ADDR
#define CEC_TV (1 << CEC_TV_ADDR)
#define CEC_RECORDING_DEVICE_1 (1 << CEC_RECORDING_DEVICE_1_ADDR)
#define CEC_RECORDING_DEVICE_2 (1 << CEC_RECORDING_DEVICE_2_ADDR)
#define CEC_TUNER_1 (1 << CEC_TUNER_1_ADDR)
#define CEC_PLAYBACK_DEVICE_1 (1 << CEC_PLAYBACK_DEVICE_1_ADDR)
#define CEC_AUDIO_SYSTEM (1 << CEC_AUDIO_SYSTEM_ADDR)
#define CEC_TUNER_2 (1 << CEC_TUNER_2_ADDR)
#define CEC_TUNER_3 (1 << CEC_TUNER_3_ADDR)
#define CEC_PLAYBACK_DEVICE_2 (1 << CEC_PLAYBACK_DEVICE_2_ADDR)
#define CEC_RECORDING_DEVICE_3 (1 << CEC_RECORDING_DEVICE_3_ADDR)
#define CEC_TUNER_4 (1 << CEC_TUNER_4_ADDR)
#define CEC_PLAYBACK_DEVICE_3 (1 << CEC_PLAYBACK_DEVICE_3_ADDR)
#define CEC_RESERVED_1 (1 << CEC_RESERVED_1_ADDR)
#define CEC_RESERVED_2 (1 << CEC_RESERVED_2_ADDR)
#define CEC_FREE_USE (1 << CEC_FREE_USE_ADDR)
#define CEC_UNREGISTERED (1 << CEC_UNREGISTERED_ADDR)
#define CEC_DISPLAY_DEVICE (CEC_TV | CEC_FREE_USE)
#define CEC_RECORDING_DEVICE (CEC_RECORDING_DEVICE_1 \
| CEC_RECORDING_DEVICE_2 | CEC_RECORDING_DEVICE_3)
#define CEC_PLAYBACK_DEVICE (CEC_PLAYBACK_DEVICE_1 \
| CEC_PLAYBACK_DEVICE_2 | CEC_PLAYBACK_DEVICE_3)
#define CEC_TUNER_DEVICE (CEC_TUNER_1 | CEC_TUNER_2 \
| CEC_TUNER_3 | CEC_TUNER_4)
#define CEC_AUDIO_SYSTEM_DEVICE (CEC_AUDIO_SYSTEM)
#define CEC_IOC_MAGIC 'C'
#define CEC_IOC_GET_PHYSICAL_ADDR _IOR(CEC_IOC_MAGIC, 0x00, uint16_t)
#define CEC_IOC_GET_VERSION _IOR(CEC_IOC_MAGIC, 0x01, int)
#define CEC_IOC_GET_VENDOR_ID _IOR(CEC_IOC_MAGIC, 0x02, uint32_t)
#define CEC_IOC_GET_PORT_INFO _IOR(CEC_IOC_MAGIC, 0x03, int)
#define CEC_IOC_GET_PORT_NUM _IOR(CEC_IOC_MAGIC, 0x04, int)
#define CEC_IOC_GET_SEND_FAIL_REASON _IOR(CEC_IOC_MAGIC, 0x05, uint32_t)
#define CEC_IOC_SET_OPTION_WAKEUP _IOW(CEC_IOC_MAGIC, 0x06, uint32_t)
#define CEC_IOC_SET_OPTION_ENALBE_CEC _IOW(CEC_IOC_MAGIC, 0x07, uint32_t)
#define CEC_IOC_SET_OPTION_SYS_CTRL _IOW(CEC_IOC_MAGIC, 0x08, uint32_t)
#define CEC_IOC_SET_OPTION_SET_LANG _IOW(CEC_IOC_MAGIC, 0x09, uint32_t)
#define CEC_IOC_GET_CONNECT_STATUS _IOR(CEC_IOC_MAGIC, 0x0A, uint32_t)
#define CEC_IOC_ADD_LOGICAL_ADDR _IOW(CEC_IOC_MAGIC, 0x0B, uint32_t)
#define CEC_IOC_CLR_LOGICAL_ADDR _IOW(CEC_IOC_MAGIC, 0x0C, uint32_t)
#define CEC_IOC_SET_DEV_TYPE _IOW(CEC_IOC_MAGIC, 0x0D, uint32_t)
#define CEC_IOC_SET_ARC_ENABLE _IOW(CEC_IOC_MAGIC, 0x0E, uint32_t)
#define CEC_IOC_SET_AUTO_DEVICE_OFF _IOW(CEC_IOC_MAGIC, 0x0F, uint32_t)
#define CEC_FAIL_NONE 0
#define CEC_FAIL_NACK 1
#define CEC_FAIL_BUSY 2
#define CEC_FAIL_OTHER 3
enum hdmi_port_type {
HDMI_INPUT = 0,
HDMI_OUTPUT = 1
};
struct hdmi_port_info {
int type;
/* Port ID should start from 1 which corresponds to HDMI "port 1". */
int port_id;
int cec_supported;
int arc_supported;
uint16_t physical_address;
};
enum cec_dev_type_addr {
CEC_DISPLAY_DEVICE_TYPE = 0x0,
CEC_RECORDING_DEVICE_TYPE,
CEC_RESERVED_DEVICE_TYPE,
CEC_TUNER_DEVICE_TYPE,
CEC_PLAYBACK_DEVICE_TYPE,
CEC_AUDIO_SYSTEM_DEVICE_TYPE,
CEC_UNREGISTERED_DEVICE_TYPE,
};
enum cec_feature_abort_e {
CEC_UNRECONIZED_OPCODE = 0x0,
CEC_NOT_CORRECT_MODE_TO_RESPOND,
CEC_CANNOT_PROVIDE_SOURCE,
CEC_INVALID_OPERAND,
CEC_REFUSED,
CEC_UNABLE_TO_DETERMINE,
};
/*
* CEC OPCODES
*/
#define CEC_OC_ABORT_MESSAGE 0xFF
#define CEC_OC_ACTIVE_SOURCE 0x82
#define CEC_OC_CEC_VERSION 0x9E
#define CEC_OC_CLEAR_ANALOGUE_TIMER 0x33
#define CEC_OC_CLEAR_DIGITAL_TIMER 0x99
#define CEC_OC_CLEAR_EXTERNAL_TIMER 0xA1
#define CEC_OC_DECK_CONTROL 0x42
#define CEC_OC_DECK_STATUS 0x1B
#define CEC_OC_DEVICE_VENDOR_ID 0x87
#define CEC_OC_FEATURE_ABORT 0x00
#define CEC_OC_GET_CEC_VERSION 0x9F
#define CEC_OC_GET_MENU_LANGUAGE 0x91
#define CEC_OC_GIVE_AUDIO_STATUS 0x71
#define CEC_OC_GIVE_DECK_STATUS 0x1A
#define CEC_OC_GIVE_DEVICE_POWER_STATUS 0x8F
#define CEC_OC_GIVE_DEVICE_VENDOR_ID 0x8C
#define CEC_OC_GIVE_OSD_NAME 0x46
#define CEC_OC_GIVE_PHYSICAL_ADDRESS 0x83
#define CEC_OC_GIVE_SYSTEM_AUDIO_MODE_STATUS 0x7D
#define CEC_OC_GIVE_TUNER_DEVICE_STATUS 0x08
#define CEC_OC_IMAGE_VIEW_ON 0x04
#define CEC_OC_INACTIVE_SOURCE 0x9D
#define CEC_OC_MENU_REQUEST 0x8D
#define CEC_OC_MENU_STATUS 0x8E
#define CEC_OC_PLAY 0x41
#define CEC_OC_POLLING_MESSAGE 0xFC
#define CEC_OC_RECORD_OFF 0x0B
#define CEC_OC_RECORD_ON 0x09
#define CEC_OC_RECORD_STATUS 0x0A
#define CEC_OC_RECORD_TV_SCREEN 0x0F
#define CEC_OC_REPORT_AUDIO_STATUS 0x7A
#define CEC_OC_REPORT_PHYSICAL_ADDRESS 0x84
#define CEC_OC_REPORT_POWER_STATUS 0x90
#define CEC_OC_REQUEST_ACTIVE_SOURCE 0x85
#define CEC_OC_ROUTING_CHANGE 0x80
#define CEC_OC_ROUTING_INFORMATION 0x81
#define CEC_OC_SELECT_ANALOGUE_SERVICE 0x92
#define CEC_OC_SELECT_DIGITAL_SERVICE 0x93
#define CEC_OC_SET_ANALOGUE_TIMER 0x34
#define CEC_OC_SET_AUDIO_RATE 0x9A
#define CEC_OC_SET_DIGITAL_TIMER 0x97
#define CEC_OC_SET_EXTERNAL_TIMER 0xA2
#define CEC_OC_SET_MENU_LANGUAGE 0x32
#define CEC_OC_SET_OSD_NAME 0x47
#define CEC_OC_SET_OSD_STRING 0x64
#define CEC_OC_SET_STREAM_PATH 0x86
#define CEC_OC_SET_SYSTEM_AUDIO_MODE 0x72
#define CEC_OC_SET_TIMER_PROGRAM_TITLE 0x67
#define CEC_OC_STANDBY 0x36
#define CEC_OC_SYSTEM_AUDIO_MODE_REQUEST 0x70
#define CEC_OC_SYSTEM_AUDIO_MODE_STATUS 0x7E
#define CEC_OC_TEXT_VIEW_ON 0x0D
#define CEC_OC_TIMER_CLEARED_STATUS 0x43
#define CEC_OC_TIMER_STATUS 0x35
#define CEC_OC_TUNER_DEVICE_STATUS 0x07
#define CEC_OC_TUNER_STEP_DECREMENT 0x06
#define CEC_OC_TUNER_STEP_INCREMENT 0x05
#define CEC_OC_USER_CONTROL_PRESSED 0x44
#define CEC_OC_USER_CONTROL_RELEASED 0x45
#define CEC_OC_VENDOR_COMMAND 0x89
#define CEC_OC_VENDOR_COMMAND_WITH_ID 0xA0
#define CEC_OC_VENDOR_REMOTE_BUTTON_DOWN 0x8A
#define CEC_OC_VENDOR_REMOTE_BUTTON_UP 0x8B
/* cec global struct */
enum cec_node_status_e {
STATE_UNKNOWN = 0x00,
STATE_START,
STATE_STOP
};
enum cec_power_status_e {
POWER_ON = 0x00,
POWER_STANDBY,
TRANS_STANDBY_TO_ON,
TRANS_ON_TO_STANDBY,
};
enum status_req_mode_e {
STATUS_REQ_ON = 1,
STATUS_REQ_OFF,
STATUS_REQ_ONCE,
};
enum deck_info_e {
DECK_UNKNOWN_STATUS = 0,
DECK_PLAY = 0X11,
DECK_RECORD,
DECK_PLAY_REVERSE,
DECK_STILL,
DECK_SLOW,
DECK_SLOW_REVERSE,
DECK_FAST_FORWARD,
DECK_FAST_REVERSE,
DECK_NO_MEDIA,
DECK_STOP,
DECK_SKIP_FORWARD_WIND,
DECK_SKIP_REVERSE_REWIND,
DECK_INDEX_SEARCH_FORWARD,
DECK_INDEX_SEARCH_REVERSE,
DECK_OTHER_STATUS,
};
enum deck_cnt_mode_e {
DECK_CNT_SKIP_FORWARD_WIND = 1,
DECK_CNT_SKIP_REVERSE_REWIND,
DECK_CNT_STOP,
DECK_CNT_EJECT,
};
enum play_mode_e {
PLAY_FORWARD = 0X24,
PLAY_REVERSE = 0X20,
PLAY_STILL = 0X25,
FAST_FORWARD_MIN_SPEED = 0X05,
FAST_FORWARD_MEDIUM_SPEED = 0X06,
FAST_FORWARD_MAX_SPEED = 0X07,
FAST_REVERSE_MIN_SPEED = 0X09,
FAST_REVERSE_MEDIUM_SPEED = 0X0A,
FAST_REVERSE_MAX_SPEED = 0X0B,
SLOW_FORWARD_MIN_SPEED = 0X15,
SLOW_FORWARD_MEDIUM_SPEED = 0X16,
SLOW_FORWARD_MAX_SPEED = 0X17,
SLOW_REVERSE_MIN_SPEED = 0X19,
SLOW_REVERSE_MEDIUM_SPEED = 0X1A,
SLOW_REVERSE_MAX_SPEED = 0X1B,
};
enum cec_version_e {
CEC_VERSION_11 = 0,
CEC_VERSION_12,
CEC_VERSION_12A,
CEC_VERSION_13,
CEC_VERSION_13A,
CEC_VERSION_14A,
};
#define INFO_MASK_CEC_VERSION (1<<0)
#define INFO_MASK_VENDOR_ID (1<<1)
#define INFO_MASK_DEVICE_TYPE (1<<2)
#define INFO_MASK_POWER_STATUS (1<<3)
#define INFO_MASK_PHYSICAL_ADDRESS (1<<4)
#define INFO_MASK_LOGIC_ADDRESS (1<<5)
#define INFO_MASK_OSD_NAME (1<<6)
#define INFO_MASK_MENU_STATE (1<<7)
#define INFO_MASK_MENU_LANGUAGE (1<<8)
#define INFO_MASK_DECK_INfO (1<<9)
#define INFO_MASK_PLAY_MODE (1<<10)
/*CEC UI MASK*/
#define CEC_FUNC_MSAK 0
#define ONE_TOUCH_PLAY_MASK 1
#define ONE_TOUCH_STANDBY_MASK 2
#define AUTO_POWER_ON_MASK 3
struct cec_node_info_t {
};
/*
* only for 1 tx device
*/
struct cec_global_info_t {
dev_t dev_no;
unsigned int open_count;
unsigned int hal_ctl; /* message controlled by hal */
unsigned int vendor_id:24;
unsigned int menu_lang;
unsigned char cec_version;
unsigned char power_status;
unsigned char log_addr;
unsigned char menu_status;
unsigned char osd_name[16];
struct input_dev *remote_cec_dev; /* cec input device */
struct hdmitx_dev *hdmitx_device;
};
enum cec_device_menu_state_e {
DEVICE_MENU_ACTIVE = 0,
DEVICE_MENU_INACTIVE,
};
int cec_ll_tx(const unsigned char *msg, unsigned char len);
int cec_ll_rx(unsigned char *msg, unsigned char *len);
#endif

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include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_compliance.h Normal file
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/*
* include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_compliance.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __HDMI_TX_COMPLIANCE_H
#define __HDMI_TX_COMPLIANCE_H
#include "hdmi_info_global.h"
#include "hdmi_tx_module.h"
void hdmitx_special_handler_video(struct hdmitx_dev *hdmitx_device);
void hdmitx_special_handler_audio(struct hdmitx_dev *hdmitx_device);
#endif

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include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_ddc.h Normal file
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/*
* include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_ddc.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __HDMI_TX_DDC_H__
#define __HDMI_TX_DDC_H__
#include <linux/types.h>
#define EDID_SLAVE 0x50
#define EDIDSEG_ADR 0x30
#define HDCP_SLAVE 0x3a
#define SCDC_SLAVE 0x54
/* Little-Endian format */
enum scdc_addr {
SINK_VER = 0x01,
SOURCE_VER, /* RW */
UPDATE_0 = 0x10, /* RW */
UPDATE_1, /* RW */
TMDS_CFG = 0x20, /* RW */
SCRAMBLER_ST,
CONFIG_0 = 0x30, /* RW */
STATUS_FLAGS_0 = 0x40,
STATUS_FLAGS_1,
ERR_DET_0_L = 0x50,
ERR_DET_0_H,
ERR_DET_1_L,
ERR_DET_1_H,
ERR_DET_2_L,
ERR_DET_2_H,
ERR_DET_CHKSUM,
TEST_CONFIG_0 = 0xC0, /* RW */
MANUFACT_IEEE_OUI_2 = 0xD0,
MANUFACT_IEEE_OUI_1,
MANUFACT_IEEE_OUI_0,
DEVICE_ID = 0xD3, /* 0xD3 ~ 0xDD */
/* RW 0xDE ~ 0xFF */
MANUFACT_SPECIFIC = 0xDE,
};
enum hdcp_addr {
HDCP14_BKSV = 0x00,
HDCP14_RI_ = 0x08,
HDCP14_PJ_ = 0x0a,
HDCP14_AKSV = 0x10,
HDCP14_AINFO = 0x15,
HDCP14_AN = 0x18,
HDCP14_V_H0 = 0x20,
HDCP14_V_H1 = 0x24,
HDCP14_V_H2 = 0x28,
HDCP14_V_H3 = 0x2C,
HDCP14_V_H4 = 0x30,
HDCP14_BCAPS = 0x40,
HDCP14_BSTATUS = 0x41,
HDCP14_KSV_FIFO = 0x43,
HDCP2_VERSION = 0x50,
HDCP2_WR_MSG = 0x60,
HDCP2_RXSTATUS = 0x70,
HDCP2_RD_MSG = 0x80,
HDCP2_DBG = 0xC0,
};
/*
* HDMITX DDC HW related operations
*/
enum ddc_op {
DDC_INIT_DISABLE_PULL_UP_DN,
DDC_MUX_DDC,
DDC_UNMUX_DDC,
};
int hdmitx_ddc_hw_op(enum ddc_op cmd);
void scdc_rd_sink(uint8_t adr, uint8_t *val);
void scdc_wr_sink(uint8_t adr, uint8_t val);
uint32_t hdcp_rd_hdcp14_ver(void);
uint32_t hdcp_rd_hdcp22_ver(void);
void scdc_config(void *hdev);
#endif /* __HDMI_TX_SCDC_H__ */

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/*
* include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_ext.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __HDMI_TX_EXT_H__
#define __HDMI_TX_EXT_H__
void direct_hdcptx14_start(void);
void direct_hdcptx14_stop(void);
#endif

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/*
* include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef _HDMI_TX_MODULE_H
#define _HDMI_TX_MODULE_H
#include "hdmi_info_global.h"
#include "hdmi_config.h"
#include <linux/wait.h>
#include <linux/clk.h>
#include <linux/cdev.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
/* #include <linux/amlogic/aml_gpio_consumer.h> */
/*****************************
* hdmitx attr management
******************************/
/************************************
* hdmitx device structure
*************************************/
/* VIC_MAX_VALID_MODE and VIC_MAX_NUM are associated with
* HDMITX_VIC420_OFFSET and HDMITX_VIC_MASK in hdmi_common.h
*/
#define VIC_MAX_VALID_MODE 256 /* consider 4k2k */
/* half for valid vic, half for vic with y420*/
#define VIC_MAX_NUM 512
#define AUD_MAX_NUM 60
struct rx_audiocap {
unsigned char audio_format_code;
unsigned char channel_num_max;
unsigned char freq_cc;
unsigned char cc3;
};
enum hd_ctrl {
VID_EN, VID_DIS, AUD_EN, AUD_DIS, EDID_EN, EDID_DIS, HDCP_EN, HDCP_DIS,
};
struct rx_cap {
unsigned int native_Mode;
/*video*/
unsigned int VIC[VIC_MAX_NUM];
unsigned int VIC_count;
unsigned int native_VIC;
/*audio*/
struct rx_audiocap RxAudioCap[AUD_MAX_NUM];
unsigned char AUD_count;
unsigned char RxSpeakerAllocation;
/*vendor*/
unsigned int IEEEOUI;
unsigned int Max_TMDS_Clock1; /* HDMI1.4b TMDS_CLK */
unsigned int HF_IEEEOUI; /* For HDMI Forum */
unsigned int Max_TMDS_Clock2; /* HDMI2.0 TMDS_CLK */
/* CEA861-F, Table 56, Colorimetry Data Block */
unsigned int colorimetry_data;
unsigned int scdc_present:1;
unsigned int scdc_rr_capable:1; /* SCDC read request */
unsigned int lte_340mcsc_scramble:1;
unsigned int dc_y444:1;
unsigned int dc_30bit:1;
unsigned int dc_36bit:1;
unsigned int dc_48bit:1;
unsigned int dc_30bit_420:1;
unsigned int dc_36bit_420:1;
unsigned int dc_48bit_420:1;
unsigned int hdr_sup_eotf_sdr:1;
unsigned int hdr_sup_eotf_hdr:1;
unsigned int hdr_sup_eotf_smpte_st_2084:1;
unsigned int hdr_sup_eotf_future:1;
unsigned int hdr_sup_SMD_type1:1;
unsigned char hdr_lum_max;
unsigned char hdr_lum_avg;
unsigned char hdr_lum_min;
unsigned char ReceiverBrandName[4];
unsigned char ReceiverProductName[16];
unsigned char manufacture_week;
unsigned char manufacture_year;
unsigned char edid_version;
unsigned char edid_revision;
unsigned int ColorDeepSupport;
unsigned int Video_Latency;
unsigned int Audio_Latency;
unsigned int Interlaced_Video_Latency;
unsigned int Interlaced_Audio_Latency;
unsigned int threeD_present;
unsigned int threeD_Multi_present;
unsigned int hdmi_vic_LEN;
unsigned int HDMI_3D_LEN;
unsigned int threeD_Structure_ALL_15_0;
unsigned int threeD_MASK_15_0;
struct {
unsigned char frame_packing;
unsigned char top_and_bottom;
unsigned char side_by_side;
} support_3d_format[VIC_MAX_NUM];
struct dv_info dv_info;
enum hdmi_vic preferred_mode;
struct dtd dtd[16];
unsigned char dtd_idx;
unsigned char flag_vfpdb;
unsigned char number_of_dtd;
/*blk0 check sum*/
unsigned char blk0_chksum;
};
struct cts_conftab {
unsigned int fixed_n;
unsigned int tmds_clk;
unsigned int fixed_cts;
};
struct vic_attrmap {
enum hdmi_vic VIC;
unsigned int tmds_clk;
};
enum hdmi_event_t {
HDMI_TX_NONE = 0,
HDMI_TX_HPD_PLUGIN = 1,
HDMI_TX_HPD_PLUGOUT = 2,
HDMI_TX_INTERNAL_INTR = 4,
};
struct hdmi_phy_t {
unsigned long reg;
unsigned long val_sleep;
unsigned long val_save;
};
struct audcts_log {
unsigned int val:20;
unsigned int stable:1;
};
struct frac_rate_table {
char *hz;
u32 sync_num_int;
u32 sync_den_int;
u32 sync_num_dec;
u32 sync_den_dec;
};
#define EDID_MAX_BLOCK 4
#define HDMI_TMP_BUF_SIZE 1024
struct hdmitx_dev {
struct cdev cdev; /* The cdev structure */
struct proc_dir_entry *proc_file;
struct task_struct *task;
struct task_struct *task_monitor;
struct task_struct *task_hdcp;
struct task_struct *task_cec;
struct notifier_block nb;
struct workqueue_struct *hdmi_wq;
struct device *hdtx_dev;
struct delayed_work work_hpd_plugin;
struct delayed_work work_hpd_plugout;
struct work_struct work_internal_intr;
struct work_struct work_hdr;
struct timer_list hdcp_timer;
const char *hpd_pin;
const char *ddc_pin;
int hdcp_try_times;
/* -1, no hdcp; 0, NULL; 1, 1.4; 2, 2.2 */
int hdcp_mode;
int ready; /* 1, hdmi stable output, others are 0 */
int hdcp_hpd_stick; /* 1 not init & reset at plugout */
struct {
void (*SetPacket)(int type, unsigned char *DB,
unsigned char *HB);
void (*SetAudioInfoFrame)(unsigned char *AUD_DB,
unsigned char *CHAN_STAT_BUF);
int (*SetDispMode)(struct hdmitx_dev *hdmitx_device);
int (*SetAudMode)(struct hdmitx_dev *hdmitx_device,
struct hdmitx_audpara *audio_param);
void (*SetupIRQ)(struct hdmitx_dev *hdmitx_device);
void (*DebugFun)(struct hdmitx_dev *hdmitx_device,
const char *buf);
void (*UnInit)(struct hdmitx_dev *hdmitx_device);
int (*CntlPower)(struct hdmitx_dev *hdmitx_device,
unsigned int cmd, unsigned int arg); /* Power control */
/* edid/hdcp control */
int (*CntlDDC)(struct hdmitx_dev *hdmitx_device,
unsigned int cmd, unsigned long arg);
/* Audio/Video/System Status */
int (*GetState)(struct hdmitx_dev *hdmitx_device,
unsigned int cmd, unsigned int arg);
int (*CntlPacket)(struct hdmitx_dev *hdmitx_device,
unsigned int cmd,
unsigned int arg); /* Packet control */
int (*CntlConfig)(struct hdmitx_dev *hdmitx_device,
unsigned int cmd,
unsigned int arg); /* Configure control */
int (*CntlMisc)(struct hdmitx_dev *hdmitx_device,
unsigned int cmd, unsigned int arg); /* Other control */
int (*Cntl)(struct hdmitx_dev *hdmitx_device, unsigned int cmd,
unsigned int arg); /* Other control */
} HWOp;
struct {
unsigned int hdcp14_en;
unsigned int hdcp14_rslt;
} hdcpop;
struct hdmi_config_platform_data config_data;
enum hdmi_event_t hdmitx_event;
unsigned int irq_hpd;
unsigned int irq_cec;
/* wait_queue_head_t wait_queue;*/
/*EDID*/
unsigned int cur_edid_block;
unsigned int cur_phy_block_ptr;
unsigned char EDID_buf[EDID_MAX_BLOCK * 128];
unsigned char EDID_buf1[EDID_MAX_BLOCK*128]; /* for second read */
unsigned char *edid_ptr;
unsigned int edid_parsing; /* Indicator that RX edid data integrated */
unsigned char EDID_hash[20];
struct rx_cap RXCap;
struct hdmitx_vidpara *cur_video_param;
int vic_count;
/*audio*/
struct hdmitx_audpara cur_audio_param;
int audio_param_update_flag;
/*status*/
#define DISP_SWITCH_FORCE 0
#define DISP_SWITCH_EDID 1
unsigned char disp_switch_config; /* 0, force; 1,edid */
unsigned int cur_VIC;
unsigned char unplug_powerdown;
/**/
unsigned char hpd_event; /* 1, plugin; 2, plugout */
unsigned char hpd_state; /* 1, connect; 0, disconnect */
unsigned char force_audio_flag;
unsigned char mux_hpd_if_pin_high_flag;
unsigned char cec_func_flag;
int auth_process_timer;
struct hdmitx_info hdmi_info;
unsigned char tmp_buf[HDMI_TMP_BUF_SIZE];
unsigned int log;
unsigned int cec_func_config;
unsigned int cec_init_ready;
unsigned int tv_cec_support;
unsigned int tx_aud_cfg; /* 0, off; 1, on */
/* For some un-well-known TVs, no edid at all */
unsigned int tv_no_edid;
unsigned int hpd_lock;
struct hdmi_format_para *para;
/* 0: RGB444 1: Y444 2: Y422 3: Y420 */
/* 4: 24bit 5: 30bit 6: 36bit 7: 48bit */
/* if equals to 1, means current video & audio output are blank */
unsigned int output_blank_flag;
unsigned int audio_notify_flag;
unsigned int audio_step;
unsigned int frac_rate_policy;
/* configure for I2S: 8ch in, 2ch out */
/* 0: default setting 1:ch0/1 2:ch2/3 3:ch4/5 4:ch6/7 */
unsigned int aud_output_ch;
unsigned int hdr_src_feature;
unsigned int flag_3dfp:1;
unsigned int flag_3dtb:1;
unsigned int flag_3dss:1;
};
#define CMD_DDC_OFFSET (0x10 << 24)
#define CMD_STATUS_OFFSET (0x11 << 24)
#define CMD_PACKET_OFFSET (0x12 << 24)
#define CMD_MISC_OFFSET (0x13 << 24)
#define CMD_CONF_OFFSET (0x14 << 24)
#define CMD_STAT_OFFSET (0x15 << 24)
/***********************************************************************
* DDC CONTROL //CntlDDC
**********************************************************************/
#define DDC_RESET_EDID (CMD_DDC_OFFSET + 0x00)
#define DDC_RESET_HDCP (CMD_DDC_OFFSET + 0x01)
#define DDC_HDCP_OP (CMD_DDC_OFFSET + 0x02)
#define HDCP14_ON 0x1
#define HDCP14_OFF 0x2
#define HDCP22_ON 0x3
#define HDCP22_OFF 0x4
#define DDC_HDCP_BYP (CMD_DDC_OFFSET + 0x03)
#define DDC_IS_HDCP_ON (CMD_DDC_OFFSET + 0x04)
#define DDC_HDCP_GET_AKSV (CMD_DDC_OFFSET + 0x05)
#define DDC_HDCP_GET_BKSV (CMD_DDC_OFFSET + 0x06)
#define DDC_HDCP_GET_AUTH (CMD_DDC_OFFSET + 0x07)
#define DDC_PIN_MUX_OP (CMD_DDC_OFFSET + 0x08)
#define PIN_MUX 0x1
#define PIN_UNMUX 0x2
#define DDC_EDID_READ_DATA (CMD_DDC_OFFSET + 0x0a)
#define DDC_IS_EDID_DATA_READY (CMD_DDC_OFFSET + 0x0b)
#define DDC_EDID_GET_DATA (CMD_DDC_OFFSET + 0x0c)
#define DDC_EDID_CLEAR_RAM (CMD_DDC_OFFSET + 0x0d)
#define DDC_HDCP_MUX_INIT (CMD_DDC_OFFSET + 0x0e)
#define DDC_HDCP_14_LSTORE (CMD_DDC_OFFSET + 0x0f)
#define DDC_HDCP_22_LSTORE (CMD_DDC_OFFSET + 0x10)
#define DDC_SCDC_DIV40_SCRAMB (CMD_DDC_OFFSET + 0x20)
/***********************************************************************
* CONFIG CONTROL //CntlConfig
**********************************************************************/
/* Video part */
#define CONF_VIDEO_BLANK_OP (CMD_CONF_OFFSET + 0x00)
#define VIDEO_BLANK 0x1
#define VIDEO_UNBLANK 0x2
#define CONF_HDMI_DVI_MODE (CMD_CONF_OFFSET + 0x02)
#define HDMI_MODE 0x1
#define DVI_MODE 0x2
#define CONF_SYSTEM_ST (CMD_CONF_OFFSET + 0x03)
/* Audio part */
#define CONF_CLR_AVI_PACKET (CMD_CONF_OFFSET + 0x04)
#define CONF_CLR_VSDB_PACKET (CMD_CONF_OFFSET + 0x05)
#define CONF_VIDEO_MAPPING (CMD_CONF_OFFSET + 0x06)
#define CONF_GET_HDMI_DVI_MODE (CMD_CONF_OFFSET + 0x07)
#define CONF_AUDIO_MUTE_OP (CMD_CONF_OFFSET + 0x1000 + 0x00)
#define AUDIO_MUTE 0x1
#define AUDIO_UNMUTE 0x2
#define CONF_CLR_AUDINFO_PACKET (CMD_CONF_OFFSET + 0x1000 + 0x01)
#define CONF_AVI_BT2020 (CMD_CONF_OFFSET + 0X2000 + 0x00)
#define CLR_AVI_BT2020 0x0
#define SET_AVI_BT2020 0x1
/* set value as COLORSPACE_RGB444, YUV422, YUV444, YUV420 */
#define CONF_AVI_RGBYCC_INDIC (CMD_CONF_OFFSET + 0X2000 + 0x01)
#define CONF_AVI_Q01 (CMD_CONF_OFFSET + 0X2000 + 0x02)
#define RGB_RANGE_DEFAULT 0
#define RGB_RANGE_LIM 1
#define RGB_RANGE_FUL 2
#define RGB_RANGE_RSVD 3
#define CONF_AVI_YQ01 (CMD_CONF_OFFSET + 0X2000 + 0x03)
#define YCC_RANGE_LIM 0
#define YCC_RANGE_FUL 1
#define YCC_RANGE_RSVD 2
/***********************************************************************
* MISC control, hpd, hpll //CntlMisc
**********************************************************************/
#define MISC_HPD_MUX_OP (CMD_MISC_OFFSET + 0x00)
#define MISC_HPD_GPI_ST (CMD_MISC_OFFSET + 0x02)
#define MISC_HPLL_OP (CMD_MISC_OFFSET + 0x03)
#define HPLL_ENABLE 0x1
#define HPLL_DISABLE 0x2
#define HPLL_SET 0x3
#define MISC_TMDS_PHY_OP (CMD_MISC_OFFSET + 0x04)
#define TMDS_PHY_ENABLE 0x1
#define TMDS_PHY_DISABLE 0x2
#define MISC_VIID_IS_USING (CMD_MISC_OFFSET + 0x05)
#define MISC_TMDS_CLK_DIV40 (CMD_MISC_OFFSET + 0x07)
#define MISC_COMP_HPLL (CMD_MISC_OFFSET + 0x08)
#define COMP_HPLL_SET_OPTIMISE_HPLL1 0x1
#define COMP_HPLL_SET_OPTIMISE_HPLL2 0x2
#define MISC_COMP_AUDIO (CMD_MISC_OFFSET + 0x09)
#define COMP_AUDIO_SET_N_6144x2 0x1
#define COMP_AUDIO_SET_N_6144x3 0x2
#define MISC_AVMUTE_OP (CMD_MISC_OFFSET + 0x0a)
#define MISC_FINE_TUNE_HPLL (CMD_MISC_OFFSET + 0x0b)
#define OFF_AVMUTE 0x0
#define CLR_AVMUTE 0x1
#define SET_AVMUTE 0x2
#define MISC_HPLL_FAKE (CMD_MISC_OFFSET + 0x0c)
#define MISC_ESM_RESET (CMD_MISC_OFFSET + 0x0d)
#define MISC_HDCP_CLKDIS (CMD_MISC_OFFSET + 0x0e)
/***********************************************************************
* Get State //GetState
**********************************************************************/
#define STAT_VIDEO_VIC (CMD_STAT_OFFSET + 0x00)
#define STAT_VIDEO_CLK (CMD_STAT_OFFSET + 0x01)
#define STAT_AUDIO_FORMAT (CMD_STAT_OFFSET + 0x10)
#define STAT_AUDIO_CHANNEL (CMD_STAT_OFFSET + 0x11)
#define STAT_AUDIO_CLK_STABLE (CMD_STAT_OFFSET + 0x12)
#define STAT_AUDIO_PACK (CMD_STAT_OFFSET + 0x13)
/* HDMI LOG */
#define HDMI_LOG_HDCP (1 << 0)
#define HDMI_SOURCE_DESCRIPTION 0
#define HDMI_PACKET_VEND 1
#define HDMI_MPEG_SOURCE_INFO 2
#define HDMI_PACKET_AVI 3
#define HDMI_AUDIO_INFO 4
#define HDMI_AUDIO_CONTENT_PROTECTION 5
#define HDMI_PACKET_HBR 6
#define HDMI_PACKET_DRM 0x86
#define HDMI_PROCESS_DELAY msleep(10)
/* reduce a little time, previous setting is 4000/10 */
#define AUTH_PROCESS_TIME (1000/100)
#define HDMITX_VER "2014May6"
/***********************************************************************
* hdmitx protocol level interface
**********************************************************************/
extern void hdmitx_init_parameters(struct hdmitx_info *info);
extern enum hdmi_vic hdmitx_edid_vic_tab_map_vic(const char *disp_mode);
extern int hdmitx_edid_parse(struct hdmitx_dev *hdmitx_device);
extern int check_dvi_hdmi_edid_valid(unsigned char *buf);
enum hdmi_vic hdmitx_edid_get_VIC(struct hdmitx_dev *hdmitx_device,
const char *disp_mode, char force_flag);
extern int hdmitx_edid_VIC_support(enum hdmi_vic vic);
extern int hdmitx_edid_dump(struct hdmitx_dev *hdmitx_device, char *buffer,
int buffer_len);
bool hdmitx_edid_check_valid_mode(struct hdmitx_dev *hdev,
struct hdmi_format_para *para);
extern const char *hdmitx_edid_vic_to_string(enum hdmi_vic vic);
extern void hdmitx_edid_clear(struct hdmitx_dev *hdmitx_device);
extern void hdmitx_edid_ram_buffer_clear(struct hdmitx_dev *hdmitx_device);
extern void hdmitx_edid_buf_compare_print(struct hdmitx_dev *hdmitx_device);
extern const char *hdmitx_edid_get_native_VIC(struct hdmitx_dev *hdmitx_device);
/*
* HDMI Repeater TX I/F
* RX downstream Information from rptx to rprx
*/
/* send part raw edid from TX to RX */
extern void rx_repeat_hpd_state(unsigned int st);
/* prevent compile error in no HDMIRX case */
void __attribute__((weak))rx_repeat_hpd_state(unsigned int st)
{
}
extern void rx_edid_physical_addr(unsigned char a, unsigned char b,
unsigned char c, unsigned char d);
void __attribute__((weak))rx_edid_physical_addr(unsigned char a,
unsigned char b, unsigned char c, unsigned char d)
{
}
extern void rx_set_repeater_support(bool enable);
void __attribute__((weak))rx_set_repeater_support(bool enable)
{
}
extern void rx_set_receiver_edid(unsigned char *data, int len);
void __attribute__((weak))rx_set_receiver_edid(unsigned char *data, int len)
{
}
/*
* ver = 22 means downstream supports HDCP22
* ver = 14 means support HDCP14
* ver = 0 means support NO HDCP
*/
extern void rx_repeat_hdcp_ver(unsigned int ver);
void __attribute__((weak))rx_repeat_hdcp_ver(unsigned int ver)
{
}
extern void rx_set_receive_hdcp(unsigned char *data, int len, int depth,
bool max_cascade, bool max_devs);
void __attribute__((weak))rx_set_receive_hdcp(unsigned char *data, int len,
int depth, bool max_cascade, bool max_devs)
{
}
extern int hdmitx_set_display(struct hdmitx_dev *hdmitx_device,
enum hdmi_vic VideoCode);
extern int hdmi_set_3d(struct hdmitx_dev *hdmitx_device, int type,
unsigned int param);
extern int hdmitx_set_audio(struct hdmitx_dev *hdmitx_device,
struct hdmitx_audpara *audio_param, int hdmi_ch);
#ifdef CONFIG_AMLOGIC_HDMITX
extern struct hdmitx_dev *get_hdmitx_device(void);
#else
static inline struct hdmitx_dev *get_hdmitx_device(void)
{
return NULL;
}
#endif
extern int hdmi_print_buf(char *buf, int len);
extern void hdmi_set_audio_para(int para);
extern void hdmitx_output_rgb(void);
extern int get_cur_vout_index(void);
extern struct vinfo_s *hdmi_get_current_vinfo(void);
void phy_pll_off(void);
extern int get_hpd_state(void);
/***********************************************************************
* hdmitx hardware level interface
***********************************************************************/
/* #define DOUBLE_CLK_720P_1080I */
extern unsigned char hdmi_pll_mode; /* 1, use external clk as hdmi pll source */
extern void HDMITX_Meson_Init(struct hdmitx_dev *hdmitx_device);
extern unsigned char hdmi_audio_off_flag;
/*
* hdmitx_audio_mute_op() is used by external driver call
* flag: 0: audio off 1: audio_on
* 2: for EDID auto mode
*/
extern void hdmitx_audio_mute_op(unsigned int flag);
#define HDMITX_HWCMD_MUX_HPD_IF_PIN_HIGH 0x3
#define HDMITX_HWCMD_TURNOFF_HDMIHW 0x4
#define HDMITX_HWCMD_MUX_HPD 0x5
#define HDMITX_HWCMD_PLL_MODE 0x6
#define HDMITX_HWCMD_TURN_ON_PRBS 0x7
#define HDMITX_FORCE_480P_CLK 0x8
#define HDMITX_GET_AUTHENTICATE_STATE 0xa
#define HDMITX_SW_INTERNAL_HPD_TRIG 0xb
#define HDMITX_HWCMD_OSD_ENABLE 0xf
#define HDMITX_HDCP_MONITOR 0x11
#define HDMITX_IP_INTR_MASN_RST 0x12
#define HDMITX_EARLY_SUSPEND_RESUME_CNTL 0x14
#define HDMITX_EARLY_SUSPEND 0x1
#define HDMITX_LATE_RESUME 0x2
/* Refer to HDMI_OTHER_CTRL0 in hdmi_tx_reg.h */
#define HDMITX_IP_SW_RST 0x15
#define TX_CREG_SW_RST (1<<5)
#define TX_SYS_SW_RST (1<<4)
#define CEC_CREG_SW_RST (1<<3)
#define CEC_SYS_SW_RST (1<<2)
#define HDMITX_AVMUTE_CNTL 0x19
#define AVMUTE_SET 0 /* set AVMUTE to 1 */
#define AVMUTE_CLEAR 1 /* set AVunMUTE to 1 */
#define AVMUTE_OFF 2 /* set both AVMUTE and AVunMUTE to 0 */
#define HDMITX_CBUS_RST 0x1A
#define HDMITX_INTR_MASKN_CNTL 0x1B
#define INTR_MASKN_ENABLE 0
#define INTR_MASKN_DISABLE 1
#define INTR_CLEAR 2
#define HDMI_HDCP_DELAYTIME_AFTER_DISPLAY 20 /* unit: ms */
#define HDMITX_HDCP_MONITOR_BUF_SIZE 1024
struct Hdcp_Sub {
char *hdcp_sub_name;
unsigned int hdcp_sub_addr_start;
unsigned int hdcp_sub_len;
};
/***********************************************************************
* hdmi debug printk
* level: 0 ~ 4 Default is 2
* 0: ERRor 1: IMPortant 2: INFormative 3: DETtal 4: LOW
* hdmi_print(ERR, EDID "edid bad\");
* hdmi_print(IMP, AUD "set audio format: AC-3\n");
* hdmi_print(DET)
**********************************************************************/
#define HD "hdmitx: "
#define VID HD "video: "
#define AUD HD "audio: "
#define CEC HD "cec: "
#define EDID HD "edid: "
#define HDCP HD "hdcp: "
#define SYS HD "system: "
#define HPD HD "hpd: "
#define ERR 1
#define IMP 2
#define INF 3
#define LOW 4
#define DET (5, "%s[%d]", __func__, __LINE__)
extern void hdmi_print(int level, const char *fmt, ...);
#define dd()
#ifndef dd
#error delete debug information
#endif
#endif

54
include/linux/amlogic/media/vout/vinfo.h
View File

@@ -49,6 +49,56 @@ struct master_display_info_s {
u32 primaries[3][2]; /* normalized 50000 in G,B,R order */
u32 white_point[2]; /* normalized 50000 */
u32 luminance[2]; /* max/min lumin, normalized 10000 */
u32 max_content; /* Maximum Content Light Level */
u32 max_frame_average; /* Maximum Frame-average Light Level */
};
struct hdr_info {
u32 hdr_support; /* RX EDID hdr support types */
u32 lumi_max; /* RX EDID Lumi Max value */
u32 lumi_avg; /* RX EDID Lumi Avg value */
u32 lumi_min; /* RX EDID Lumi Min value */
};
enum eotf_type {
EOTF_T_NULL = 0,
EOTF_T_DOLBYVISION,
EOTF_T_HDR10,
EOTF_T_SDR,
EOTF_T_MAX,
};
struct dv_info {
uint32_t ieeeoui;
uint8_t ver; /* 0 or 1 */
uint8_t sup_yuv422_12bit:1; /* if as 0, then support RGB tunnel mode */
uint8_t sup_2160p60hz:1; /* if as 0, then support 2160p30hz */
uint8_t sup_global_dimming:1;
uint8_t colorimetry:1;
union {
struct {
uint16_t chrom_red_primary_x;
uint16_t chrom_red_primary_y;
uint16_t chrom_green_primary_x;
uint16_t chrom_green_primary_y;
uint16_t chrom_blue_primary_x;
uint16_t chrom_blue_primary_y;
uint16_t chrom_white_primary_x;
uint16_t chrom_white_primary_y;
uint16_t target_min_pq;
uint16_t target_max_pq;
uint8_t dm_major_ver;
uint8_t dm_minor_ver;
} ver0;
struct {
uint8_t dm_version;
uint8_t target_max_lum;
uint8_t target_min_lum;
uint8_t chrom_red_primary_x;
uint8_t chrom_red_primary_y;
uint8_t chrom_green_primary_x;
uint8_t chrom_green_primary_y;
uint8_t chrom_blue_primary_x;
uint8_t chrom_blue_primary_y;
} ver1;
} vers;
};
struct vinfo_s {
@@ -68,6 +118,10 @@ struct vinfo_s {
enum color_fmt_e viu_color_fmt;
enum viu_mux_e viu_mux;
struct master_display_info_s master_display_info;
struct hdr_info hdr_info;
const struct dv_info *dv_info;
void (*fresh_tx_hdr_pkt)(struct master_display_info_s *data);
void (*fresh_tx_vsif_pkt)(enum eotf_type type, uint8_t tunnel_mode);
void *vout_device;
};

2
include/linux/amlogic/media/vout/vout_notify.h
View File

@@ -1,7 +1,7 @@
/*
* include/linux/amlogic/media/vout/vout_notify.h
*
* Copyright (C) 2016 Amlogic, Inc. All rights reserved.
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by