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clk: rockchip: rk1808: Fixed incorrect parameter configuration

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fix up the 1G pll vco,
fix up the sdmmc gating bit.

Change-Id: I91ccc7a864e6fd1458e40965b8e5677887b8e055
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2019-05-09 11:20:17 +08:00
parent 91c4d7f635
commit abfc038343
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/rockchip/clk-rk1808.c
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@@ -45,7 +45,7 @@ static struct rockchip_pll_rate_table rk1808_pll_rates[] = {
RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
RK3036_PLL_RATE(1100000000, 2, 275, 3, 1, 1, 0),
RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
RK3036_PLL_RATE(1000000000, 1, 250, 6, 1, 1, 0),
RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0),
RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
@@ -645,7 +645,7 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = {
RK1808_CLKGATE_CON(9), 8, GFLAGS),
COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK1808_CLKSEL_CON(21), 15, 1, MFLAGS,
RK1808_CLKGATE_CON(9), 10, GFLAGS),
RK1808_CLKGATE_CON(9), 9, GFLAGS),
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK1808_SDMMC_CON0, 1),
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK1808_SDMMC_CON1, 1),