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media: rk-isp10: fix the issue that setting of isp0 mipi affect txrx dphy.

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Change-Id: I0c4a859caa42f1c5f9fd2ed51b2b8f92e84badd6
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
This commit is contained in:
Hu Kejun
2018-07-25 10:30:38 +08:00
committed by Tao Huang
parent 9828198d5f
commit ac3fe15f64
1 changed files with 15 additions and 4 deletions
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19
drivers/media/platform/rk-isp10/cif_isp10_rk3399.c
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@@ -292,11 +292,22 @@ static int mipi_dphy_cfg(struct cif_isp10_rk3399 *isp_cfg, struct pltfrm_cam_mip
datalane_en |= (1 << i);
if (input_sel == 0) {
/*
* According to the sequence of RK3399_TXRX_DPHY, the setting of isp0 mipi
* will affect txrx dphy in default state of grf_soc_con24.
*/
write_grf_reg(GRF_SOC_CON24_OFFSET,
DPHY_TX1RX1_MASTERSLAVEZ_MASK |
(0x0 << DPHY_TX1RX1_MASTERSLAVEZ_BIT) |
DPHY_TX1RX1_BASEDIR_MASK |
(0x1 << DPHY_TX1RX1_BASEDIR_BIT) |
DPHY_RX1_MASK | 0x0 << DPHY_RX1_SEL_BIT);
write_grf_reg(GRF_SOC_CON21_OFFSET,
DPHY_RX0_FORCERXMODE_MASK |
(0x0 << DPHY_RX0_FORCERXMODE_BIT) |
DPHY_RX0_FORCETXSTOPMODE_MASK |
(0x0 << DPHY_RX0_FORCETXSTOPMODE_BIT));
DPHY_RX0_FORCERXMODE_MASK |
(0x0 << DPHY_RX0_FORCERXMODE_BIT) |
DPHY_RX0_FORCETXSTOPMODE_MASK |
(0x0 << DPHY_RX0_FORCETXSTOPMODE_BIT));
/* set lane num */
write_grf_reg(GRF_SOC_CON21_OFFSET,