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arm64: dts: rockchip: rk3568: Add video codec relative node

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nodes: vdpu, jpeg_dec, vepu, rkvdec, rkvenc.

Change-Id: I4dce947d1bdee272618cc073ceebccb04d5f818a
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
This commit is contained in:
Ding Wei
2020-09-28 14:40:08 +08:00
parent bcb5409b23
commit ac51c391bc
1 changed files with 173 additions and 0 deletions
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173
arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -87,6 +87,13 @@
};
#endif
mpp_srv: mpp-srv {
compatible = "rockchip,mpp-service";
rockchip,taskqueue-count = <5>;
rockchip,resetgroup-count = <5>;
status = "disabled";
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -561,6 +568,172 @@
};
};
vdpu: vdpu@fdea0400 {
compatible = "rockchip,vpu-decoder-v2";
reg = <0x0 0xfdea0400 0x0 0x400>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk_vcodec", "hclk_vcodec";
resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>;
reset-names = "video_a", "video_h";
iommus = <&vdpu_mmu>;
power-domains = <&power RK3568_PD_VPU>;
rockchip,srv = <&mpp_srv>;
rockchip,taskqueue-node = <0>;
rockchip,resetgroup-node = <0>;
status = "disabled";
};
vdpu_mmu: iommu@fdea0800 {
compatible = "rockchip,iommu-v2";
reg = <0x0 0xfdea0800 0x0 0x40>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vdpu_mmu";
clock-names = "aclk", "iface";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
power-domains = <&power RK3568_PD_VPU>;
#iommu-cells = <0>;
status = "disabled";
};
jpegd: jpegd@fded0000 {
compatible = "rockchip,rkv-jpeg-decoder-v1";
reg = <0x0 0xfded0000 0x0 0x400>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
clock-names = "aclk_vcodec", "hclk_vcodec";
rockchip,normal-rates = <400000000>, <0>;
rockchip,advanced-rates = <500000000>, <0>;
rockchip,default-max-load = <2088960>;
resets = <&cru SRST_A_JDEC>, <&cru SRST_H_JDEC>;
reset-names = "video_a", "video_h";
iommus = <&jpegd_mmu>;
rockchip,srv = <&mpp_srv>;
rockchip,taskqueue-node = <1>;
rockchip,resetgroup-node = <1>;
power-domains = <&power RK3568_PD_RGA>;
status = "disabled";
};
jpegd_mmu: iommu@fded0480 {
compatible = "rockchip,iommu-v2";
reg = <0x0 0xfded0480 0x0 0x40>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "jpegd_mmu";
clock-names = "aclk", "iface";
clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
power-domains = <&power RK3568_PD_RGA>;
#iommu-cells = <0>;
status = "disabled";
};
vepu: vepu@fdee0000 {
compatible = "rockchip,vpu-encoder-v2";
reg = <0x0 0xfdee0000 0x0 0x400>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
clock-names = "aclk_vcodec", "hclk_vcodec";
rockchip,normal-rates = <400000000>, <0>;
rockchip,advanced-rates = <500000000>, <0>;
rockchip,default-max-load = <2088960>;
resets = <&cru SRST_A_JENC>, <&cru SRST_H_JENC>;
reset-names = "video_a", "video_h";
iommus = <&vepu_mmu>;
rockchip,srv = <&mpp_srv>;
rockchip,taskqueue-node = <2>;
rockchip,resetgroup-node = <2>;
power-domains = <&power RK3568_PD_RGA>;
status = "disabled";
};
vepu_mmu: iommu@fdee0800 {
compatible = "rockchip,iommu-v2";
reg = <0x0 0xfdee0800 0x0 0x40>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vepu_mmu";
clock-names = "aclk", "iface";
clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
power-domains = <&power RK3568_PD_RGA>;
#iommu-cells = <0>;
status = "disabled";
};
rkvenc: rkvenc@fdf40000 {
compatible = "rockchip,rkv-encoder-v1";
reg = <0x0 0xfdf40000 0x0 0x400>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_enc";
clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>,
<&cru CLK_RKVENC_CORE>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
rockchip,normal-rates = <300000000>, <0>, <400000000>;
rockchip,advanced-rates = <300000000>, <0>, <600000000>;
rockchip,default-max-load = <2088960>;
resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>,
<&cru SRST_RKVENC_CORE>;
reset-names = "video_a", "video_h", "video_core";
assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>;
assigned-clock-rates = <297000000>, <594000000>;
iommus = <&rkvenc_mmu>;
node-name = "rkvenc";
rockchip,srv = <&mpp_srv>;
rockchip,taskqueue-node = <3>;
rockchip,resetgroup-node = <3>;
power-domains = <&power RK3568_PD_RKVENC>;
status = "disabled";
};
rkvenc_mmu: iommu@fdf40f00 {
compatible = "rockchip,iommu-v2";
reg = <0x0 0xfdf40f00 0x0 0x40>, <0x0 0xfdf40f40 0x0 0x40>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1";
clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>;
clock-names = "aclk", "iface";
rockchip,disable-mmu-reset;
rockchip,enable-cmd-retry;
#iommu-cells = <0>;
power-domains = <&power RK3568_PD_RKVENC>;
status = "disabled";
};
rkvdec: rkvdec@fdf80200 {
compatible = "rockchip,rkv-decoder-v2";
reg = <0x0 0xfdf80200 0x0 0x400>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
<&cru CLK_RKVDEC_CA>, <&cru CLK_RKVDEC_CORE>,
<&cru CLK_RKVDEC_HEVC_CA>;
clock-names = "aclk_vcodec", "hclk_vcodec","clk_cabac",
"clk_core", "clk_hevc_cabac";
resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>,
<&cru SRST_RKVDEC_CA>, <&cru SRST_RKVDEC_CORE>,
<&cru SRST_RKVDEC_HEVC_CA>;
reset-names = "video_a", "video_h", "video_cabac",
"video_core", "video_hevc_cabac";
power-domains = <&power RK3568_PD_RKVDEC>;
iommus = <&rkvdec_mmu>;
rockchip,srv = <&mpp_srv>;
rockchip,taskqueue-node = <4>;
rockchip,resetgroup-node = <4>;
status = "disabled";
};
rkvdec_mmu: iommu@fdf80800 {
compatible = "rockchip,iommu-v2";
reg = <0x0 0xfdf80800 0x0 0x40>, <0x0 0xfdf80840 0x0 0x40>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "rkvdec_mmu";
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface";
power-domains = <&power RK3568_PD_RKVDEC>;
#iommu-cells = <0>;
status = "disabled";
};
gmac1: ethernet@fe010000 {
compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe010000 0x0 0x10000>;