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clk: rockchip: rk3568: Replace RKNN with NPU

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Update the TRM.

Change-Id: I0fb48df339d2a2350d0e6e2efc5128be0f90a97a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2020-10-12 10:34:20 +08:00
parent 0c17cc5fc3
commit ac723caa42
2 changed files with 6 additions and 6 deletions
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4
drivers/clk/rockchip/clk-rk3568.c
View File

@@ -575,9 +575,9 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
RK3568_CLKGATE_CON(3), 3, GFLAGS),
GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 0,
RK3568_CLKGATE_CON(3), 4, GFLAGS),
GATE(ACLK_RKNN, "aclk_rknn", "aclk_npu_pre", 0,
GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 0,
RK3568_CLKGATE_CON(3), 7, GFLAGS),
GATE(HCLK_RKNN, "hclk_rknn", "hclk_npu_pre", 0,
GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 0,
RK3568_CLKGATE_CON(3), 8, GFLAGS),
GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 0,

8
include/dt-bindings/clock/rk3568-cru.h
View File

@@ -97,8 +97,8 @@
#define HCLK_NPU_PRE 37
#define PCLK_NPU_PRE 38
#define ACLK_NPU_PRE 39
#define ACLK_RKNN 40
#define HCLK_RKNN 41
#define ACLK_NPU 40
#define HCLK_NPU 41
#define PCLK_NPU_PVTM 42
#define CLK_NPU_PVTM 43
#define CLK_NPU_PVTM_CORE 44
@@ -523,8 +523,8 @@
#define SRST_A_NPU_NIU 40
#define SRST_H_NPU_NIU 41
#define SRST_P_NPU_NIU 42
#define SRST_A_RKNN 43
#define SRST_H_RKNN 44
#define SRST_A_NPU 43
#define SRST_H_NPU 44
#define SRST_P_NPU_PVTM 45
#define SRST_NPU_PVTM 46
#define SRST_NPU_PVTPLL 47