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Merge tag 'drm-intel-fixes-2021-04-22' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes

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- GVT's BDW regression fix for cmd parser (Zhenyu)
- Fix modesetting in case of unexpected AUX timeouts (Imre)

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YIGZ3pQPgPQtZtyI@intel.com
This commit is contained in:
Dave Airlie
2021-04-23 12:16:12 +10:00
parent b4d1913df2 2d292995bb
commit aca38735ae
2 changed files with 15 additions and 7 deletions
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3
drivers/gpu/drm/i915/display/intel_dp_link_training.c
View File

@@ -848,7 +848,8 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp);
if (lttpr_count < 0)
return;
/* Still continue with enabling the port and link training. */
lttpr_count = 0;
if (!intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count))
intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);

19
drivers/gpu/drm/i915/gvt/cmd_parser.c
View File

@@ -916,19 +916,26 @@ static int cmd_reg_handler(struct parser_exec_state *s,
if (!strncmp(cmd, "srm", 3) ||
!strncmp(cmd, "lrm", 3)) {
if (offset != i915_mmio_reg_offset(GEN8_L3SQCREG4) &&
offset != 0x21f0) {
if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) ||
offset == 0x21f0 ||
(IS_BROADWELL(gvt->gt->i915) &&
offset == i915_mmio_reg_offset(INSTPM)))
return 0;
else {
gvt_vgpu_err("%s access to register (%x)\n",
cmd, offset);
return -EPERM;
} else
return 0;
}
}
if (!strncmp(cmd, "lrr-src", 7) ||
!strncmp(cmd, "lrr-dst", 7)) {
gvt_vgpu_err("not allowed cmd %s\n", cmd);
return -EPERM;
if (IS_BROADWELL(gvt->gt->i915) && offset == 0x215c)
return 0;
else {
gvt_vgpu_err("not allowed cmd %s reg (%x)\n", cmd, offset);
return -EPERM;
}
}
if (!strncmp(cmd, "pipe_ctrl", 9)) {