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https://github.com/hardkernel/linux.git
synced 2026-06-08 11:50:43 +09:00
ARM: rockchip: add iomap and soc id support
This commit is contained in:
黄涛
@@ -1,4 +1,5 @@
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obj-y += common.o
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obj-y += cpu.o
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obj-y += rk3188.o
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obj-$(CONFIG_SMP) += platsmp.o
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obj-$(CONFIG_FIQ_DEBUGGER) += rk_fiq_debugger.o
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81
arch/arm/mach-rockchip/cpu.c
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81
arch/arm/mach-rockchip/cpu.c
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@@ -0,0 +1,81 @@
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#include <linux/kernel.h>
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#include <linux/cpu.h>
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#include "cpu.h"
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unsigned long rockchip_soc_id;
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EXPORT_SYMBOL(rockchip_soc_id);
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static ssize_t type_show(struct device *dev, struct device_attribute *attr, char *buf)
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{
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const char *type;
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if (cpu_is_rk319x())
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type = "rk319x";
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else if (cpu_is_rk3188())
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type = "rk3188";
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else if (cpu_is_rk3066b())
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type = "rk3066b";
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else if (cpu_is_rk3026())
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type = "rk3026";
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else if (cpu_is_rk30xx())
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type = "rk30xx";
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else if (cpu_is_rk2928())
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type = "rk2928";
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else
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type = "";
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return sprintf(buf, "%s\n", type);
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}
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static struct device_attribute type_attr = __ATTR_RO(type);
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static ssize_t soc_show(struct device *dev, struct device_attribute *attr, char *buf)
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{
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const char *soc;
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if (soc_is_rk3190())
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soc = "rk3190";
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else if (soc_is_rk3188plus())
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soc = "rk3188+";
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else if (soc_is_rk3188())
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soc = "rk3188";
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else if (soc_is_rk3168())
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soc = "rk3168";
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else if (soc_is_rk3028())
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soc = "rk3028";
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else if (soc_is_rk3066b())
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soc = "rk3066b";
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else if (soc_is_rk3028a())
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soc = "rk3028a";
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else if (soc_is_rk3026())
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soc = "rk3026";
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else if (soc_is_rk2928g())
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soc = "rk2928g";
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else if (soc_is_rk2928l())
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soc = "rk2928l";
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else if (soc_is_rk2926())
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soc = "rk2926";
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else if (soc_is_rk3066())
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soc = "rk3066";
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else if (soc_is_rk3068())
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soc = "rk3068";
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else if (soc_is_rk3000())
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soc = "rk3000";
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else
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soc = "";
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return sprintf(buf, "%s\n", soc);
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}
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static struct device_attribute soc_attr = __ATTR_RO(soc);
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static int __init rockchip_cpu_lateinit(void)
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{
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int err;
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err = device_create_file(cpu_subsys.dev_root, &type_attr);
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err = device_create_file(cpu_subsys.dev_root, &soc_attr);
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return err;
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}
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late_initcall(rockchip_cpu_lateinit);
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51
arch/arm/mach-rockchip/cpu.h
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51
arch/arm/mach-rockchip/cpu.h
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@@ -0,0 +1,51 @@
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#ifndef __MACH_ROCKCHIP_CPU_H
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#define __MACH_ROCKCHIP_CPU_H
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extern unsigned long rockchip_soc_id;
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#define ROCKCHIP_CPU_MASK 0xffff0000
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#define ROCKCHIP_CPU_RK2928 0x29280000
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#define ROCKCHIP_CPU_RK3026 0x30260000
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#define ROCKCHIP_CPU_RK30XX 0x30660000
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#define ROCKCHIP_CPU_RK3066B 0x31680000
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#define ROCKCHIP_CPU_RK3188 0x31880000
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#define ROCKCHIP_CPU_RK319X 0x31900000
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static inline bool cpu_is_rk2928(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK2928; }
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static inline bool cpu_is_rk3026(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3026; }
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static inline bool cpu_is_rk30xx(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK30XX; }
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static inline bool cpu_is_rk3066b(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3066B; }
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static inline bool cpu_is_rk3188(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3188; }
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static inline bool cpu_is_rk319x(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK319X; }
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#define ROCKCHIP_SOC_RK2926 (ROCKCHIP_CPU_RK2928 | 0x00)
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#define ROCKCHIP_SOC_RK2928G (ROCKCHIP_CPU_RK2928 | 0x01)
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#define ROCKCHIP_SOC_RK2928L (ROCKCHIP_CPU_RK2928 | 0x02)
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#define ROCKCHIP_SOC_RK3028A (ROCKCHIP_CPU_RK3026 | 0x03)
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#define ROCKCHIP_SOC_RK3026 (ROCKCHIP_CPU_RK3026 | 0x04)
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#define ROCKCHIP_SOC_RK3000 (ROCKCHIP_CPU_RK30XX | 0x00)
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#define ROCKCHIP_SOC_RK3066 (ROCKCHIP_CPU_RK30XX | 0x01)
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#define ROCKCHIP_SOC_RK3068 (ROCKCHIP_CPU_RK30XX | 0x02)
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#define ROCKCHIP_SOC_RK3066B (ROCKCHIP_CPU_RK3066B| 0x00)
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#define ROCKCHIP_SOC_RK3168 (ROCKCHIP_CPU_RK3066B| 0x01)
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#define ROCKCHIP_SOC_RK3028 (ROCKCHIP_CPU_RK3066B| 0x03)
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#define ROCKCHIP_SOC_RK3188 (ROCKCHIP_CPU_RK3188 | 0x00)
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#define ROCKCHIP_SOC_RK3188PLUS (ROCKCHIP_CPU_RK3188 | 0x10)
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#define ROCKCHIP_SOC_RK3190 (ROCKCHIP_CPU_RK319X | 0x00)
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static inline bool soc_is_rk2926(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK2926; }
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static inline bool soc_is_rk2928g(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK2928G; }
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static inline bool soc_is_rk2928l(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK2928L; }
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static inline bool soc_is_rk3028a(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3028A; }
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static inline bool soc_is_rk3026(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3026; }
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static inline bool soc_is_rk3000(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3000; }
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static inline bool soc_is_rk3066(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3066; }
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static inline bool soc_is_rk3068(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3068; }
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static inline bool soc_is_rk3066b(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3066B; }
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static inline bool soc_is_rk3168(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3168; }
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static inline bool soc_is_rk3028(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3028; }
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static inline bool soc_is_rk3188(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3188; }
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static inline bool soc_is_rk3188plus(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3188PLUS; }
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static inline bool soc_is_rk3190(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3190; }
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#endif
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42
arch/arm/mach-rockchip/iomap.h
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42
arch/arm/mach-rockchip/iomap.h
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@@ -0,0 +1,42 @@
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#ifndef __MACH_ROCKCHIP_IOMAP_H
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#define __MACH_ROCKCHIP_IOMAP_H
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#define RK_IO_ADDRESS(x) IOMEM(0xFED00000 + x)
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#define RK_CRU_VIRT RK_IO_ADDRESS(0x00000000)
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#define RK_GRF_VIRT RK_IO_ADDRESS(0x00010000)
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#define RK_PMU_VIRT RK_IO_ADDRESS(0x00020000)
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#define RK_ROM_VIRT RK_IO_ADDRESS(0x00030000)
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#define RK_EFUSE_VIRT RK_IO_ADDRESS(0x00040000)
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#define RK_GPIO_VIRT(n) RK_IO_ADDRESS(0x00050000 + (n) * 0x1000)
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#define RK_DEBUG_UART_VIRT RK_IO_ADDRESS(0x00060000)
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#define RK_CPU_AXI_BUS_VIRT RK_IO_ADDRESS(0x00070000)
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#define RK_TIMER_VIRT RK_IO_ADDRESS(0x00080000)
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#define RK_DDR_VIRT RK_IO_ADDRESS(0x000d0000)
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#define RK3188_CRU_PHYS 0x20000000
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#define RK3188_CRU_SIZE SZ_4K
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#define RK3188_GRF_PHYS 0x20008000
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#define RK3188_GRF_SIZE SZ_4K
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#define RK3188_PMU_PHYS 0x20004000
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#define RK3188_PMU_SIZE SZ_4K
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#define RK3188_ROM_PHYS 0x10120000
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#define RK3188_ROM_SIZE SZ_16K
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#define RK3188_EFUSE_PHYS 0x20010000
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#define RK3188_EFUSE_SIZE SZ_4K
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#define RK3188_GPIO0_PHYS 0x2000a000
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#define RK3188_GPIO1_PHYS 0x2003c000
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#define RK3188_GPIO2_PHYS 0x2003e000
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#define RK3188_GPIO3_PHYS 0x20080000
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#define RK3188_GPIO_SIZE SZ_4K
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#define RK3188_CPU_AXI_BUS_PHYS 0x10128000
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#define RK3188_CPU_AXI_BUS_SIZE SZ_32K
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#define RK3188_TIMER0_PHYS 0x20038000
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#define RK3188_TIMER3_PHYS 0x2000e000
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#define RK3188_TIMER_SIZE SZ_4K
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#define RK3188_DDR_PCTL_PHYS 0x20020000
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#define RK3188_DDR_PCTL_SIZE SZ_16K
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#define RK3188_DDR_PUBL_PHYS 0x20040000
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#define RK3188_DDR_PUBL_SIZE SZ_16K
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#endif
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@@ -24,35 +24,91 @@
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include "core.h"
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#include "cpu.h"
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#include "cpu_axi.h"
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#include "iomap.h"
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#define RK3188_DEVICE(name) \
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{ \
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.virtual = (unsigned long) RK_##name##_VIRT, \
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.pfn = __phys_to_pfn(RK3188_##name##_PHYS), \
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.length = RK3188_##name##_SIZE, \
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.type = MT_DEVICE, \
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}
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static struct map_desc rk3188_io_desc[] __initdata = {
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RK3188_DEVICE(CRU),
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RK3188_DEVICE(GRF),
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RK3188_DEVICE(PMU),
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RK3188_DEVICE(ROM),
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RK3188_DEVICE(EFUSE),
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RK3188_DEVICE(CPU_AXI_BUS),
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{
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.virtual = (unsigned long) RK_DDR_VIRT,
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.pfn = __phys_to_pfn(RK3188_DDR_PCTL_PHYS),
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.length = RK3188_DDR_PCTL_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = (unsigned long) RK_DDR_VIRT + RK3188_DDR_PCTL_SIZE,
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.pfn = __phys_to_pfn(RK3188_DDR_PUBL_PHYS),
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.length = RK3188_DDR_PUBL_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = (unsigned long) RK_GPIO_VIRT(0),
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.pfn = __phys_to_pfn(RK3188_GPIO0_PHYS),
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.length = RK3188_GPIO_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = (unsigned long) RK_GPIO_VIRT(1),
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.pfn = __phys_to_pfn(RK3188_GPIO1_PHYS),
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.length = RK3188_GPIO_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = (unsigned long) RK_GPIO_VIRT(2),
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.pfn = __phys_to_pfn(RK3188_GPIO2_PHYS),
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.length = RK3188_GPIO_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = (unsigned long) RK_GPIO_VIRT(3),
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.pfn = __phys_to_pfn(RK3188_GPIO3_PHYS),
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.length = RK3188_GPIO_SIZE,
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.type = MT_DEVICE,
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},
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};
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static void __init rk3188_dt_map_io(void)
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{
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preset_lpj = 11996091ULL / 2;
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iotable_init(rk3188_io_desc, ARRAY_SIZE(rk3188_io_desc));
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debug_ll_io_init();
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rockchip_soc_id = ROCKCHIP_SOC_RK3188;
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if (readl_relaxed(RK_ROM_VIRT + 0x27f0) == 0x33313042
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&& readl_relaxed(RK_ROM_VIRT + 0x27f4) == 0x32303133
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&& readl_relaxed(RK_ROM_VIRT + 0x27f8) == 0x30313331
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&& readl_relaxed(RK_ROM_VIRT + 0x27fc) == 0x56313031)
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rockchip_soc_id = ROCKCHIP_SOC_RK3188PLUS;
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}
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static void __init rk3188_dt_timer_init(void)
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static void __init rk3188_dt_init_timer(void)
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{
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of_clk_init(NULL);
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clocksource_of_init();
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}
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static void __init rk3188_dt_init(void)
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{
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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}
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static const char * const rk3188_dt_compat[] = {
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"rockchip,rk3188",
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NULL,
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};
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DT_MACHINE_START(RK3188_DT, "Rockchip RK3188 (Flattened Device Tree)")
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//.nr_irqs = 32*10,
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.smp = smp_ops(rockchip_smp_ops),
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.map_io = rk3188_dt_map_io,
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.init_machine = rk3188_dt_init,
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.init_time = rk3188_dt_timer_init,
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.init_time = rk3188_dt_init_timer,
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.dt_compat = rk3188_dt_compat,
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MACHINE_END
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