shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-06 02:50:49 +09:00
Code Issues Packages Projects Releases Wiki Activity

PCI: rockchip: dw-ep: Support ltssm fifo debug

Browse Source 
Set RK_PCIE_DBG to 1 to enable ltssm fifo debug.

Change-Id: If88824e7bb7455006b0cf7ceac5bb901bf76f282
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Jon Lin
2025-03-09 17:00:44 +08:00
committed by Tao Huang
parent e31d0ecd30
commit ad8d1ad7f2
1 changed files with 41 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

41
drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c
View File

@@ -35,6 +35,17 @@
#define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
#define RK_PCIE_DBG 0
#define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310
#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320
#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324
#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328
#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c
#define PCIE_CLIENT_DBG_FIFO_STATUS 0x350
#define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000
#define PCIE_CLIENT_DBF_EN 0xffff0007
#define PCIE_DMA_OFFSET 0x380000
#define PCIE_DMA_CTRL_OFF 0x8
@@ -751,6 +762,33 @@ static void rockchip_pcie_hide_broken_ats_cap(struct dw_pcie *pci)
dw_pcie_dbi_ro_wr_dis(pci);
}
static void rockchip_pcie_enable_debug(struct rockchip_pcie *rockchip)
{
rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DBG_TRANSITION_DATA,
PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0);
rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DBG_TRANSITION_DATA,
PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1);
rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DBG_TRANSITION_DATA,
PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0);
rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DBG_TRANSITION_DATA,
PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1);
rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DBF_EN,
PCIE_CLIENT_DBG_FIFO_MODE_CON);
}
static void rockchip_pcie_debug_dump(struct rockchip_pcie *rockchip)
{
#if RK_PCIE_DBG
u32 loop;
dev_info(rockchip->pci.dev, "ltssm = 0x%x\n",
rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS));
for (loop = 0; loop < 64; loop++)
dev_info(rockchip->pci.dev, "fifo_status = 0x%x\n",
rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_DBG_FIFO_STATUS));
#endif
}
static int rockchip_pcie_config_host(struct rockchip_pcie *rockchip)
{
struct device *dev = rockchip->pci.dev;
@@ -822,6 +860,7 @@ static int rockchip_pcie_config_host(struct rockchip_pcie *rockchip)
dev_info(dev, "hot reset ever\n");
}
rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
rockchip_pcie_enable_debug(rockchip);
retries = 1000;
for (i = 0; i < retries; i++) {
@@ -838,12 +877,14 @@ static int rockchip_pcie_config_host(struct rockchip_pcie *rockchip)
if (dw_pcie_link_up(pci)) {
dev_info(pci->dev, "PCIe Link up, LTSSM is 0x%x\n",
rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS));
rockchip_pcie_debug_dump(rockchip);
break;
}
}
dev_info_ratelimited(dev, "PCIe Linking... LTSSM is 0x%x\n",
rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS));
rockchip_pcie_debug_dump(rockchip);
msleep(20);
}