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Merge commit '7566b06bc28508ec9c88917e4422b7633c860459'
* commit '7566b06bc28508ec9c88917e4422b7633c860459': iio: imu: inv_icm42670: add drive-open-drain setting spi: rockchip-slave: Get rid of the sram driver dependency iio: imu: inv_icm42670: use low pass filter bypassed pinctrl: rockchip: rk3328: Fix pinmux for GPIO2-B Change-Id: Ie4872af2463e81fcbbdabf6ee1df4d336e482141
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@@ -166,6 +166,28 @@
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#define BIT_ACCEL_UI_FS_SEL_MASK GENMASK(6, 5)
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#define BIT_ACCEL_ODR_MASK GENMASK(3, 0)
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/*
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* GYRO_CONFIG1
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* Register Name : GYRO_CONFIG1
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*/
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/*
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* gyro_ui_filt_bw
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* Selects GYRO UI low pass filter bandwidth
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*
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* 000: Low pass filter bypassed
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* 001: 180 Hz
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* 010: 121 Hz
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* 011: 73 Hz
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* 100: 53 Hz
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* 101: 34 Hz
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* 110: 25 Hz
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* 111: 16 Hz
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*
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* This field can be changed on-the-fly even if gyro sensor is on
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*/
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#define GYRO_CONFIG1_GYRO_UI_FILT_BW_MASK 0x07
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/* Bank0 REG_GYRO_CONFIG1 */
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#define BIT_GYR_UI_FLT_BW_BYPASS 0x00
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#define BIT_GYR_UI_FLT_BW_180HZ 0x01
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@@ -182,6 +204,23 @@
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#define BIT_GYR_UI_AVG_IND_32X 0x40
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#define BIT_GYR_UI_AVG_IND_64X 0x50
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/*
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* accel_ui_filt_bw
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* Selects ACCEL UI low pass filter bandwidth
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*
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* 000: Low pass filter bypassed
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* 001: 180 Hz
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* 010: 121 Hz
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* 011: 73 Hz
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* 100: 53 Hz
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* 101: 34 Hz
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* 110: 25 Hz
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* 111: 16 Hz
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*
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* This field can be changed on-the-fly even if accel sensor is on
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*/
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#define ACCEL_CONFIG1_ACCEL_UI_FILT_BW_MASK 0x07
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/* Bank0 REG_ACCEL_CONFIG1 */
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#define BIT_ACC_FILT_BW_IND_BYPASS 0x00
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#define BIT_ACC_FILT_BW_IND_180HZ 0x01
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@@ -204,12 +243,12 @@
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#define SHIFT_INT1_POLARITY 0x00
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#define BIT_ONLY_INT1_ACTIVE_HIGH \
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((1 << SHIFT_INT1_POLARITY) | \
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(1 << SHIFT_INT1_DRIVE_CIRCUIT) | \
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(0 << SHIFT_INT1_MODE))
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#define BIT_ONLY_INT1_ACTIVE_LOW \
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((0 << SHIFT_INT1_POLARITY) | \
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(1 << SHIFT_INT1_DRIVE_CIRCUIT) | \
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(0 << SHIFT_INT1_MODE))
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#define BIT_ONLY_INT1_OPEN_DRAIN (0 << SHIFT_INT1_DRIVE_CIRCUIT)
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#define BIT_ONLY_INT1_PUSH_PULL (1 << SHIFT_INT1_DRIVE_CIRCUIT)
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/* Bank0 REG_PWR_MGMT_0 */
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#define BIT_PWR_MGMTO_ACCEL_LP_CLK_SEL BIT(7)
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@@ -988,6 +988,22 @@ static int icm42670_chip_init(struct icm42670_data *data, icm42670_bus_setup bus
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return ret;
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}
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ret = regmap_update_bits(data->regmap, REG_GYRO_CONFIG1,
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GYRO_CONFIG1_GYRO_UI_FILT_BW_MASK,
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BIT_GYR_UI_FLT_BW_BYPASS);
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if (ret < 0) {
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dev_err(dev, "icm42670 set gyro ln bw failed!\r\n");
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return ret;
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}
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ret = regmap_update_bits(data->regmap, REG_ACCEL_CONFIG1,
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ACCEL_CONFIG1_ACCEL_UI_FILT_BW_MASK,
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BIT_ACC_FILT_BW_IND_BYPASS);
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if (ret < 0) {
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dev_err(dev, "icm42670 set accel ln bw failed!\r\n");
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return ret;
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}
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ret = regmap_write(data->regmap, REG_INT_CONFIG_REG, data->irq_mask);
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if (ret < 0)
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return ret;
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@@ -1055,6 +1071,11 @@ int icm42670_core_probe(struct regmap *regmap,
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return -EINVAL;
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}
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if (device_property_read_bool(dev, "drive-open-drain"))
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data->irq_mask |= BIT_ONLY_INT1_OPEN_DRAIN;
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else
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data->irq_mask |= BIT_ONLY_INT1_PUSH_PULL;
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data->vdd_supply = devm_regulator_get(dev, "vcc_3v3_s0");
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if (IS_ERR(data->vdd_supply)) {
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dev_err(dev, "Could not find vdd_avdd!\n");
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@@ -719,49 +719,7 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
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static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
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{
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.num = 2,
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.pin = 8,
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.reg = 0x24,
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.bit = 0,
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.mask = 0x3
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}, {
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.num = 2,
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.pin = 9,
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.reg = 0x24,
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.bit = 2,
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.mask = 0x3
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}, {
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.num = 2,
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.pin = 10,
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.reg = 0x24,
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.bit = 4,
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.mask = 0x3
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}, {
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.num = 2,
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.pin = 11,
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.reg = 0x24,
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.bit = 6,
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.mask = 0x3
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}, {
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.num = 2,
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.pin = 12,
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.reg = 0x24,
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.bit = 8,
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.mask = 0x3
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}, {
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/* gpio2_b7_sel */
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.num = 2,
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.pin = 13,
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.reg = 0x24,
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.bit = 10,
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.mask = 0x3
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}, {
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.num = 2,
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.pin = 14,
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.reg = 0x24,
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.bit = 12,
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.mask = 0x3
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}, {
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.num = 2,
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.pin = 15,
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.reg = 0x28,
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@@ -813,9 +813,9 @@ static int rockchip_spi_slave_probe(struct platform_device *pdev)
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rs->max_transfer_size = resource_size(&sram_res);
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rs->dma_phys = sram_res.start;
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rs->dma_buf = devm_ioremap_resource(&pdev->dev, &sram_res);
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if (IS_ERR(rs->dma_buf)) {
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ret = PTR_ERR(rs->dma_buf);
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rs->dma_buf = devm_ioremap(&pdev->dev, sram_res.start, resource_size(&sram_res));
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if (!rs->dma_buf) {
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ret = -ENOMEM;
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goto err_put_ctlr;
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}
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dev_err(&pdev->dev, "set sram_buf\n");
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