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move screen、transmitter、tve to rockchip

Browse Source 
screen:indepent from jetta scaler
screen private info indepent from rk_screen
This commit is contained in:
yxj
2013-05-30 12:16:40 +08:00
parent f2fb554178
commit add5bbb626
106 changed files with 4094 additions and 4407 deletions
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4
drivers/video/Kconfig
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@@ -2439,11 +2439,13 @@ source "drivers/video/omap2/Kconfig"
source "drivers/video/backlight/Kconfig"
source "drivers/video/display/Kconfig"
if !LCDC_RK30 && !LCDC_RK2928
if ARCH_RK29
source "drivers/video/hdmi/Kconfig"
endif
if !ARCH_RK29
source "drivers/video/rockchip/Kconfig"
endif
if VT
source "drivers/video/console/Kconfig"

5
drivers/video/display/Kconfig
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@@ -21,9 +21,8 @@ config DISPLAY_SUPPORT
comment "Display hardware drivers"
depends on DISPLAY_SUPPORT
if ARCH_RK29
source "drivers/video/display/screen/Kconfig"
source "drivers/video/display/transmitter/Kconfig"
source "drivers/video/display/tve/Kconfig"
endif
endmenu

3
drivers/video/display/Makefile
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@@ -3,6 +3,3 @@
display-objs := display-sys.o
obj-$(CONFIG_DISPLAY_SUPPORT) += display.o
obj-$(CONFIG_DISPLAY_SUPPORT) += screen/
obj-y += transmitter/
obj-y += tve/

153
drivers/video/display/screen/Kconfig Executable file → Normal file
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@@ -1,154 +1,33 @@
choice
depends on DISPLAY_SUPPORT
prompt "LCD Panel Select"
config LCD_NULL
depends on FB_RK29
prompt "LCD Panel Select for rk2918 platform"
config LCD_RK29_NULL
bool "NULL"
config LCD_RK2928
bool "RK2928 LCD"
depends on MACH_RK2928
config LCD_LG_LP097X02
config LCD_RK29_LG_LP097X02
bool "RGB LCD_LG_LP097X02 1024X768"
config LCD_TD043MGEA1
bool "RGB TD043MGEA1"
config LCD_HX8357
bool "RGB HX8357"
config LCD_TJ048NC01CA
bool "RGB TJ048NC01CA"
config LCD_HL070VM4AU
bool "RGB_HL070VM4AU"
config LCD_HSD070IDW1
bool "RGB Hannstar800x480"
config LCD_RGB_TFT480800_25_E
bool "RGB TFT480800_25_E"
config LCD_HSD100PXN
config LCD_RK29_HSD100PXN
bool "RGB Hannstar HSD100PXN(1024X768)"
config LCD_BYD8688FTGF
bool "RGB BYD 1024X600 8688FTGF"
config LCD_B101AW06
bool "RGB Hannstar B101AW06(1024X600)"
config LCD_RGB_TFT480800_25_E
bool "RGB TFT480800_25_E(480X800)"
config LCD_LS035Y8DX02A
config LCD_RK29_LS035Y8DX02A
bool "RGB LS035Y8DX02A(480X800)"
config LCD_LS035Y8DX04A
config LCD_RK29_LS035Y8DX04A
bool "RGB LS035Y8DX04A(480X800)"
config LCD_HSD100PXN_FOR_TDW851
bool "RGB Hannstar HSD100PXN(800X480)"
config LCD_CPTCLAA038LA31XE
bool "RGB LCD_CPTCLAA038LA31XE(480X800)"
config LCD_A060SE02
bool "MCU A060SE02"
config LCD_S1D13521
bool "MCU S1D13521"
config LCD_NT35582
bool "MCU NT35582"
config LCD_NT35580
bool "MCU NT35580"
config LCD_IPS1P5680_V1_E
bool "MCU IPS1P5680_V1_E"
config LCD_MCU_TFT480800_25_E
bool "MCU TFT480800_25_E"
config LCD_NT35510
bool "RGB lcd_nt35510"
config LCD_ILI9803_CPT4_3
bool "RGB lcd_ILI9803_CPT4_3"
config LCD_IPS1P5680_V1_E
bool "MCU IPS1P5680_V1_E"
config LCD_MCU_TFT480800_25_E
bool "MCU TFT480800_25_E"
config LCD_RK29_NT35510
bool "RGB lcd_nt35510"
config DEFAULT_OUT_HDMI
bool "HDMI for default panel"
depends on HDMI
---help---
if you want set HDMI for default panel, android UI size is HDMI default resolution.
config LCD_AT070TNA2
bool "RGB AT070TNA2"
config LCD_AT070TN93
bool "RGB AT070TN93"
config LCD_TX23D88VM
bool "HITACHI LVDS TX23D88VM (1200x800)"
config LCD_A050VL01
config LCD_RK29_A050VL01
bool "RGB A050VL01"
config LCD_B101EW05
bool "RGB lcd panel B101EW05"
config LCD_RK3168M_B101EW05
bool "RGB lcd panel LCD_RK3168M_B101EW05"
config LCD_HJ050NA_06A
bool "RGB lcd panel HJ050NA-06A"
config LCD_HDMI_1366x768
depends on MFD_RK610
bool "RK610 LCD_HDMI_1366X768"
---help---
if support RK610, this setting can support dual screen output
config LCD_HDMI_1280x800
depends on MFD_RK610
bool "RGB Hannstar LCD_HDMI_1280X800"
---help---
if support RK610, this setting can support dual screen output
config LCD_HDMI_1024x768
depends on MFD_RK610
bool "RGB Hannstar LCD_HDMI_1024X768"
---help---
if support RK610, this setting can support dual screen output
config LCD_HSD07PFW1
depends on MFD_RK610
bool "RGB Hannstar LCD_HDMI_1024X600"
config LCD_HDMI_800x480
depends on MFD_RK610
bool "RGB Hannstar LCD_HDMI_800x480"
---help---
if support RK610, this setting can support dual screen output
config LCD_HV070WSA100
bool "HV070WSA-100 1024X600"
config LCD_COMMON
bool "LCD COMMON"
config LCD_RK3168_AUO_A080SN03
bool "RK3168 auo panel 800x480"
config LCD_RK2928_A720
bool "RK2928 A720 panel 800x480"
config LCD_RK2926_V86
bool "RK2926 v86 panel 800x480"
config LCD_RK3168_86V
bool "RK3168 86v panel 800x480"
config LCD_HJ080NA
bool "HJ080NA_4J 1024X768"
config LCD_HJ101NA
bool "HJ101NA_4J 1280X800"
config LCD_AUTO
bool "auto select lcd"
config LCD_HSD07PFW1
depends on MFD_RK610
bool "RGB lcd panel HSD07PFW1"
config LCD_I30_800X480
bool "lcd I30"
config LCD_TL5001_MIPI
bool "TL5001 720X1280"
config LCD_LP097QX1
bool "Display Port screen LP097QX1"
config LCD_DS1006H
bool "Lvds screen for ds1006h(RK3168)"
config LCD_B101UANO_1920x1200
bool "Lvds screen B101UANO for u30gt2"
config LCD_E242868_1024X600
bool "RK3168 86v RGB 1024*600 "
config LCD_WY_800X480
bool "lcd for 760"
config LCD_HH070D_LVDS
bool "lcd lvds for 760"
endchoice

66
drivers/video/display/screen/Makefile Executable file → Normal file
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@@ -1,62 +1,12 @@
obj-$(CONFIG_LCD_NULL) += lcd_null.o
obj-$(CONFIG_LCD_RK29_NULL) += lcd_null.o
obj-$(CONFIG_LCD_RK2928) += lcd_rk2928.o
obj-$(CONFIG_LCD_RK29_LG_LP097X02)+= lcd_LG_LP097X02.o
obj-$(CONFIG_LCD_RK29_LS035Y8DX02A) += lcd_ls035y8dx02a.o
obj-$(CONFIG_LCD_RK29_LS035Y8DX04A) += lcd_ls035y8dx04a.o
obj-$(CONFIG_LCD_RK29_HSD100PXN) += lcd_hsd100pxn.o
obj-$(CONFIG_LCD_RK29_NT35510) += lcd_nt35510.o
obj-$(CONFIG_LCD_RK29_A050VL01) += lcd_A050VL01.o
obj-$(CONFIG_LCD_TD043MGEA1) += lcd_td043mgea1.o
obj-$(CONFIG_LCD_HSD070IDW1) += lcd_hsd800x480.o
obj-$(CONFIG_LCD_HL070VM4AU) += lcd_hl070vm4.o
obj-$(CONFIG_LCD_BYD8688FTGF) += lcd_byd1024x600.o
obj-$(CONFIG_LCD_LG_LP097X02)+= lcd_LG_LP097X02.o
obj-$(CONFIG_LCD_TJ048NC01CA) += lcd_tj048nc01ca.o
obj-$(CONFIG_LCD_A060SE02) += lcd_a060se02.o
obj-$(CONFIG_LCD_S1D13521) += lcd_s1d13521.o
obj-$(CONFIG_LCD_NT35582) += lcd_nt35582.o
obj-$(CONFIG_LCD_NT35580) += lcd_nt35580.o
obj-$(CONFIG_LCD_IPS1P5680_V1_E) += lcd_ips1p5680_v1_e.o
obj-$(CONFIG_LCD_RGB_TFT480800_25_E) += lcd_rgb_tft480800_25_e.o
obj-$(CONFIG_LCD_MCU_TFT480800_25_E) += lcd_mcu_tft480800_25_e.o
obj-$(CONFIG_LCD_LS035Y8DX02A) += lcd_ls035y8dx02a.o
obj-$(CONFIG_LCD_LS035Y8DX04A) += lcd_ls035y8dx04a.o
obj-$(CONFIG_LCD_CPTCLAA038LA31XE) += lcd_CPTclaa038la31xe.o
obj-$(CONFIG_LCD_HX8357) += lcd_hx8357.o
obj-$(CONFIG_LCD_HSD100PXN) += lcd_hsd100pxn.o
obj-$(CONFIG_LCD_HDMI_1366x768) += lcd_hdmi_1366x768.o
obj-$(CONFIG_LCD_HDMI_1280x800) += lcd_hdmi_1280x800.o
obj-$(CONFIG_LCD_HDMI_1024x768) += lcd_hdmi_1024x768.o
obj-$(CONFIG_LCD_HDMI_800x480) += lcd_hdmi_800x480.o
obj-$(CONFIG_LCD_B101AW06) += lcd_B101AW06.o
obj-$(CONFIG_LCD_NT35510) += lcd_nt35510.o
obj-$(CONFIG_LCD_ILI9803_CPT4_3) += lcd_ili9803_cpt4_3.o
obj-$(CONFIG_LCD_RGB_TFT480800_25_E) += lcd_rgb_tft480800_25_e.o
obj-$(CONFIG_LCD_LS035Y8DX02A) += lcd_ls035y8dx02a.o
obj-$(CONFIG_LCD_IPS1P5680_V1_E) += lcd_ips1p5680_v1_e.o
obj-$(CONFIG_LCD_MCU_TFT480800_25_E) += lcd_mcu_tft480800_25_e.o
obj-$(CONFIG_LCD_AT070TNA2) += lcd_AT070TNA2.o
obj-$(CONFIG_LCD_TX23D88VM) += lcd_tx23d88vm.o
obj-$(CONFIG_LCD_AT070TN93) += lcd_at070tn93.o
obj-$(CONFIG_LCD_A050VL01) += lcd_A050VL01.o
obj-$(CONFIG_LCD_B101EW05) += lcd_b101ew05.o
obj-$(CONFIG_LCD_RK3168M_B101EW05) += lcd_hdmi_rk3168m_b101ew05.o
obj-$(CONFIG_LCD_HJ050NA_06A) += lcd_hj050na_06a.o
obj-$(CONFIG_LCD_HSD100PXN_FOR_TDW851) += lcd_hsd100pxn_for_tdw851.o
obj-$(CONFIG_LCD_HV070WSA100) += lcd_hv070wsa.o
obj-$(CONFIG_LCD_COMMON) += lcd_common.o
obj-$(CONFIG_LCD_RK2928_A720) += lcd_YQ70CPT9160.o
obj-$(CONFIG_LCD_RK3168_AUO_A080SN03) += lcd_AUO_A080SN03.o
obj-$(CONFIG_LCD_RK2926_V86) += lcd_YQ70CPT9160_v86.o
obj-$(CONFIG_LCD_RK3168_86V) += lcd_YQ70CPT9160_rk3168_86v.o
obj-$(CONFIG_LCD_HSD07PFW1) += lcd_hdmi_1024x600.o
obj-$(CONFIG_LCD_HJ080NA) += lcd_hj080na.o
obj-$(CONFIG_LCD_HJ101NA) += lcd_hj101na.o
obj-$(CONFIG_LCD_AUTO) += lcd_auto.o
obj-$(CONFIG_LCD_I30_800X480) += lcd_I30_800x480.o
obj-$(CONFIG_LCD_TL5001_MIPI) += lcd_tl5001_mipi.o
obj-$(CONFIG_LCD_LP097QX1) += lcd_LP097QX1.o
obj-$(CONFIG_LCD_DS1006H) += lcd_ds1006h.o
obj-$(CONFIG_LCD_B101UANO_1920x1200) += lcd_b101uano_1920x1200.o
obj-$(CONFIG_LCD_E242868_1024X600) += lcd_E242868_rk3168_86v.o
obj-$(CONFIG_LCD_WY_800X480) += lcd_wy_800x480.o
obj-$(CONFIG_LCD_HH070D_LVDS) += lcd_hh070d_lvds.o

89
drivers/video/display/screen/lcd_AUO_A080SN03.c
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@@ -1,89 +0,0 @@
/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */
#include <linux/delay.h>
#include<linux/rk_fb.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P888//OUT_P666
#define OUT_CLK 40000000
#define LCDC_ACLK 500000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 1//30//48 //10
#define H_BP 46//10//40 //100
#define H_VD 800 //1024
#define H_FP 210// //210
#define V_PW 3// 2// 3//13//10
#define V_BP 23// 18 // 23//10// //10
#define V_VD 600//480 //768
#define V_FP 2// 8// 12//22 //18
/* Other */
#define DCLK_POL 1
#define SWAP_RB 0
#define LCD_WIDTH 162//154 //need modify
#define LCD_HEIGHT 121//85
static struct rk29lcd_info *gLcd_info = NULL;
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
/*screen->init = init;*/
screen->init = NULL;
screen->standby = NULL;
if(lcd_info)
gLcd_info = lcd_info;
}
size_t get_fb_size(void)
{
size_t size = 0;
#if defined(CONFIG_THREE_FB_BUFFER)
size = ((H_VD)*(V_VD)<<2)* 3; //three buffer
#else
size = ((H_VD)*(V_VD)<<2)<<1; //two buffer
#endif
return ALIGN(size,SZ_1M);
}

195
drivers/video/display/screen/lcd_E242868_rk3168_86v.c
View File

@@ -1,195 +0,0 @@
/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */
#include <linux/fb.h>
#include <linux/rk_fb.h>
#include <linux/delay.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include "screen.h"
#include <linux/hdmi.h>
//#include "../../rk29_fb.h"
#include "../transmitter/rk610_lcd.h"
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P888
#define OUT_CLK 50000000
#define LCDC_ACLK 500000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 30
#define H_BP 10
#define H_VD 1024
#define H_FP 210
#define V_PW 13
#define V_BP 10
#define V_VD 600
#define V_FP 22
#define LCD_WIDTH 154
#define LCD_HEIGHT 85
/* Other */
#define DCLK_POL 0
#define SWAP_RB 0
#ifdef CONFIG_HDMI_DUAL_DISP
static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
{
screen->s_clk_inv = S_DCLK_POL;
screen->s_den_inv = 0;
screen->s_hv_sync_inv = 0;
switch(hdmi_resolution){
case HDMI_1920x1080p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S_OUT_CLK;
screen->s_hsync_len = S_H_PW;
screen->s_left_margin = S_H_BP;
screen->s_right_margin = S_H_FP;
screen->s_hsync_len = S_H_PW;
screen->s_upper_margin = S_V_BP;
screen->s_lower_margin = S_V_FP;
screen->s_vsync_len = S_V_PW;
screen->s_hsync_st = S_H_ST;
screen->s_vsync_st = S_V_ST;
break;
case HDMI_1920x1080p_50Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S1_OUT_CLK;
screen->s_hsync_len = S1_H_PW;
screen->s_left_margin = S1_H_BP;
screen->s_right_margin = S1_H_FP;
screen->s_hsync_len = S1_H_PW;
screen->s_upper_margin = S1_V_BP;
screen->s_lower_margin = S1_V_FP;
screen->s_vsync_len = S1_V_PW;
screen->s_hsync_st = S1_H_ST;
screen->s_vsync_st = S1_V_ST;
break;
case HDMI_1280x720p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S2_OUT_CLK;
screen->s_hsync_len = S2_H_PW;
screen->s_left_margin = S2_H_BP;
screen->s_right_margin = S2_H_FP;
screen->s_hsync_len = S2_H_PW;
screen->s_upper_margin = S2_V_BP;
screen->s_lower_margin = S2_V_FP;
screen->s_vsync_len = S2_V_PW;
screen->s_hsync_st = S2_H_ST;
screen->s_vsync_st = S2_V_ST;
break;
case HDMI_1280x720p_50Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S3_OUT_CLK;
screen->s_hsync_len = S3_H_PW;
screen->s_left_margin = S3_H_BP;
screen->s_right_margin = S3_H_FP;
screen->s_hsync_len = S3_H_PW;
screen->s_upper_margin = S3_V_BP;
screen->s_lower_margin = S3_V_FP;
screen->s_vsync_len = S3_V_PW;
screen->s_hsync_st = S3_H_ST;
screen->s_vsync_st = S3_V_ST;
break;
case HDMI_720x576p_50Hz_4x3:
case HDMI_720x576p_50Hz_16x9:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S4_OUT_CLK;
screen->s_hsync_len = S4_H_PW;
screen->s_left_margin = S4_H_BP;
screen->s_right_margin = S4_H_FP;
screen->s_hsync_len = S4_H_PW;
screen->s_upper_margin = S4_V_BP;
screen->s_lower_margin = S4_V_FP;
screen->s_vsync_len = S4_V_PW;
screen->s_hsync_st = S4_H_ST;
screen->s_vsync_st = S4_V_ST;
break;
case HDMI_720x480p_60Hz_16x9:
case HDMI_720x480p_60Hz_4x3:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S5_OUT_CLK;
screen->s_hsync_len = S5_H_PW;
screen->s_left_margin = S5_H_BP;
screen->s_right_margin = S5_H_FP;
screen->s_hsync_len = S5_H_PW;
screen->s_upper_margin = S5_V_BP;
screen->s_lower_margin = S5_V_FP;
screen->s_vsync_len = S5_V_PW;
screen->s_hsync_st = S5_H_ST;
screen->s_vsync_st = S5_V_ST;
break;
default :
printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution);
return -1;
break;
}
return 0;
}
#else
static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution){}
#endif
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
/*screen->init = init;*/
screen->init = NULL;
screen->standby = NULL;
screen->sscreen_get = set_scaler_info;
#ifdef CONFIG_RK610_LVDS
screen->sscreen_set = rk610_lcd_scaler_set_param;
#endif
}
size_t get_fb_size(void)
{
size_t size = 0;
#if defined(CONFIG_THREE_FB_BUFFER)
size = ((H_VD)*(V_VD)<<2)* 3; //three buffer
#else
size = ((H_VD)*(V_VD)<<2)<<1; //two buffer
#endif
return ALIGN(size,SZ_1M);
}

109
drivers/video/display/screen/lcd_I30_800x480.c
View File

@@ -1,109 +0,0 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include "screen.h"
/* Base */
#define LCD_WIDTH 154 //need modify
#define LCD_HEIGHT 85
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P666
#define OUT_CLK 30000000
#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 48 //10
#define H_BP 88 //100
#define H_VD 800
#define H_FP 40 //210
#define V_PW 3 //10
#define V_BP 32 //10
#define V_VD 480
#define V_FP 13 //18
/* Other */
#define DCLK_POL 1
#define SWAP_RB 0
static struct rk29lcd_info *gLcd_info = NULL;
static int init(void)
{
int ret = 0;
if(gLcd_info && gLcd_info->io_init)
gLcd_info->io_init();
return 0;
}
static int standby(u8 enable)
{
if(!enable)
{
if(gLcd_info && gLcd_info->io_enable)
gLcd_info->io_enable();
}
else
{
if(gLcd_info && gLcd_info->io_disable)
gLcd_info->io_disable();
}
return 0;
}
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
screen->init = init;
screen->standby = standby;
if(lcd_info)
{
gLcd_info = lcd_info;
}
else
{
printk("%s lcd_info==NULL\n", __func__);
}
}

0
drivers/video/display/screen/lcd_LG_LP097X02.c Executable file → Normal file
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80
drivers/video/display/screen/lcd_YQ70CPT9160.c
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@@ -1,80 +0,0 @@
/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include "screen.h"
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P666
#define OUT_CLK 33000000
#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 30//48 //10
#define H_BP 10//40 //100
#define H_VD 800 //1024
#define H_FP 210// //210
#define V_PW 13//10
#define V_BP 10// //10
#define V_VD 480 //768
#define V_FP 22 //18
/* Other */
#define DCLK_POL 1
#define SWAP_RB 0
#define LCD_WIDTH 154 //need modify
#define LCD_HEIGHT 85
static struct rk29lcd_info *gLcd_info = NULL;
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
/*screen->init = init;*/
screen->init = NULL;
screen->standby = NULL;
if(lcd_info)
gLcd_info = lcd_info;
}

195
drivers/video/display/screen/lcd_YQ70CPT9160_rk3168_86v.c
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@@ -1,195 +0,0 @@
/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */
#include <linux/fb.h>
#include <linux/rk_fb.h>
#include <linux/delay.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include "screen.h"
#include <linux/hdmi.h>
//#include "../../rk29_fb.h"
#include "../transmitter/rk610_lcd.h"
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P888
#define OUT_CLK 33000000
#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 30//48 //10
#define H_BP 10//40 //100
#define H_VD 800 //1024
#define H_FP 210// //210
#define V_PW 13//10
#define V_BP 10// //10
#define V_VD 480 //768
#define V_FP 22 //18
#define LCD_WIDTH 154
#define LCD_HEIGHT 85
/* Other */
#define DCLK_POL 0
#define SWAP_RB 0
#ifdef CONFIG_HDMI_DUAL_DISP
static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
{
screen->s_clk_inv = S_DCLK_POL;
screen->s_den_inv = 0;
screen->s_hv_sync_inv = 0;
switch(hdmi_resolution){
case HDMI_1920x1080p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S_OUT_CLK;
screen->s_hsync_len = S_H_PW;
screen->s_left_margin = S_H_BP;
screen->s_right_margin = S_H_FP;
screen->s_hsync_len = S_H_PW;
screen->s_upper_margin = S_V_BP;
screen->s_lower_margin = S_V_FP;
screen->s_vsync_len = S_V_PW;
screen->s_hsync_st = S_H_ST;
screen->s_vsync_st = S_V_ST;
break;
case HDMI_1920x1080p_50Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S1_OUT_CLK;
screen->s_hsync_len = S1_H_PW;
screen->s_left_margin = S1_H_BP;
screen->s_right_margin = S1_H_FP;
screen->s_hsync_len = S1_H_PW;
screen->s_upper_margin = S1_V_BP;
screen->s_lower_margin = S1_V_FP;
screen->s_vsync_len = S1_V_PW;
screen->s_hsync_st = S1_H_ST;
screen->s_vsync_st = S1_V_ST;
break;
case HDMI_1280x720p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S2_OUT_CLK;
screen->s_hsync_len = S2_H_PW;
screen->s_left_margin = S2_H_BP;
screen->s_right_margin = S2_H_FP;
screen->s_hsync_len = S2_H_PW;
screen->s_upper_margin = S2_V_BP;
screen->s_lower_margin = S2_V_FP;
screen->s_vsync_len = S2_V_PW;
screen->s_hsync_st = S2_H_ST;
screen->s_vsync_st = S2_V_ST;
break;
case HDMI_1280x720p_50Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S3_OUT_CLK;
screen->s_hsync_len = S3_H_PW;
screen->s_left_margin = S3_H_BP;
screen->s_right_margin = S3_H_FP;
screen->s_hsync_len = S3_H_PW;
screen->s_upper_margin = S3_V_BP;
screen->s_lower_margin = S3_V_FP;
screen->s_vsync_len = S3_V_PW;
screen->s_hsync_st = S3_H_ST;
screen->s_vsync_st = S3_V_ST;
break;
case HDMI_720x576p_50Hz_4x3:
case HDMI_720x576p_50Hz_16x9:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S4_OUT_CLK;
screen->s_hsync_len = S4_H_PW;
screen->s_left_margin = S4_H_BP;
screen->s_right_margin = S4_H_FP;
screen->s_hsync_len = S4_H_PW;
screen->s_upper_margin = S4_V_BP;
screen->s_lower_margin = S4_V_FP;
screen->s_vsync_len = S4_V_PW;
screen->s_hsync_st = S4_H_ST;
screen->s_vsync_st = S4_V_ST;
break;
case HDMI_720x480p_60Hz_16x9:
case HDMI_720x480p_60Hz_4x3:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S5_OUT_CLK;
screen->s_hsync_len = S5_H_PW;
screen->s_left_margin = S5_H_BP;
screen->s_right_margin = S5_H_FP;
screen->s_hsync_len = S5_H_PW;
screen->s_upper_margin = S5_V_BP;
screen->s_lower_margin = S5_V_FP;
screen->s_vsync_len = S5_V_PW;
screen->s_hsync_st = S5_H_ST;
screen->s_vsync_st = S5_V_ST;
break;
default :
printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution);
return -1;
break;
}
return 0;
}
#else
static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution){}
#endif
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
/*screen->init = init;*/
screen->init = NULL;
screen->standby = NULL;
screen->sscreen_get = set_scaler_info;
#ifdef CONFIG_RK610_LVDS
screen->sscreen_set = rk610_lcd_scaler_set_param;
#endif
}
size_t get_fb_size(void)
{
size_t size = 0;
#if defined(CONFIG_THREE_FB_BUFFER)
size = ((H_VD)*(V_VD)<<2)* 3; //three buffer
#else
size = ((H_VD)*(V_VD)<<2)<<1; //two buffer
#endif
return ALIGN(size,SZ_1M);
}

80
drivers/video/display/screen/lcd_YQ70CPT9160_v86.c
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@@ -1,80 +0,0 @@
/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include "screen.h"
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P666
#define OUT_CLK 33000000
#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 30//48 //10
#define H_BP 10//40 //100
#define H_VD 800 //1024
#define H_FP 210// //210
#define V_PW 13//10
#define V_BP 10// //10
#define V_VD 480 //768
#define V_FP 22 //18
/* Other */
#define DCLK_POL 0
#define SWAP_RB 0
#define LCD_WIDTH 154 //need modify
#define LCD_HEIGHT 85
static struct rk29lcd_info *gLcd_info = NULL;
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
/*screen->init = init;*/
screen->init = NULL;
screen->standby = NULL;
if(lcd_info)
gLcd_info = lcd_info;
}

455
drivers/video/display/screen/lcd_b101ew05.c
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@@ -1,455 +0,0 @@
#include <linux/delay.h>
#include <linux/rk_fb.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#if defined(CONFIG_RK_HDMI)
#include "../../rockchip/hdmi/rk_hdmi.h"
#endif
#if defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS)
#include "../transmitter/rk610_lcd.h"
#endif
/* Base */
#if defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS)
#define OUT_TYPE SCREEN_LVDS
#define LVDS_FORMAT LVDS_8BIT_2
#else
#define OUT_TYPE SCREEN_RGB
#endif
#define OUT_FACE OUT_D888_P666
#define OUT_CLK 71000000
#define LCDC_ACLK 300000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 10
#define H_BP 100
#define H_VD 1280
#define H_FP 18
#define V_PW 2
#define V_BP 8
#define V_VD 800
#define V_FP 6
#define LCD_WIDTH 216
#define LCD_HEIGHT 135
/* Other */
#if defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS)
#define DCLK_POL 1
#else
#define DCLK_POL 0
#endif
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
int dsp_lut[256] ={
0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707,
0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f,
0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717,
0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f,
0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727,
0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f,
0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737,
0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f,
0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747,
0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f,
0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757,
0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f,
0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767,
0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f,
0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777,
0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f,
0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787,
0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f,
0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797,
0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f,
0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7,
0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf,
0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7,
0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf,
0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7,
0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf,
0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7,
0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf,
0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7,
0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef,
0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7,
0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff,
};
#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& ( defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS))
/* scaler Timing */
//1920*1080*60
#define S_OUT_CLK SCALE_RATE(148500000,74250000) //m=16 n=9 no=4
#define S_H_PW 48
#define S_H_BP 98
#define S_H_VD 1280
#define S_H_FP 59
#define S_V_PW 6
#define S_V_BP 25
#define S_V_VD 800
#define S_V_FP 2
#define S_H_ST 495
#define S_V_ST 2
#define S_PLL_CFG_VAL 0x01842016
#define S_FRAC 0xc16c2d
#define S_SCL_VST 0x25
#define S_SCL_HST 0x4ba
#define S_VIF_VST 0x1
#define S_VIF_HST 0xca
//1920*1080*50
#define S1_OUT_CLK SCALE_RATE(148500000,57375000) //m=17 n=11 no=4
#define S1_H_PW 10
#define S1_H_BP 10
#define S1_H_VD 1280
#define S1_H_FP 77
#define S1_V_PW 10
#define S1_V_BP 10
#define S1_V_VD 800
#define S1_V_FP 13
#define S1_H_ST 459
#define S1_V_ST 13
#define S1_PLL_CFG_VAL 0x01c42016
#define S1_FRAC 0x1f9ad4
#define S1_SCL_VST 0x25
#define S1_SCL_HST 0x5ab
#define S1_VIF_VST 0x1
#define S1_VIF_HST 0xca
//1280*720*60
#define S2_OUT_CLK SCALE_RATE(74250000,74250000) //m=32 n=9 no=4
#define S2_H_PW 48
#define S2_H_BP 98
#define S2_H_VD 1280
#define S2_H_FP 59
#define S2_V_PW 6
#define S2_V_BP 25
#define S2_V_VD 800
#define S2_V_FP 2
#define S2_H_ST 495
#define S2_V_ST 5
//bellow are for jettaB
#define S2_PLL_CFG_VAL 0x01822016
#define S2_FRAC 0xc16c2d
#define S2_SCL_VST 0x19
#define S2_SCL_HST 0x483
#define S2_VIF_VST 0x1
#define S2_VIF_HST 0xcf
//1280*720*50
#define S3_OUT_CLK SCALE_RATE(74250000,67500000) // m=34 n=11 no=4
#define S3_H_PW 48
#define S3_H_BP 233
#define S3_H_VD 1280
#define S3_H_FP 59
#define S3_V_PW 6
#define S3_V_BP 25
#define S3_V_VD 800
#define S3_V_FP 2
#define S3_H_ST 540
#define S3_V_ST 3
#define S3_PLL_CFG_VAL 0x01c22016
#define S3_FRAC 0x1f9ad4
#define S3_SCL_VST 0x19
#define S3_SCL_HST 0x569
#define S3_VIF_VST 0x1
#define S3_VIF_HST 0xcf
//720*576*50
#define S4_OUT_CLK SCALE_RATE(27000000,70312500) //m=75 n=4 no=8
#define S4_H_PW 48
#define S4_H_BP 233
#define S4_H_VD 1280
#define S4_H_FP 59
#define S4_V_PW 9
#define S4_V_BP 57
#define S4_V_VD 800
#define S4_V_FP 2
#define S4_H_ST 90
#define S4_V_ST 2
#define S4_PLL_CFG_VAL 0x01412016
#define S4_FRAC 0xa23d09
#define S4_SCL_VST 0x2d
#define S4_SCL_HST 0x33d
#define S4_VIF_VST 0x1
#define S4_VIF_HST 0xc1
//720*480*60
#define S5_OUT_CLK SCALE_RATE(27000000,75000000) //m=100 n=9 no=4
#define S5_H_PW 48
#define S5_H_BP 86
#define S5_H_VD 1280
#define S5_H_FP 16
#define S5_V_PW 9
#define S5_V_BP 35
#define S5_V_VD 800
#define S5_V_FP 30
#define S5_H_ST 476
#define S5_V_ST 12
#define S5_PLL_CFG_VAL 0x01c11013
#define S5_FRAC 0x25325e
#define S5_SCL_VST 0x26
#define S5_SCL_HST 0x2ae
#define S5_VIF_VST 0x1
#define S5_VIF_HST 0xc1
#define S_DCLK_POL 1
static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
{
screen->s_clk_inv = S_DCLK_POL;
screen->s_den_inv = 0;
screen->s_hv_sync_inv = 0;
switch(hdmi_resolution)
{
case HDMI_1920x1080p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S_OUT_CLK;
screen->s_hsync_len = S_H_PW;
screen->s_left_margin = S_H_BP;
screen->s_right_margin = S_H_FP;
screen->s_hsync_len = S_H_PW;
screen->s_upper_margin = S_V_BP;
screen->s_lower_margin = S_V_FP;
screen->s_vsync_len = S_V_PW;
screen->s_hsync_st = S_H_ST;
screen->s_vsync_st = S_V_ST;
//bellow are for JettaB
#if defined(CONFIG_RK616_LVDS)
screen->pll_cfg_val = S_PLL_CFG_VAL;
screen->frac = S_FRAC;
screen->scl_vst = S_SCL_VST;
screen->scl_hst = S_SCL_HST;
screen->vif_vst = S_VIF_VST;
screen->vif_hst = S_VIF_HST;
#endif
break;
case HDMI_1920x1080p_50Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S1_OUT_CLK;
screen->s_hsync_len = S1_H_PW;
screen->s_left_margin = S1_H_BP;
screen->s_right_margin = S1_H_FP;
screen->s_hsync_len = S1_H_PW;
screen->s_upper_margin = S1_V_BP;
screen->s_lower_margin = S1_V_FP;
screen->s_vsync_len = S1_V_PW;
screen->s_hsync_st = S1_H_ST;
screen->s_vsync_st = S1_V_ST;
#if defined(CONFIG_RK616_LVDS)
screen->pll_cfg_val = S1_PLL_CFG_VAL;
screen->frac = S1_FRAC;
screen->scl_vst = S1_SCL_VST;
screen->scl_hst = S1_SCL_HST;
screen->vif_vst = S1_VIF_VST;
screen->vif_hst = S1_VIF_HST;
#endif
break;
case HDMI_1280x720p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S2_OUT_CLK;
screen->s_hsync_len = S2_H_PW;
screen->s_left_margin = S2_H_BP;
screen->s_right_margin = S2_H_FP;
screen->s_hsync_len = S2_H_PW;
screen->s_upper_margin = S2_V_BP;
screen->s_lower_margin = S2_V_FP;
screen->s_vsync_len = S2_V_PW;
screen->s_hsync_st = S2_H_ST;
screen->s_vsync_st = S2_V_ST;
#if defined(CONFIG_RK616_LVDS)
screen->pll_cfg_val = S2_PLL_CFG_VAL;
screen->frac = S2_FRAC;
screen->scl_vst = S2_SCL_VST;
screen->scl_hst = S2_SCL_HST;
screen->vif_vst = S2_VIF_VST;
screen->vif_hst = S2_VIF_HST;
#endif
break;
case HDMI_1280x720p_50Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S3_OUT_CLK;
screen->s_hsync_len = S3_H_PW;
screen->s_left_margin = S3_H_BP;
screen->s_right_margin = S3_H_FP;
screen->s_hsync_len = S3_H_PW;
screen->s_upper_margin = S3_V_BP;
screen->s_lower_margin = S3_V_FP;
screen->s_vsync_len = S3_V_PW;
screen->s_hsync_st = S3_H_ST;
screen->s_vsync_st = S3_V_ST;
#if defined(CONFIG_RK616_LVDS)
screen->pll_cfg_val = S3_PLL_CFG_VAL;
screen->frac = S3_FRAC;
screen->scl_vst = S3_SCL_VST;
screen->scl_hst = S3_SCL_HST;
screen->vif_vst = S3_VIF_VST;
screen->vif_hst = S3_VIF_HST;
#endif
break;
case HDMI_720x576p_50Hz_4_3:
case HDMI_720x576p_50Hz_16_9:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S4_OUT_CLK;
screen->s_hsync_len = S4_H_PW;
screen->s_left_margin = S4_H_BP;
screen->s_right_margin = S4_H_FP;
screen->s_hsync_len = S4_H_PW;
screen->s_upper_margin = S4_V_BP;
screen->s_lower_margin = S4_V_FP;
screen->s_vsync_len = S4_V_PW;
screen->s_hsync_st = S4_H_ST;
screen->s_vsync_st = S4_V_ST;
#if defined(CONFIG_RK616_LVDS)
screen->pll_cfg_val = S4_PLL_CFG_VAL;
screen->frac = S4_FRAC;
screen->scl_vst = S4_SCL_VST;
screen->scl_hst = S4_SCL_HST;
screen->vif_vst = S4_VIF_VST;
screen->vif_hst = S4_VIF_HST;
#endif
break;
case HDMI_720x480p_60Hz_16_9:
case HDMI_720x480p_60Hz_4_3:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S5_OUT_CLK;
screen->s_hsync_len = S5_H_PW;
screen->s_left_margin = S5_H_BP;
screen->s_right_margin = S5_H_FP;
screen->s_hsync_len = S5_H_PW;
screen->s_upper_margin = S5_V_BP;
screen->s_lower_margin = S5_V_FP;
screen->s_vsync_len = S5_V_PW;
screen->s_hsync_st = S5_H_ST;
screen->s_vsync_st = S5_V_ST;
#if defined(CONFIG_RK616_LVDS)
screen->pll_cfg_val = S5_PLL_CFG_VAL;
screen->frac = S5_FRAC;
screen->scl_vst = S5_SCL_VST;
screen->scl_hst = S5_SCL_HST;
screen->vif_vst = S5_VIF_VST;
screen->vif_hst = S5_VIF_HST;
#endif
break;
default :
printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution);
return -1;
break;
}
return 0;
}
#else
#define set_scaler_info NULL
#endif
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->face = OUT_FACE;
screen->type = OUT_TYPE;
#if defined(CONFIG_RK610_LVDS)|| defined(CONFIG_RK616_LVDS)
screen->hw_format = LVDS_FORMAT;
#endif
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = HSYNC_POL;
screen->pin_vsync = VSYNC_POL;
screen->pin_den = DEN_POL;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = SWAP_RG;
screen->swap_gb = SWAP_GB;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
screen->init = NULL;
screen->standby = NULL;
screen->dsp_lut = dsp_lut;
screen->sscreen_get = set_scaler_info;
#if defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS)
screen->sscreen_set = rk610_lcd_scaler_set_param;
#endif
}
size_t get_fb_size(void)
{
size_t size = 0;
#if defined(CONFIG_THREE_FB_BUFFER)
size = ((H_VD)*(V_VD)<<2)* 3; //three buffer
#else
size = ((H_VD)*(V_VD)<<2)<<1; //two buffer
#endif
return ALIGN(size,SZ_1M);
}

302
drivers/video/display/screen/lcd_hdmi_1024x768.c
View File

@@ -1,302 +0,0 @@
#include <linux/delay.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include <linux/rk_fb.h>
#if defined(CONFIG_RK_HDMI)
#include "../../rockchip/hdmi/rk_hdmi.h"
#endif
#ifdef CONFIG_RK610_LVDS
#include "../transmitter/rk610_lcd.h"
#endif
/* Base */
#define OUT_TYPE SCREEN_LVDS
#define LVDS_FORMAT LVDS_8BIT_2
#define OUT_FACE OUT_D888_P666
#define OUT_CLK 65000000
#define LCDC_ACLK 500000000//312000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 10
#define H_BP 100
#define H_VD 1024
#define H_FP 210
#define V_PW 10
#define V_BP 10
#define V_VD 768
#define V_FP 18
#define LCD_WIDTH 202
#define LCD_HEIGHT 152
/* scaler Timing */
//1920*1080*60
#define S_OUT_CLK SCALE_RATE(148500000,66000000) //m=16 n=9 no=4
#define S_H_PW 100
#define S_H_BP 100
#define S_H_VD 1024
#define S_H_FP 151
#define S_V_PW 5
#define S_V_BP 15
#define S_V_VD 768
#define S_V_FP 12
#define S_H_ST 1757
#define S_V_ST 14
//1920*1080*50
#define S1_OUT_CLK SCALE_RATE(148500000,54000000) //m=16 n=11 no=4
#define S1_H_PW 100
#define S1_H_BP 100
#define S1_H_VD 1024
#define S1_H_FP 126
#define S1_V_PW 5
#define S1_V_BP 15
#define S1_V_VD 768
#define S1_V_FP 12
#define S1_H_ST 1757
#define S1_V_ST 14
//1280*720*60
#define S2_OUT_CLK SCALE_RATE(74250000,66000000) //m=32 n=9 no=4
#define S2_H_PW 100
#define S2_H_BP 100
#define S2_H_VD 1024
#define S2_H_FP 151
#define S2_V_PW 5
#define S2_V_BP 15
#define S2_V_VD 768
#define S2_V_FP 12
#define S2_H_ST 0
#define S2_V_ST 12
//1280*720*50
#define S3_OUT_CLK SCALE_RATE(74250000,54000000) // m=32 n=11 no=4
#define S3_H_PW 100
#define S3_H_BP 100
#define S3_H_VD 1024
#define S3_H_FP 151
#define S3_V_PW 5
#define S3_V_BP 15
#define S3_V_VD 768
#define S3_V_FP 12
#define S3_H_ST 0
#define S3_V_ST 12
//720*576*50
#define S4_OUT_CLK SCALE_RATE(27000000,54375000) //m=145 n=9 no=8
#define S4_H_PW 100
#define S4_H_BP 100
#define S4_H_VD 1024
#define S4_H_FP 81
#define S4_V_PW 5
#define S4_V_BP 15
#define S4_V_VD 768
#define S4_V_FP 45
#define S4_H_ST 435
#define S4_V_ST 45
//720*480*60
#define S5_OUT_CLK SCALE_RATE(27000000,72000000) //m=32 n=3 no=4
#define S5_H_PW 100
#define S5_H_BP 100
#define S5_H_VD 1024
#define S5_H_FP 81
#define S5_V_PW 5
#define S5_V_BP 15
#define S5_V_VD 768
#define S5_V_FP 51
#define S5_H_ST 858
#define S5_V_ST 45
#define S_DCLK_POL 0
/* Other */
#define DCLK_POL 0
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#if ( defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) ) || defined(CONFIG_HDMI_DUAL_DISP)
static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
{
screen->s_clk_inv = S_DCLK_POL;
screen->s_den_inv = 0;
screen->s_hv_sync_inv = 0;
switch(hdmi_resolution){
case HDMI_1920x1080p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S_OUT_CLK;
screen->s_hsync_len = S_H_PW;
screen->s_left_margin = S_H_BP;
screen->s_right_margin = S_H_FP;
screen->s_hsync_len = S_H_PW;
screen->s_upper_margin = S_V_BP;
screen->s_lower_margin = S_V_FP;
screen->s_vsync_len = S_V_PW;
screen->s_hsync_st = S_H_ST;
screen->s_vsync_st = S_V_ST;
break;
case HDMI_1920x1080p_50Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S1_OUT_CLK;
screen->s_hsync_len = S1_H_PW;
screen->s_left_margin = S1_H_BP;
screen->s_right_margin = S1_H_FP;
screen->s_hsync_len = S1_H_PW;
screen->s_upper_margin = S1_V_BP;
screen->s_lower_margin = S1_V_FP;
screen->s_vsync_len = S1_V_PW;
screen->s_hsync_st = S1_H_ST;
screen->s_vsync_st = S1_V_ST;
break;
case HDMI_1280x720p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S2_OUT_CLK;
screen->s_hsync_len = S2_H_PW;
screen->s_left_margin = S2_H_BP;
screen->s_right_margin = S2_H_FP;
screen->s_hsync_len = S2_H_PW;
screen->s_upper_margin = S2_V_BP;
screen->s_lower_margin = S2_V_FP;
screen->s_vsync_len = S2_V_PW;
screen->s_hsync_st = S2_H_ST;
screen->s_vsync_st = S2_V_ST;
break;
case HDMI_1280x720p_50Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S3_OUT_CLK;
screen->s_hsync_len = S3_H_PW;
screen->s_left_margin = S3_H_BP;
screen->s_right_margin = S3_H_FP;
screen->s_hsync_len = S3_H_PW;
screen->s_upper_margin = S3_V_BP;
screen->s_lower_margin = S3_V_FP;
screen->s_vsync_len = S3_V_PW;
screen->s_hsync_st = S3_H_ST;
screen->s_vsync_st = S3_V_ST;
break;
case HDMI_720x576p_50Hz_4_3:
case HDMI_720x576p_50Hz_16_9:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S4_OUT_CLK;
screen->s_hsync_len = S4_H_PW;
screen->s_left_margin = S4_H_BP;
screen->s_right_margin = S4_H_FP;
screen->s_hsync_len = S4_H_PW;
screen->s_upper_margin = S4_V_BP;
screen->s_lower_margin = S4_V_FP;
screen->s_vsync_len = S4_V_PW;
screen->s_hsync_st = S4_H_ST;
screen->s_vsync_st = S4_V_ST;
break;
case HDMI_720x480p_60Hz_16_9:
case HDMI_720x480p_60Hz_4_3:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S5_OUT_CLK;
screen->s_hsync_len = S5_H_PW;
screen->s_left_margin = S5_H_BP;
screen->s_right_margin = S5_H_FP;
screen->s_hsync_len = S5_H_PW;
screen->s_upper_margin = S5_V_BP;
screen->s_lower_margin = S5_V_FP;
screen->s_vsync_len = S5_V_PW;
screen->s_hsync_st = S5_H_ST;
screen->s_vsync_st = S5_V_ST;
break;
default :
printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution);
return -1;
break;
}
return 0;
}
#else
static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution){return 0;}
#endif
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
screen->hw_format = LVDS_FORMAT;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = HSYNC_POL;
screen->pin_vsync = VSYNC_POL;
screen->pin_den = DEN_POL;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = SWAP_RG;
screen->swap_gb = SWAP_GB;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
screen->init = NULL;
screen->standby = NULL;
screen->sscreen_get = set_scaler_info;
#ifdef CONFIG_RK610_LVDS
screen->sscreen_set = rk610_lcd_scaler_set_param;
#endif
}
size_t get_fb_size(void)
{
size_t size = 0;
#if defined(CONFIG_THREE_FB_BUFFER)
size = ((H_VD)*(V_VD)<<2)* 3; //three buffer
#else
size = ((H_VD)*(V_VD)<<2)<<1; //two buffer
#endif
return ALIGN(size,SZ_1M);
}

306
drivers/video/display/screen/lcd_hdmi_1280x800.c
View File

@@ -1,306 +0,0 @@
#include <linux/delay.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include <linux/rk_fb.h>
#if defined(CONFIG_RK_HDMI)
#include "../../rockchip/hdmi/rk_hdmi.h"
#endif
#ifdef CONFIG_RK610_LVDS
#include "../transmitter/rk610_lcd.h"
#endif
/* Base */
#define OUT_TYPE SCREEN_LVDS
#define LVDS_FORMAT LVDS_8BIT_2
#define OUT_FACE OUT_D888_P666
#define OUT_CLK 65000000
#define LCDC_ACLK 500000000//312000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 10
#define H_BP 10
#define H_VD 1280
#define H_FP 20
#define V_PW 10
#define V_BP 10
#define V_VD 800
#define V_FP 13
#define LCD_WIDTH 202
#define LCD_HEIGHT 152
/* scaler Timing */
//1920*1080*60
#define S_OUT_CLK SCALE_RATE(148500000,66000000) //m=16 n=9 no=4
#define S_H_PW 10
#define S_H_BP 10
#define S_H_VD 1280
#define S_H_FP 20
#define S_V_PW 10
#define S_V_BP 10
#define S_V_VD 800
#define S_V_FP 13
#define S_H_ST 440
#define S_V_ST 13
//1920*1080*50
#define S1_OUT_CLK SCALE_RATE(148500000,57375000) //m=17 n=11 no=4
#define S1_H_PW 10
#define S1_H_BP 10
#define S1_H_VD 1280
#define S1_H_FP 77
#define S1_V_PW 10
#define S1_V_BP 10
#define S1_V_VD 800
#define S1_V_FP 13
#define S1_H_ST 459
#define S1_V_ST 13
//1280*720*60
#define S2_OUT_CLK SCALE_RATE(74250000,66000000) //m=32 n=9 no=4
#define S2_H_PW 10
#define S2_H_BP 10
#define S2_H_VD 1280
#define S2_H_FP 20
#define S2_V_PW 10
#define S2_V_BP 10
#define S2_V_VD 800
#define S2_V_FP 13
#define S2_H_ST 440
#define S2_V_ST 13
//1280*720*50
#define S3_OUT_CLK SCALE_RATE(74250000,57375000) // m=34 n=11 no=4
#define S3_H_PW 10
#define S3_H_BP 10
#define S3_H_VD 1280
#define S3_H_FP 77
#define S3_V_PW 10
#define S3_V_BP 10
#define S3_V_VD 800
#define S3_V_FP 13
#define S3_H_ST 459
#define S3_V_ST 13
//720*576*50
#define S4_OUT_CLK SCALE_RATE(27000000,63281250) //m=75 n=4 no=8
#define S4_H_PW 10
#define S4_H_BP 10
#define S4_H_VD 1280
#define S4_H_FP 185
#define S4_V_PW 10
#define S4_V_BP 10
#define S4_V_VD 800
#define S4_V_FP 48
#define S4_H_ST 81
#define S4_V_ST 48
//720*480*60
#define S5_OUT_CLK SCALE_RATE(27000000,75000000) //m=100 n=9 no=4
#define S5_H_PW 10
#define S5_H_BP 10
#define S5_H_VD 1280
#define S5_H_FP 130
#define S5_V_PW 10
#define S5_V_BP 10
#define S5_V_VD 800
#define S5_V_FP 54
#define S5_H_ST 476
#define S5_V_ST 48
#define S_DCLK_POL 0
/* Other */
#define DCLK_POL 0
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#if ( defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) ) || defined(CONFIG_HDMI_DUAL_DISP)
static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
{
screen->s_clk_inv = S_DCLK_POL;
screen->s_den_inv = 0;
screen->s_hv_sync_inv = 0;
switch(hdmi_resolution){
case HDMI_1920x1080p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S_OUT_CLK;
screen->s_hsync_len = S_H_PW;
screen->s_left_margin = S_H_BP;
screen->s_right_margin = S_H_FP;
screen->s_hsync_len = S_H_PW;
screen->s_upper_margin = S_V_BP;
screen->s_lower_margin = S_V_FP;
screen->s_vsync_len = S_V_PW;
screen->s_hsync_st = S_H_ST;
screen->s_vsync_st = S_V_ST;
break;
case HDMI_1920x1080p_50Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S1_OUT_CLK;
screen->s_hsync_len = S1_H_PW;
screen->s_left_margin = S1_H_BP;
screen->s_right_margin = S1_H_FP;
screen->s_hsync_len = S1_H_PW;
screen->s_upper_margin = S1_V_BP;
screen->s_lower_margin = S1_V_FP;
screen->s_vsync_len = S1_V_PW;
screen->s_hsync_st = S1_H_ST;
screen->s_vsync_st = S1_V_ST;
break;
case HDMI_1280x720p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S2_OUT_CLK;
screen->s_hsync_len = S2_H_PW;
screen->s_left_margin = S2_H_BP;
screen->s_right_margin = S2_H_FP;
screen->s_hsync_len = S2_H_PW;
screen->s_upper_margin = S2_V_BP;
screen->s_lower_margin = S2_V_FP;
screen->s_vsync_len = S2_V_PW;
screen->s_hsync_st = S2_H_ST;
screen->s_vsync_st = S2_V_ST;
break;
case HDMI_1280x720p_50Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S3_OUT_CLK;
screen->s_hsync_len = S3_H_PW;
screen->s_left_margin = S3_H_BP;
screen->s_right_margin = S3_H_FP;
screen->s_hsync_len = S3_H_PW;
screen->s_upper_margin = S3_V_BP;
screen->s_lower_margin = S3_V_FP;
screen->s_vsync_len = S3_V_PW;
screen->s_hsync_st = S3_H_ST;
screen->s_vsync_st = S3_V_ST;
break;
case HDMI_720x576p_50Hz_4_3:
case HDMI_720x576p_50Hz_16_9:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S4_OUT_CLK;
screen->s_hsync_len = S4_H_PW;
screen->s_left_margin = S4_H_BP;
screen->s_right_margin = S4_H_FP;
screen->s_hsync_len = S4_H_PW;
screen->s_upper_margin = S4_V_BP;
screen->s_lower_margin = S4_V_FP;
screen->s_vsync_len = S4_V_PW;
screen->s_hsync_st = S4_H_ST;
screen->s_vsync_st = S4_V_ST;
break;
case HDMI_720x480p_60Hz_16_9:
case HDMI_720x480p_60Hz_4_3:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S5_OUT_CLK;
screen->s_hsync_len = S5_H_PW;
screen->s_left_margin = S5_H_BP;
screen->s_right_margin = S5_H_FP;
screen->s_hsync_len = S5_H_PW;
screen->s_upper_margin = S5_V_BP;
screen->s_lower_margin = S5_V_FP;
screen->s_vsync_len = S5_V_PW;
screen->s_hsync_st = S5_H_ST;
screen->s_vsync_st = S5_V_ST;
break;
default :
printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution);
return -1;
break;
}
return 0;
}
#else
static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution){return 0;}
#endif
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
screen->hw_format = LVDS_FORMAT;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = HSYNC_POL;
screen->pin_vsync = VSYNC_POL;
screen->pin_den = DEN_POL;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = SWAP_RG;
screen->swap_gb = SWAP_GB;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
screen->init = NULL;
screen->standby = NULL;
screen->sscreen_get = set_scaler_info;
#ifdef CONFIG_RK610_LVDS
screen->sscreen_set = rk610_lcd_scaler_set_param;
#endif
}
size_t get_fb_size(void)
{
size_t size = 0;
#if defined(CONFIG_THREE_FB_BUFFER)
size = ((H_VD)*(V_VD)<<2)* 3; //three buffer
#else
size = ((H_VD)*(V_VD)<<2)<<1; //two buffer
#endif
return ALIGN(size,SZ_1M);
}

345
drivers/video/display/screen/lcd_hdmi_1366x768.c
View File

@@ -1,345 +0,0 @@
#include <linux/delay.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include <linux/rk_fb.h>
#if defined(CONFIG_RK_HDMI)
#include "../../rockchip/hdmi/rk_hdmi.h"
#endif
#ifdef CONFIG_RK610_LVDS
#include "../transmitter/rk610_lcd.h"
#endif
/* Base */
#define OUT_TYPE SCREEN_LVDS
#define OUT_FORMAT LVDS_8BIT_1
#define OUT_FACE OUT_D888_P666
//#define OUT_FACE OUT_P888
#define OUT_CLK 95000000 // 1280x800x1.13x60(hz)
#define LCDC_ACLK 500000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 34
#define H_BP 120
#define H_VD 1366
#define H_FP 80
#define V_PW 8
#define V_BP 50
#define V_VD 768
#define V_FP 12
#define LCD_WIDTH 1366
#define LCD_HEIGHT 768
int dsp_lut[256] ={
0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707,
0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f,
0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717,
0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f,
0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727,
0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f,
0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737,
0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f,
0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747,
0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f,
0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757,
0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f,
0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767,
0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f,
0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777,
0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f,
0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787,
0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f,
0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797,
0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f,
0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7,
0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf,
0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7,
0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf,
0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7,
0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf,
0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7,
0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf,
0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7,
0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef,
0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7,
0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff,
};
/* scaler Timing */
//1920*1080*60
#define S_OUT_CLK SCALE_RATE(148500000,79199997) //m=32 n=15 no=4
#define S_H_PW 34
#define S_H_BP 120
#define S_H_VD 1366
#define S_H_FP 130
#define S_V_PW 8
#define S_V_BP 10
#define S_V_VD 768
#define S_V_FP 13
#define S_H_ST 0
#define S_V_ST 15
//1920*1080*50
#define S1_OUT_CLK SCALE_RATE(148500000,66000000) //m=16 n=9 no=4
#define S1_H_PW 34
#define S1_H_BP 120
#define S1_H_VD 1366
#define S1_H_FP 130
#define S1_V_PW 8
#define S1_V_BP 10
#define S1_V_VD 768
#define S1_V_FP 14
#define S1_H_ST 0
#define S1_V_ST 15
//1280*720p 60HZ
#define S2_OUT_CLK SCALE_RATE(74250000,79199997) //m=64 n=15 no=4
#define S2_H_PW 34
#define S2_H_BP 120
#define S2_H_VD 1366
#define S2_H_FP 130
#define S2_V_PW 8
#define S2_V_BP 10
#define S2_V_VD 768
#define S2_V_FP 13
#define S2_H_ST 0
#define S2_V_ST 8
//1280*720*50
#define S3_OUT_CLK SCALE_RATE(74250000,66000000) // m=16 n=5 no=4
#define S3_H_PW 34
#define S3_H_BP 120
#define S3_H_VD 1366
#define S3_H_FP 130
#define S3_V_PW 8
#define S3_V_BP 10
#define S3_V_VD 768
#define S3_V_FP 14
#define S3_H_ST 0
#define S3_V_ST 8
//720*576*50
//run
#define S4_OUT_CLK SCALE_RATE(27000000,60000000) //m=91 n=9 no=4
#define S4_H_PW 34
#define S4_H_BP 20
#define S4_H_VD 1366
#define S4_H_FP 20
#define S4_V_PW 8
#define S4_V_BP 10
#define S4_V_VD 768
#define S4_V_FP 47
#define S4_H_ST 0
#define S4_V_ST 33
//720*480*60
#define S5_OUT_CLK SCALE_RATE(27000000,72000000) //m=79 n=7 no=4
#define S5_H_PW 34
#define S5_H_BP 20
#define S5_H_VD 1366
#define S5_H_FP 10
#define S5_V_PW 8
#define S5_V_BP 10
#define S5_V_VD 768
#define S5_V_FP 53
#define S5_H_ST 0
#define S5_V_ST 29
#define S_DCLK_POL 1
/* Other */
#define DCLK_POL 1
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#if ( defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) ) || defined(CONFIG_HDMI_DUAL_DISP)
static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
{
screen->s_clk_inv = S_DCLK_POL;
screen->s_den_inv = 0;
screen->s_hv_sync_inv = 0;
switch(hdmi_resolution){
case HDMI_1920x1080p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S_OUT_CLK;
screen->s_hsync_len = S_H_PW;
screen->s_left_margin = S_H_BP;
screen->s_right_margin = S_H_FP;
screen->s_hsync_len = S_H_PW;
screen->s_upper_margin = S_V_BP;
screen->s_lower_margin = S_V_FP;
screen->s_vsync_len = S_V_PW;
screen->s_hsync_st = S_H_ST;
screen->s_vsync_st = S_V_ST;
break;
case HDMI_1920x1080p_50Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S1_OUT_CLK;
screen->s_hsync_len = S1_H_PW;
screen->s_left_margin = S1_H_BP;
screen->s_right_margin = S1_H_FP;
screen->s_hsync_len = S1_H_PW;
screen->s_upper_margin = S1_V_BP;
screen->s_lower_margin = S1_V_FP;
screen->s_vsync_len = S1_V_PW;
screen->s_hsync_st = S1_H_ST;
screen->s_vsync_st = S1_V_ST;
break;
case HDMI_1280x720p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S2_OUT_CLK;
screen->s_hsync_len = S2_H_PW;
screen->s_left_margin = S2_H_BP;
screen->s_right_margin = S2_H_FP;
screen->s_hsync_len = S2_H_PW;
screen->s_upper_margin = S2_V_BP;
screen->s_lower_margin = S2_V_FP;
screen->s_vsync_len = S2_V_PW;
screen->s_hsync_st = S2_H_ST;
screen->s_vsync_st = S2_V_ST;
break;
case HDMI_1280x720p_50Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S3_OUT_CLK;
screen->s_hsync_len = S3_H_PW;
screen->s_left_margin = S3_H_BP;
screen->s_right_margin = S3_H_FP;
screen->s_hsync_len = S3_H_PW;
screen->s_upper_margin = S3_V_BP;
screen->s_lower_margin = S3_V_FP;
screen->s_vsync_len = S3_V_PW;
screen->s_hsync_st = S3_H_ST;
screen->s_vsync_st = S3_V_ST;
break;
case HDMI_720x576p_50Hz_4_3:
case HDMI_720x576p_50Hz_16_9:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S4_OUT_CLK;
screen->s_hsync_len = S4_H_PW;
screen->s_left_margin = S4_H_BP;
screen->s_right_margin = S4_H_FP;
screen->s_hsync_len = S4_H_PW;
screen->s_upper_margin = S4_V_BP;
screen->s_lower_margin = S4_V_FP;
screen->s_vsync_len = S4_V_PW;
screen->s_hsync_st = S4_H_ST;
screen->s_vsync_st = S4_V_ST;
break;
case HDMI_720x480p_60Hz_16_9:
case HDMI_720x480p_60Hz_4_3:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S5_OUT_CLK;
screen->s_hsync_len = S5_H_PW;
screen->s_left_margin = S5_H_BP;
screen->s_right_margin = S5_H_FP;
screen->s_hsync_len = S5_H_PW;
screen->s_upper_margin = S5_V_BP;
screen->s_lower_margin = S5_V_FP;
screen->s_vsync_len = S5_V_PW;
screen->s_hsync_st = S5_H_ST;
screen->s_vsync_st = S5_V_ST;
break;
default :
printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution);
return -1;
break;
}
return 0;
}
#else
static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution){return 0;}
#endif
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->face = OUT_FACE;
screen->type = OUT_TYPE;
screen->hw_format = OUT_FORMAT;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = HSYNC_POL;
screen->pin_vsync = VSYNC_POL;
screen->pin_den = DEN_POL;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = SWAP_RG;
screen->swap_gb = SWAP_GB;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
screen->init = NULL;
screen->standby = NULL;
//screen->dsp_lut = dsp_lut;
screen->sscreen_get = set_scaler_info;
#ifdef CONFIG_RK610_LVDS
screen->sscreen_set = rk610_lcd_scaler_set_param;
#endif
}
size_t get_fb_size(void)
{
size_t size = 0;
#if defined(CONFIG_THREE_FB_BUFFER)
size = ((H_VD)*(V_VD)<<2)* 3; //three buffer
#else
size = ((H_VD)*(V_VD)<<2)<<1; //two buffer
#endif
return ALIGN(size,SZ_1M);
}

353
drivers/video/display/screen/lcd_hdmi_rk3168m_b101ew05.c
View File

@@ -1,353 +0,0 @@
#include <linux/delay.h>
#include <linux/rk_fb.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#if defined(CONFIG_RK_HDMI)
#include "../../rockchip/hdmi/rk_hdmi.h"
#endif
#ifdef CONFIG_RK610_LVDS
#include "../transmitter/rk610_lcd.h"
#endif
/* Base */
#ifdef CONFIG_RK610_LVDS
#define OUT_TYPE SCREEN_LVDS
#define OUT_FORMAT LVDS_8BIT_2
#else
#define OUT_TYPE SCREEN_RGB
#endif
#define OUT_FACE OUT_D888_P666
#define OUT_CLK 71000000
#define LCDC_ACLK 300000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 10
#define H_BP 100
#define H_VD 1280
#define H_FP 18
#define V_PW 2
#define V_BP 8
#define V_VD 800
#define V_FP 6
#define LCD_WIDTH 216
#define LCD_HEIGHT 135
/* Other */
#ifdef CONFIG_RK610_LVDS
#define DCLK_POL 1
#else
#define DCLK_POL 0
#endif
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
int dsp_lut[256] ={
0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707,
0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f,
0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717,
0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f,
0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727,
0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f,
0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737,
0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f,
0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747,
0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f,
0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757,
0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f,
0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767,
0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f,
0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777,
0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f,
0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787,
0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f,
0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797,
0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f,
0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7,
0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf,
0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7,
0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf,
0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7,
0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf,
0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7,
0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf,
0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7,
0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef,
0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7,
0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff,
};
#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS)
/* scaler Timing */
//1920*1080*60
#define S_OUT_CLK SCALE_RATE(148500000,74250000) //m=16 n=9 no=4
#define S_H_PW 48
#define S_H_BP 98
#define S_H_VD 1280
#define S_H_FP 59
#define S_V_PW 6
#define S_V_BP 25
#define S_V_VD 800
#define S_V_FP 2
#define S_H_ST 0
#define S_V_ST 13
//1920*1080*50
#define S1_OUT_CLK SCALE_RATE(148500000,57375000) //m=17 n=11 no=4
#define S1_H_PW 10
#define S1_H_BP 10
#define S1_H_VD 1280
#define S1_H_FP 77
#define S1_V_PW 10
#define S1_V_BP 10
#define S1_V_VD 800
#define S1_V_FP 13
#define S1_H_ST 0
#define S1_V_ST 13
//1280*720*60
#define S2_OUT_CLK SCALE_RATE(74250000,74250000) //m=32 n=9 no=4
#define S2_H_PW 48
#define S2_H_BP 98
#define S2_H_VD 1280
#define S2_H_FP 59
#define S2_V_PW 6
#define S2_V_BP 5
#define S2_V_VD 800
#define S2_V_FP 2
#define S2_H_ST 0
#define S2_V_ST 15
//1280*720*50
#define S3_OUT_CLK SCALE_RATE(74250000,67500000) // m=34 n=11 no=4
#define S3_H_PW 48
#define S3_H_BP 233
#define S3_H_VD 1280
#define S3_H_FP 59
#define S3_V_PW 6
#define S3_V_BP 5
#define S3_V_VD 800
#define S3_V_FP 2
#define S3_H_ST 0
#define S3_V_ST 15
//720*576*50
#define S4_OUT_CLK SCALE_RATE(27000000,70312500) //m=75 n=4 no=8
#define S4_H_PW 48
#define S4_H_BP 233
#define S4_H_VD 1280
#define S4_H_FP 59
#define S4_V_PW 9
#define S4_V_BP 57
#define S4_V_VD 800
#define S4_V_FP 2
#define S4_H_ST 90
#define S4_V_ST 2
//720*480*60
#define S5_OUT_CLK SCALE_RATE(27000000,75000000) //m=100 n=9 no=4
#define S5_H_PW 48
#define S5_H_BP 86
#define S5_H_VD 1280
#define S5_H_FP 16
#define S5_V_PW 9
#define S5_V_BP 35
#define S5_V_VD 800
#define S5_V_FP 30
#define S5_H_ST 476
#define S5_V_ST 12
#define S_DCLK_POL 1
static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
{
screen->s_clk_inv = S_DCLK_POL;
screen->s_den_inv = 0;
screen->s_hv_sync_inv = 0;
switch(hdmi_resolution){
case HDMI_1920x1080p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S_OUT_CLK;
screen->s_hsync_len = S_H_PW;
screen->s_left_margin = S_H_BP;
screen->s_right_margin = S_H_FP;
screen->s_hsync_len = S_H_PW;
screen->s_upper_margin = S_V_BP;
screen->s_lower_margin = S_V_FP;
screen->s_vsync_len = S_V_PW;
screen->s_hsync_st = S_H_ST;
screen->s_vsync_st = S_V_ST;
break;
case HDMI_1920x1080p_50Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S1_OUT_CLK;
screen->s_hsync_len = S1_H_PW;
screen->s_left_margin = S1_H_BP;
screen->s_right_margin = S1_H_FP;
screen->s_hsync_len = S1_H_PW;
screen->s_upper_margin = S1_V_BP;
screen->s_lower_margin = S1_V_FP;
screen->s_vsync_len = S1_V_PW;
screen->s_hsync_st = S1_H_ST;
screen->s_vsync_st = S1_V_ST;
break;
case HDMI_1280x720p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S2_OUT_CLK;
screen->s_hsync_len = S2_H_PW;
screen->s_left_margin = S2_H_BP;
screen->s_right_margin = S2_H_FP;
screen->s_hsync_len = S2_H_PW;
screen->s_upper_margin = S2_V_BP;
screen->s_lower_margin = S2_V_FP;
screen->s_vsync_len = S2_V_PW;
screen->s_hsync_st = S2_H_ST;
screen->s_vsync_st = S2_V_ST;
break;
case HDMI_1280x720p_50Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S3_OUT_CLK;
screen->s_hsync_len = S3_H_PW;
screen->s_left_margin = S3_H_BP;
screen->s_right_margin = S3_H_FP;
screen->s_hsync_len = S3_H_PW;
screen->s_upper_margin = S3_V_BP;
screen->s_lower_margin = S3_V_FP;
screen->s_vsync_len = S3_V_PW;
screen->s_hsync_st = S3_H_ST;
screen->s_vsync_st = S3_V_ST;
break;
case HDMI_720x576p_50Hz_4_3:
case HDMI_720x576p_50Hz_16_9:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S4_OUT_CLK;
screen->s_hsync_len = S4_H_PW;
screen->s_left_margin = S4_H_BP;
screen->s_right_margin = S4_H_FP;
screen->s_hsync_len = S4_H_PW;
screen->s_upper_margin = S4_V_BP;
screen->s_lower_margin = S4_V_FP;
screen->s_vsync_len = S4_V_PW;
screen->s_hsync_st = S4_H_ST;
screen->s_vsync_st = S4_V_ST;
break;
case HDMI_720x480p_60Hz_16_9:
case HDMI_720x480p_60Hz_4_3:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S5_OUT_CLK;
screen->s_hsync_len = S5_H_PW;
screen->s_left_margin = S5_H_BP;
screen->s_right_margin = S5_H_FP;
screen->s_hsync_len = S5_H_PW;
screen->s_upper_margin = S5_V_BP;
screen->s_lower_margin = S5_V_FP;
screen->s_vsync_len = S5_V_PW;
screen->s_hsync_st = S5_H_ST;
screen->s_vsync_st = S5_V_ST;
break;
default :
printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution);
return -1;
break;
}
return 0;
}
#else
#define set_scaler_info NULL
#endif
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->face = OUT_FACE;
screen->type = OUT_TYPE;
#ifdef CONFIG_RK610_LVDS
screen->hw_format = OUT_FORMAT;
#endif
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = HSYNC_POL;
screen->pin_vsync = VSYNC_POL;
screen->pin_den = DEN_POL;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = SWAP_RG;
screen->swap_gb = SWAP_GB;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
screen->init = NULL;
screen->standby = NULL;
screen->dsp_lut = dsp_lut;
screen->sscreen_get = set_scaler_info;
#ifdef CONFIG_RK610_LVDS
screen->sscreen_set = rk610_lcd_scaler_set_param;
#endif
}
size_t get_fb_size(void)
{
size_t size = 0;
#if defined(CONFIG_THREE_FB_BUFFER)
size = ((H_VD)*(V_VD)<<2)* 3; //three buffer
#else
size = ((H_VD)*(V_VD)<<2)<<1; //two buffer
#endif
return ALIGN(size,SZ_1M);
}

115
drivers/video/display/screen/lcd_hj101na.c
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@@ -1,115 +0,0 @@
/*
* This Lcd Driver is for BYD 5' LCD BM800480-8545FTGE.
* written by Michael Lin, 2010-06-18
*/
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include "screen.h"
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P888
#define OUT_CLK 71000000
#define LCDC_ACLK 300000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 10
#define H_BP 160
#define H_VD 1280
#define H_FP 16
#define V_PW 3
#define V_BP 23
#define V_VD 800
#define V_FP 12
/* Other */
#define DCLK_POL 0
#define SWAP_RB 0
#define LCD_WIDTH 216 //need modify
#define LCD_HEIGHT 135
static struct rk29lcd_info *gLcd_info = NULL;
#define DRVDelayUs(i) udelay(i*2)
static int init(void);
static int standby(u8 enable);
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
/*screen->init = init;*/
screen->init = NULL;
screen->standby = standby;
}
size_t get_fb_size(void)
{
size_t size = 0;
#if defined(CONFIG_THREE_FB_BUFFER)
size = ((H_VD)*(V_VD)<<2)* 3; //three buffer
#else
size = ((H_VD)*(V_VD)<<2)<<1; //two buffer
#endif
return ALIGN(size,SZ_1M);
}
static int standby(u8 enable)
{
printk(KERN_INFO "byd1024x600 lcd standby, enable=%d\n", enable);
if (enable)
{
//rockchip_mux_api_set(LED_CON_IOMUX_PINNAME, LED_CON_IOMUX_PINDIR);
//GPIOSetPinDirection(LED_CON_IOPIN,GPIO_OUT);
//GPIOSetPinLevel(LED_CON_IOPIN,GPIO_HIGH);
// gpio_set_value(LCD_DISP_ON_IOPIN, GPIO_LOW);
}
else
{
//rockchip_mux_api_set(LED_CON_IOMUX_PINNAME, 1);
// gpio_set_value(LCD_DISP_ON_IOPIN, GPIO_HIGH);
}
return 0;
}

0
drivers/video/display/screen/lcd_hsd100pxn.c Executable file → Normal file
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76
drivers/video/display/screen/lcd_hv070wsa.c
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@@ -1,76 +0,0 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include "screen.h"
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P888
#define OUT_CLK 50000000
#define LCDC_ACLK 500000000//312000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 100
#define H_BP 100
#define H_VD 1024
#define H_FP 120
#define V_PW 10
#define V_BP 10
#define V_VD 600
#define V_FP 15
#define LCD_WIDTH 202
#define LCD_HEIGHT 152
/* Other */
#define DCLK_POL 0
#define SWAP_RB 0
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
screen->init = NULL;
screen->standby = NULL;
}

0
drivers/video/display/screen/lcd_nt35510.c Executable file → Normal file
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0
drivers/video/display/screen/lcd_null.c Executable file → Normal file
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235
drivers/video/display/screen/lcd_td043mgea1.c
View File

@@ -1,235 +0,0 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include "screen.h"
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P888
#define OUT_CLK 27000000
#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 10
#define H_BP 206
#define H_VD 800
#define H_FP 40
#define V_PW 10
#define V_BP 25
#define V_VD 480
#define V_FP 10
#define LCD_WIDTH 800 //need modify
#define LCD_HEIGHT 480
/* Other */
#define DCLK_POL 0
#define SWAP_RB 0
#define TXD_PORT gLcd_info->txd_pin
#define CLK_PORT gLcd_info->clk_pin
#define CS_PORT gLcd_info->cs_pin
#if 0
#define CS_OUT() gpio_direction_output(CS_PORT, 0)
#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH)
#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH)
#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 0)
#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH)
#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW)
#endif
static struct rk29lcd_info *gLcd_info = NULL;
int init(void);
int standby(u8 enable);
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
screen->init = init;
screen->standby = standby;
if(lcd_info)
gLcd_info = lcd_info;
}
#if 0
void spi_screenreg_set(u32 Addr, u32 Data)
{
#define DRVDelayUs(i) udelay(i*2)
u32 i;
TXD_OUT();
CLK_OUT();
CS_OUT();
DRVDelayUs(2);
DRVDelayUs(2);
CS_SET();
TXD_SET();
CLK_SET();
DRVDelayUs(2);
CS_CLR();
for(i = 0; i < 6; i++) //reg
{
if(Addr &(1<<(5-i)))
TXD_SET();
else
TXD_CLR();
// \u6a21\u62dfCLK
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
TXD_CLR(); //write
// \u6a21\u62dfCLK
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
TXD_SET(); //highz
// \u6a21\u62dfCLK
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
for(i = 0; i < 8; i++) //data
{
if(Data &(1<<(7-i)))
TXD_SET();
else
TXD_CLR();
// \u6a21\u62dfCLK
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
CS_SET();
CLK_CLR();
TXD_CLR();
DRVDelayUs(2);
}
#endif
int init(void)
{
if(gLcd_info)
gLcd_info->io_init();
#if 0
spi_screenreg_set(0x02, 0x07);
spi_screenreg_set(0x03, 0x5f);
spi_screenreg_set(0x04, 0x17);
spi_screenreg_set(0x05, 0x20);
spi_screenreg_set(0x06, 0x08);
spi_screenreg_set(0x07, 0x20);
spi_screenreg_set(0x08, 0x20);
spi_screenreg_set(0x09, 0x20);
spi_screenreg_set(0x0a, 0x20);
spi_screenreg_set(0x0b, 0x22);
spi_screenreg_set(0x0c, 0x22);
spi_screenreg_set(0x0d, 0x22);
spi_screenreg_set(0x0e, 0x10);
spi_screenreg_set(0x0f, 0x10);
spi_screenreg_set(0x10, 0x10);
spi_screenreg_set(0x11, 0x15);
spi_screenreg_set(0x12, 0xAA);
spi_screenreg_set(0x13, 0xFF);
spi_screenreg_set(0x14, 0xb0);
spi_screenreg_set(0x15, 0x8e);
spi_screenreg_set(0x16, 0xd6);
spi_screenreg_set(0x17, 0xfe);
spi_screenreg_set(0x18, 0x28);
spi_screenreg_set(0x19, 0x52);
spi_screenreg_set(0x1A, 0x7c);
spi_screenreg_set(0x1B, 0xe9);
spi_screenreg_set(0x1C, 0x42);
spi_screenreg_set(0x1D, 0x88);
spi_screenreg_set(0x1E, 0xb8);
spi_screenreg_set(0x1F, 0xFF);
spi_screenreg_set(0x20, 0xF0);
spi_screenreg_set(0x21, 0xF0);
spi_screenreg_set(0x22, 0x09);
#endif
if(gLcd_info)
gLcd_info->io_deinit();
return 0;
}
int standby(u8 enable)
{
if(gLcd_info)
gLcd_info->io_init();
#if 0
if(enable) {
spi_screenreg_set(0x03, 0xde);
} else {
spi_screenreg_set(0x03, 0x5f);
}
#endif
if(gLcd_info)
gLcd_info->io_deinit();
return 0;
}

0
drivers/video/display/screen/screen.h Executable file → Normal file
View File

5
drivers/video/rockchip/Kconfig
View File

@@ -58,6 +58,9 @@ config THREE_FB_BUFFER
source "drivers/video/rockchip/lcdc/Kconfig"
source "drivers/video/rockchip/screen/Kconfig"
source "drivers/video/rockchip/transmitter/Kconfig"
source "drivers/video/rockchip/hdmi/Kconfig"
source "drivers/video/rockchip/tve/Kconfig"
source "drivers/video/rockchip/rga/Kconfig"
source "drivers/video/rockchip/lvds/Kconfig"

4
drivers/video/rockchip/Makefile
View File

@@ -1,4 +1,4 @@
obj-$(CONFIG_FB_ROCKCHIP) += rk_fb.o rkfb_sysfs.o lcdc/
obj-$(CONFIG_FB_ROCKCHIP) += rk_fb.o rkfb_sysfs.o lcdc/ screen/
obj-$(CONFIG_RK_TRSM) += transmitter/
obj-$(CONFIG_RGA_RK30) += rga/
obj-$(CONFIG_RK_HDMI) += hdmi/
obj-$(CONFIG_RK_LVDS) += lvds/

2
drivers/video/rockchip/lvds/Kconfig
View File

@@ -1,2 +0,0 @@
config RK_LVDS
bool "RK_LVDS support"

6
drivers/video/rockchip/lvds/Makefile
View File

@@ -1,6 +0,0 @@
#
# Makefile for LVDS linux kernel module.
#
obj-$(CONFIG_RK_LVDS) += rk_lvds.o

4
drivers/video/rockchip/screen/.gitignore vendored Normal file
View File

@@ -0,0 +1,4 @@
#
# Generated files
#
*lcd.h

149
drivers/video/rockchip/screen/Kconfig Normal file
View File

@@ -0,0 +1,149 @@
choice
depends on FB_ROCKCHIP
prompt "LCD Panel Select"
config LCD_NULL
bool "NULL"
config LCD_RK2928
bool "RK2928 LCD"
depends on MACH_RK2928
config LCD_LG_LP097X02
bool "RGB LCD_LG_LP097X02 1024X768"
config LCD_TD043MGEA1
bool "RGB TD043MGEA1"
config LCD_HX8357
bool "RGB HX8357"
config LCD_TJ048NC01CA
bool "RGB TJ048NC01CA"
config LCD_HL070VM4AU
bool "RGB_HL070VM4AU"
config LCD_HSD070IDW1
bool "RGB Hannstar800x480"
config LCD_RGB_TFT480800_25_E
bool "RGB TFT480800_25_E"
config LCD_HSD100PXN
bool "RGB Hannstar HSD100PXN(1024X768)"
config LCD_BYD8688FTGF
bool "RGB BYD 1024X600 8688FTGF"
config LCD_B101AW06
bool "RGB Hannstar B101AW06(1024X600)"
config LCD_RGB_TFT480800_25_E
bool "RGB TFT480800_25_E(480X800)"
config LCD_LS035Y8DX02A
bool "RGB LS035Y8DX02A(480X800)"
config LCD_LS035Y8DX04A
bool "RGB LS035Y8DX04A(480X800)"
config LCD_HSD100PXN_FOR_TDW851
bool "RGB Hannstar HSD100PXN(800X480)"
config LCD_CPTCLAA038LA31XE
bool "RGB LCD_CPTCLAA038LA31XE(480X800)"
config LCD_A060SE02
bool "MCU A060SE02"
config LCD_S1D13521
bool "MCU S1D13521"
config LCD_NT35582
bool "MCU NT35582"
config LCD_NT35580
bool "MCU NT35580"
config LCD_IPS1P5680_V1_E
bool "MCU IPS1P5680_V1_E"
config LCD_MCU_TFT480800_25_E
bool "MCU TFT480800_25_E"
config LCD_NT35510
bool "RGB lcd_nt35510"
config LCD_ILI9803_CPT4_3
bool "RGB lcd_ILI9803_CPT4_3"
config LCD_IPS1P5680_V1_E
bool "MCU IPS1P5680_V1_E"
config LCD_MCU_TFT480800_25_E
bool "MCU TFT480800_25_E"
config LCD_AT070TNA2
bool "RGB AT070TNA2"
config LCD_AT070TN93
bool "RGB AT070TN93"
config LCD_TX23D88VM
bool "HITACHI LVDS TX23D88VM (1200x800)"
config LCD_A050VL01
bool "RGB A050VL01"
config LCD_B101EW05
bool "RGB lcd panel B101EW05"
config LCD_RK3168M_B101EW05
bool "RGB lcd panel LCD_RK3168M_B101EW05"
config LCD_HJ050NA_06A
bool "RGB lcd panel HJ050NA-06A"
config LCD_HDMI_1366x768
depends on MFD_RK610
bool "RK610 LCD_HDMI_1366X768"
---help---
if support RK610, this setting can support dual screen output
config LCD_HDMI_1280x800
depends on MFD_RK610
bool "RGB Hannstar LCD_HDMI_1280X800"
---help---
if support RK610, this setting can support dual screen output
config LCD_HDMI_1024x768
depends on MFD_RK610
bool "RGB Hannstar LCD_HDMI_1024X768"
---help---
if support RK610, this setting can support dual screen output
config LCD_HSD07PFW1
depends on MFD_RK610
bool "RGB Hannstar LCD_HDMI_1024X600"
config LCD_HDMI_800x480
depends on MFD_RK610
bool "RGB Hannstar LCD_HDMI_800x480"
---help---
if support RK610, this setting can support dual screen output
config LCD_HV070WSA100
bool "HV070WSA-100 1024X600"
config LCD_COMMON
bool "LCD COMMON"
config LCD_RK3168_AUO_A080SN03
bool "RK3168 auo panel 800x480"
config LCD_RK2928_A720
bool "RK2928 A720 panel 800x480"
config LCD_RK2926_V86
bool "RK2926 v86 panel 800x480"
config LCD_RK3168_86V
bool "RK3168 86v panel 800x480"
config LCD_HJ080NA
bool "HJ080NA_4J 1024X768"
config LCD_HJ101NA
bool "HJ101NA_4J 1280X800"
config LCD_AUTO
bool "auto select lcd"
config LCD_HSD07PFW1
depends on MFD_RK610
bool "RGB lcd panel HSD07PFW1"
config LCD_I30_800X480
bool "lcd I30"
config LCD_TL5001_MIPI
bool "TL5001 720X1280"
config LCD_LP097QX1
bool "Display Port screen LP097QX1"
config LCD_DS1006H
bool "Lvds screen for ds1006h(RK3168)"
config LCD_B101UANO_1920x1200
bool "Lvds screen B101UANO for u30gt2"
config LCD_E242868_1024X600
bool "RK3168 86v RGB 1024*600 "
config LCD_WY_800X480
bool "lcd for 760"
config LCD_HH070D_LVDS
bool "lcd lvds for 760"
endchoice

85
drivers/video/rockchip/screen/Makefile Normal file
View File

@@ -0,0 +1,85 @@
obj-$(CONFIG_LCD_NULL) += lcd_null.o
obj-$(CONFIG_LCD_RK2928) += lcd_rk2928.o
obj-$(CONFIG_LCD_TD043MGEA1) += lcd_td043mgea1.o
obj-$(CONFIG_LCD_HSD070IDW1) += lcd_hsd800x480.o
obj-$(CONFIG_LCD_HL070VM4AU) += lcd_hl070vm4.o
obj-$(CONFIG_LCD_BYD8688FTGF) += lcd_byd1024x600.o
obj-$(CONFIG_LCD_LG_LP097X02)+= lcd_LG_LP097X02.o
obj-$(CONFIG_LCD_TJ048NC01CA) += lcd_tj048nc01ca.o
obj-$(CONFIG_LCD_A060SE02) += lcd_a060se02.o
obj-$(CONFIG_LCD_S1D13521) += lcd_s1d13521.o
obj-$(CONFIG_LCD_NT35582) += lcd_nt35582.o
obj-$(CONFIG_LCD_NT35580) += lcd_nt35580.o
obj-$(CONFIG_LCD_IPS1P5680_V1_E) += lcd_ips1p5680_v1_e.o
obj-$(CONFIG_LCD_RGB_TFT480800_25_E) += lcd_rgb_tft480800_25_e.o
obj-$(CONFIG_LCD_MCU_TFT480800_25_E) += lcd_mcu_tft480800_25_e.o
obj-$(CONFIG_LCD_LS035Y8DX02A) += lcd_ls035y8dx02a.o
obj-$(CONFIG_LCD_LS035Y8DX04A) += lcd_ls035y8dx04a.o
obj-$(CONFIG_LCD_CPTCLAA038LA31XE) += lcd_CPTclaa038la31xe.o
obj-$(CONFIG_LCD_HX8357) += lcd_hx8357.o
obj-$(CONFIG_LCD_HSD100PXN) += lcd_hsd100pxn.o
obj-$(CONFIG_LCD_HDMI_1366x768) += lcd_hdmi_1366x768.o
obj-$(CONFIG_LCD_HDMI_1280x800) += lcd_hdmi_1280x800.o
obj-$(CONFIG_LCD_HDMI_1024x768) += lcd_hdmi_1024x768.o
obj-$(CONFIG_LCD_HDMI_800x480) += lcd_hdmi_800x480.o
obj-$(CONFIG_LCD_B101AW06) += lcd_B101AW06.o
obj-$(CONFIG_LCD_NT35510) += lcd_nt35510.o
obj-$(CONFIG_LCD_ILI9803_CPT4_3) += lcd_ili9803_cpt4_3.o
obj-$(CONFIG_LCD_RGB_TFT480800_25_E) += lcd_rgb_tft480800_25_e.o
obj-$(CONFIG_LCD_LS035Y8DX02A) += lcd_ls035y8dx02a.o
obj-$(CONFIG_LCD_IPS1P5680_V1_E) += lcd_ips1p5680_v1_e.o
obj-$(CONFIG_LCD_MCU_TFT480800_25_E) += lcd_mcu_tft480800_25_e.o
obj-$(CONFIG_LCD_AT070TNA2) += lcd_AT070TNA2.o
obj-$(CONFIG_LCD_TX23D88VM) += lcd_tx23d88vm.o
obj-$(CONFIG_LCD_AT070TN93) += lcd_at070tn93.o
obj-$(CONFIG_LCD_A050VL01) += lcd_A050VL01.o
obj-$(CONFIG_LCD_B101EW05) += lcd_b101ew05.o
obj-$(CONFIG_LCD_RK3168M_B101EW05) += lcd_hdmi_rk3168m_b101ew05.o
obj-$(CONFIG_LCD_HJ050NA_06A) += lcd_hj050na_06a.o
obj-$(CONFIG_LCD_HSD100PXN_FOR_TDW851) += lcd_hsd100pxn_for_tdw851.o
obj-$(CONFIG_LCD_HV070WSA100) += lcd_hv070wsa.o
obj-$(CONFIG_LCD_COMMON) += lcd_common.o
obj-$(CONFIG_LCD_RK2928_A720) += lcd_YQ70CPT9160.o
obj-$(CONFIG_LCD_RK3168_AUO_A080SN03) += lcd_AUO_A080SN03.o
obj-$(CONFIG_LCD_RK2926_V86) += lcd_YQ70CPT9160_v86.o
obj-$(CONFIG_LCD_RK3168_86V) += lcd_YQ70CPT9160_rk3168_86v.o
obj-$(CONFIG_LCD_HSD07PFW1) += lcd_hdmi_1024x600.o
obj-$(CONFIG_LCD_HJ080NA) += lcd_hj080na.o
obj-$(CONFIG_LCD_HJ101NA) += lcd_hj101na.o
obj-$(CONFIG_LCD_AUTO) += lcd_auto.o
obj-$(CONFIG_LCD_I30_800X480) += lcd_I30_800x480.o
obj-$(CONFIG_LCD_TL5001_MIPI) += lcd_tl5001_mipi.o
obj-$(CONFIG_LCD_LP097QX1) += lcd_LP097QX1.o
obj-$(CONFIG_LCD_DS1006H) += lcd_ds1006h.o
obj-$(CONFIG_LCD_B101UANO_1920x1200) += lcd_b101uano_1920x1200.o
obj-$(CONFIG_LCD_E242868_1024X600) += lcd_E242868_rk3168_86v.o
obj-$(CONFIG_LCD_WY_800X480) += lcd_wy_800x480.o
obj-$(CONFIG_LCD_HH070D_LVDS) += lcd_hh070d_lvds.o
obj-$(CONFIG_LCD_MQ0801D) += lcd_mq0801d.o
quiet_cmd_gen = GEN $@
cmd_gen = cp -a $< $@
lcd-obj := $(filter lcd_%.o,$(obj-y))
lcd-cfile := $(patsubst %.o,%.c,$(lcd-obj))
lcd-cpath := $(src)/$(lcd-cfile)
obj-y := $(filter-out $(lcd-obj),$(obj-y))
$(obj)/lcd.h: $(lcd-cpath) FORCE
$(call if_changed,gen)
$(obj)/rk_screen.o: $(obj)/lcd.h
obj-y += rk_screen.o
clean-files := lcd.h

0
drivers/video/display/screen/lcd_AT070TNA2.c → drivers/video/rockchip/screen/lcd_AT070TNA2.c
View File

42
drivers/video/rockchip/screen/lcd_AUO_A080SN03.c Normal file
View File

@@ -0,0 +1,42 @@
/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */
#ifndef __LCD_AUO__
#define __LCD_AUO__
/* Base */
#define SCREEN_TYPE SCREEN_RGB
#define LVDS_FORMAT LVDS_8BIT_1
#define OUT_FACE OUT_P888//OUT_P666
#define DCLK 40000000
#define LCDC_ACLK 500000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 1//30//48 //10
#define H_BP 46//10//40 //100
#define H_VD 800 //1024
#define H_FP 210// //210
#define V_PW 3// 2// 3//13//10
#define V_BP 23// 18 // 23//10// //10
#define V_VD 600//480 //768
#define V_FP 2// 8// 12//22 //18
/* Other */
#define DCLK_POL 1
#define SWAP_RB 0
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#define LCD_WIDTH 162//154 //need modify
#define LCD_HEIGHT 121//85
#endif

0
drivers/video/display/screen/lcd_B101AW06.c → drivers/video/rockchip/screen/lcd_B101AW06.c Executable file → Normal file
View File

0
drivers/video/display/screen/lcd_CPTclaa038la31xe.c → drivers/video/rockchip/screen/lcd_CPTclaa038la31xe.c Executable file → Normal file
View File

34
drivers/video/rockchip/screen/lcd_E242868_rk3168_86v.c Normal file
View File

@@ -0,0 +1,34 @@
#ifndef __LCD_E242868__
#define __LCD_E242868__
/* Base */
#define SCREEN_TYPE SCREEN_RGB
#define LVDS_FORMAT LVDS_8BIT_1
#define OUT_FACE OUT_P888
#define DCLK 50000000
#define LCDC_ACLK 500000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 30
#define H_BP 10
#define H_VD 1024
#define H_FP 210
#define V_PW 13
#define V_BP 10
#define V_VD 600
#define V_FP 22
#define LCD_WIDTH 154
#define LCD_HEIGHT 85
/* Other */
#define DCLK_POL 0
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#endif

62
drivers/video/rockchip/screen/lcd_I30_800x480.c Normal file
View File

@@ -0,0 +1,62 @@
#ifndef __LCD_I30__
#define __LCD_I30__
/* Base */
#define LCD_WIDTH 154 //need modify
#define LCD_HEIGHT 85
#define SCREEN_TYPE SCREEN_RGB
#define LVDS_FORMAT LVDS_8BIT_1
#define OUT_FACE OUT_P666
#define DCLK 30000000
#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 48 //10
#define H_BP 88 //100
#define H_VD 800
#define H_FP 40 //210
#define V_PW 3 //10
#define V_BP 32 //10
#define V_VD 480
#define V_FP 13 //18
/* Other */
#define DCLK_POL 1
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#define RK_SCREEN_INIT
static struct rk29lcd_info *gLcd_info = NULL;
static int rk_lcd_init(void)
{
int ret = 0;
if(gLcd_info && gLcd_info->io_init)
gLcd_info->io_init();
return 0;
}
static int rk_lcd_standby(u8 enable)
{
if(!enable)
{
if(gLcd_info && gLcd_info->io_enable)
gLcd_info->io_enable();
}
else
{
if(gLcd_info && gLcd_info->io_disable)
gLcd_info->io_disable();
}
return 0;
}
#endif

33
drivers/video/rockchip/screen/lcd_LG_LP097X02.c Normal file
View File

@@ -0,0 +1,33 @@
#ifndef __LCD_LG097X02__
#define __LCD_LG097X02__
/* Base */
#define SCREEN_TYPE SCREEN_RGB
#define LVDS_FORMAT LVDS_8BIT_1
#define OUT_FACE OUT_D888_P666
#define DCLK 100000000
#define LCDC_ACLK 500000000
/* Timing */
#define H_PW 320
#define H_BP 480
#define H_VD 1024
#define H_FP 260
#define V_PW 10
#define V_BP 6
#define V_VD 768
#define V_FP 16
#define LCD_WIDTH 196// 142 // 202
#define LCD_HEIGHT 147 //106// 152
/* Other */
#define DCLK_POL 1 //
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#endif

78
drivers/video/display/screen/lcd_LP097QX1.c → drivers/video/rockchip/screen/lcd_LP097QX1.c
View File

@@ -1,18 +1,12 @@
#include <linux/rk_fb.h>
#include <linux/delay.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#ifndef __LCD_LP097QX1__
#define __LCD_LP097QX1__
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P666
#define OUT_CLK 205000000 //160000000//205000000
#define LCDC_ACLK 300000000 //29 lcdc axi DMA ƵÂÊ
#define SCREEN_TYPE SCREEN_RGB
#define LVDS_FORMAT LVDS_8BIT_1
#define OUT_FACE OUT_P666
#define DCLK 205000000 //160000000//205000000
#define LCDC_ACLK 300000000 //29 lcdc axi DMA ƵÂÊ
/* Timing */
#define H_PW 5
@@ -36,6 +30,10 @@
#define LCD_HEIGHT 135
/* Other */
#define DCLK_POL 1
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_DUMMY 0
#define SWAP_GB 0
@@ -76,56 +74,4 @@ int dsp_lut[256] ={
0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff,
};
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = SWAP_RG;
screen->swap_gb = SWAP_GB;
screen->swap_delta = 0;
screen->swap_dumy = SWAP_DUMMY;
/* Operation function*/
screen->init = NULL;
screen->standby = NULL;
screen->dsp_lut = dsp_lut;
}
size_t get_fb_size(void)
{
size_t size = 0;
#if defined(CONFIG_THREE_FB_BUFFER)
size = ((H_VD)*(V_VD)<<2)* 3; //three buffer
#else
size = ((H_VD)*(V_VD)<<2)<<1; //two buffer
#endif
return ALIGN(size,SZ_1M);
}
#endif

38
drivers/video/rockchip/screen/lcd_YQ70CPT9160.c Normal file
View File

@@ -0,0 +1,38 @@
/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */
#ifndef __LCD_YQ70CPT__
#define __LCD_YQ70CPT__
/* Base */
#define SCREEN_TYPE SCREEN_RGB
#define LVDS_FORMAT LVDS_8BIT_1
#define OUT_FACE OUT_P666
#define DCLK 33000000
#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 30//48 //10
#define H_BP 10//40 //100
#define H_VD 800 //1024
#define H_FP 210// //210
#define V_PW 13//10
#define V_BP 10// //10
#define V_VD 480 //768
#define V_FP 22 //18
/* Other */
#define DCLK_POL 1
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#define LCD_WIDTH 154 //need modify
#define LCD_HEIGHT 85
#endif

36
drivers/video/rockchip/screen/lcd_YQ70CPT9160_rk3168_86v.c Normal file
View File

@@ -0,0 +1,36 @@
/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */
#ifndef __LCD_YQ70CPT__
#define __LCD_YQ70CPT__
/* Base */
#define SCREEN_TYPE SCREEN_RGB
#define OUT_FACE OUT_P888
#define DCLK 33000000
#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 30//48 //10
#define H_BP 10//40 //100
#define H_VD 800 //1024
#define H_FP 210// //210
#define V_PW 13//10
#define V_BP 10// //10
#define V_VD 480 //768
#define V_FP 22 //18
#define LCD_WIDTH 154
#define LCD_HEIGHT 85
/* Other */
#define DCLK_POL 0
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#endif

40
drivers/video/rockchip/screen/lcd_YQ70CPT9160_v86.c Normal file
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@@ -0,0 +1,40 @@
/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */
#ifndef __LCD_YQ70CPT__
#define __LCD_YQ70CPT__
/* Base */
#define SCREEN_TYPE SCREEN_RGB
#define LVDS_FORMAT LVDS_8BIT_1
#define OUT_FACE OUT_P666
#define DCLK 33000000
#define LCDC_ACLK 50000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 30//48 //10
#define H_BP 10//40 //100
#define H_VD 800 //1024
#define H_FP 210// //210
#define V_PW 13//10
#define V_BP 10// //10
#define V_VD 480 //768
#define V_FP 22 //18
/* Other */
#define DCLK_POL 0
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_DUMMY 0
#define SWAP_GB 0
#define SWAP_RG 0
#define LCD_WIDTH 154 //need modify
#define LCD_HEIGHT 85
#endif

0
drivers/video/display/screen/lcd_a060se02.c → drivers/video/rockchip/screen/lcd_a060se02.c Executable file → Normal file
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0
drivers/video/display/screen/lcd_at070tn93.c → drivers/video/rockchip/screen/lcd_at070tn93.c
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182
drivers/video/display/screen/lcd_auto.c → drivers/video/rockchip/screen/lcd_auto.c Executable file → Normal file
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@@ -1,42 +1,26 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/miscdevice.h>
#ifndef __LCD_AUTO__
#define __LCD_AUTO__
#include <mach/board.h>
#include <linux/gpio.h>
#include <asm/uaccess.h>
#include <asm/atomic.h>
#include <linux/delay.h>
#include <linux/input.h>
#include <linux/workqueue.h>
#include <linux/freezer.h>
#include <linux/input/mt.h>
#ifdef CONFIG_HAS_EARLYSUSPEND
#include <linux/earlysuspend.h>
#if defined(CONFIG_HAS_EARLYSUSPEND)
#include<linux/earlysuspend.h>
#endif
#include <linux/ts-auto.h>
#include "screen.h"
#include <linux/rk_board_id.h>
extern struct rk29_bl_info rk29_bl_info;
//FOR ID0
/* Base */
#define OUT_TYPE_ID0 SCREEN_RGB
#define SCREEN_TYPE_ID0 SCREEN_RGB
#define OUT_FACE_ID0 OUT_P888
#define OUT_CLK_ID0 71000000
#define DCLK_ID0 71000000
#define LCDC_ACLK_ID0 500000000//312000000 //29 lcdc axi DMA ƵÂÊ
/* Timing */
@@ -54,13 +38,22 @@ extern struct rk29_bl_info rk29_bl_info;
#define LCD_HEIGHT_ID0 152
/* Other */
#define DCLK_POL_ID0 0
#define SWAP_RB_ID0 0
#define DEN_POL_ID0 0
#define VSYNC_POL_ID0 0
#define HSYNC_POL_ID0 0
#define SWAP_RB_ID0 0
#define SWAP_DUMMY_ID0 0
#define SWAP_GB_ID0 0
#define SWAP_RG_ID0 0
//FOR ID1
/* Base */
#define OUT_TYPE_ID1 SCREEN_RGB
#define SCREEN_TYPE_ID1 SCREEN_RGB
#define OUT_FACE_ID1 OUT_P888
#define OUT_CLK_ID1 71000000
#define DCLK_ID1 71000000
#define LCDC_ACLK_ID1 500000000
/* Timing */
@@ -77,7 +70,15 @@ extern struct rk29_bl_info rk29_bl_info;
/* Other */
#define DCLK_POL_ID1 0
#define DEN_POL_ID1 0
#define VSYNC_POL_ID1 0
#define HSYNC_POL_ID1 0
#define SWAP_RB_ID1 0
#define SWAP_DUMMY_ID1 0
#define SWAP_GB_ID1 0
#define SWAP_RG_ID1 0
#define LCD_WIDTH_ID1 270
#define LCD_HEIGHT_ID1 202
@@ -85,10 +86,10 @@ extern struct rk29_bl_info rk29_bl_info;
//FOR ID2
#define OUT_TYPE_ID2 SCREEN_RGB
#define SCREEN_TYPE_ID2 SCREEN_RGB
#define OUT_FACE_ID2 OUT_P888
#define OUT_CLK_ID2 65000000
#define DCLK_ID2 65000000
#define LCDC_ACLK_ID2 500000000
/* Timing */
@@ -106,13 +107,21 @@ extern struct rk29_bl_info rk29_bl_info;
#define LCD_HEIGHT_ID2 162
/* Other */
#define DCLK_POL_ID2 0
#define SWAP_RB_ID2 0
#define DEN_POL_ID2 0
#define VSYNC_POL_ID2 0
#define HSYNC_POL_ID2 0
#define SWAP_RB_ID2 0
#define SWAP_DUMMY_ID2 0
#define SWAP_GB_ID2 0
#define SWAP_RG_ID2 0
//FOR ID3
/* Base */
#define OUT_TYPE_ID3 SCREEN_RGB
#define SCREEN_TYPE_ID3 SCREEN_RGB
#define OUT_FACE_ID3 OUT_P888
#define OUT_CLK_ID3 71000000
#define DCLK_ID3 71000000
#define LCDC_ACLK_ID3 500000000
/* Timing */
@@ -129,7 +138,15 @@ extern struct rk29_bl_info rk29_bl_info;
/* Other */
#define DCLK_POL_ID3 0
#define DEN_POL_ID3 0
#define VSYNC_POL_ID3 0
#define HSYNC_POL_ID3 0
#define SWAP_RB_ID3 0
#define SWAP_DUMMY_ID3 0
#define SWAP_GB_ID3 0
#define SWAP_RG_ID3 0
#define LCD_WIDTH_ID3 270
#define LCD_HEIGHT_ID3 202
@@ -137,9 +154,9 @@ extern struct rk29_bl_info rk29_bl_info;
//FOR ID4
/* Base */
#define OUT_TYPE_ID4 SCREEN_RGB
#define SCREEN_TYPE_ID4 SCREEN_RGB
#define OUT_FACE_ID4 OUT_P888
#define OUT_CLK_ID4 71000000
#define DCLK_ID4 71000000
#define LCDC_ACLK_ID4 300000000 //29 lcdc axi DMA ƵÂÊ
/* Timing */
@@ -156,12 +173,22 @@ extern struct rk29_bl_info rk29_bl_info;
/* Other */
#define DCLK_POL_ID4 0
#define DEN_POL_ID4 0
#define VSYNC_POL_ID4 0
#define HSYNC_POL_ID4 0
#define SWAP_RB_ID4 0
#define SWAP_DUMMY_ID4 0
#define SWAP_GB_ID4 0
#define SWAP_RG_ID4 0
#define LCD_WIDTH_ID4 152
#define LCD_HEIGHT_ID4 202
#define H_VD 1280
#define V_VD 800
#if defined(CONFIG_TS_AUTO)
extern struct ts_private_data *g_ts;
#else
@@ -214,18 +241,20 @@ static int lcd_get_id(void)
return id;
}
#define RK_USE_SCREEN_ID
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
#if defined(RK_USE_SCREEN_ID)
void set_lcd_info_by_id(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
int id;
id = lcd_get_id();
switch(id)
{
case BOARD_ID_DS763:
case BOARD_ID_DS763:
/* screen type & face */
screen->type = OUT_TYPE_ID0;
screen->type = SCREEN_TYPE_ID0;
screen->face = OUT_FACE_ID0;
/* Screen size */
@@ -237,7 +266,7 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
/* Timing */
screen->lcdc_aclk = LCDC_ACLK_ID0;
screen->pixclock = OUT_CLK_ID0;
screen->pixclock = DCLK_ID0;
screen->left_margin = H_BP_ID0;
screen->right_margin = H_FP_ID0;
screen->hsync_len = H_PW_ID0;
@@ -246,15 +275,15 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
screen->vsync_len = V_PW_ID0;
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_hsync = HSYNC_POL_ID0;
screen->pin_vsync = VSYNC_POL_ID0;
screen->pin_den = DEN_POL_ID0;
screen->pin_dclk = DCLK_POL_ID0;
/* Swap rule */
screen->swap_rb = SWAP_RB_ID0;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_rg = SWAP_RG_ID0;
screen->swap_gb = SWAP_GB_ID0;
screen->swap_delta = 0;
screen->swap_dumy = 0;
@@ -264,10 +293,10 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
break;
case BOARD_ID_C8002:
case BOARD_ID_C8002:
/* screen type & face */
screen->type = OUT_TYPE_ID1;
screen->type = SCREEN_TYPE_ID1;
screen->face = OUT_FACE_ID1;
/* Screen size */
@@ -279,7 +308,7 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
/* Timing */
screen->lcdc_aclk = LCDC_ACLK_ID1;
screen->pixclock = OUT_CLK_ID1;
screen->pixclock = DCLK_ID1;
screen->left_margin = H_BP_ID1;
screen->right_margin = H_FP_ID1;
screen->hsync_len = H_PW_ID1;
@@ -288,15 +317,15 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
screen->vsync_len = V_PW_ID1;
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_hsync = HSYNC_POL_ID1;
screen->pin_vsync = VSYNC_POL_ID1;
screen->pin_den = DEN_POL_ID1;
screen->pin_dclk = DCLK_POL_ID1;
/* Swap rule */
screen->swap_rb = SWAP_RB_ID1;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_rg = SWAP_RG_ID1;
screen->swap_gb = SWAP_GB_ID1;
screen->swap_delta = 0;
screen->swap_dumy = 0;
@@ -305,10 +334,10 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
screen->standby = NULL;
break;
case BOARD_ID_C8003:
case BOARD_ID_C8003:
/* screen type & face */
screen->type = OUT_TYPE_ID2;
screen->type = SCREEN_TYPE_ID2;
screen->face = OUT_FACE_ID2;
/* Screen size */
@@ -320,7 +349,7 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
/* Timing */
screen->lcdc_aclk = LCDC_ACLK_ID2;
screen->pixclock = OUT_CLK_ID2;
screen->pixclock = DCLK_ID2;
screen->left_margin = H_BP_ID2;
screen->right_margin = H_FP_ID2;
screen->hsync_len = H_PW_ID2;
@@ -329,15 +358,15 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
screen->vsync_len = V_PW_ID2;
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_hsync = HSYNC_POL_ID2;
screen->pin_vsync = VSYNC_POL_ID2;
screen->pin_den = DEN_POL_ID2;
screen->pin_dclk = DCLK_POL_ID2;
/* Swap rule */
screen->swap_rb = SWAP_RB_ID2;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_rg = SWAP_RG_ID2;
screen->swap_gb = SWAP_GB_ID2;
screen->swap_delta = 0;
screen->swap_dumy = 0;
@@ -347,11 +376,11 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
break;
case BOARD_ID_C1014:
case BOARD_ID_C1014:
default:
/* screen type & face */
screen->type = OUT_TYPE_ID3;
screen->type = SCREEN_TYPE_ID3;
screen->face = OUT_FACE_ID3;
/* Screen size */
@@ -363,7 +392,7 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
/* Timing */
screen->lcdc_aclk = LCDC_ACLK_ID3;
screen->pixclock = OUT_CLK_ID3;
screen->pixclock = DCLK_ID3;
screen->left_margin = H_BP_ID3;
screen->right_margin = H_FP_ID3;
screen->hsync_len = H_PW_ID3;
@@ -372,15 +401,15 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
screen->vsync_len = V_PW_ID3;
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_hsync = HSYNC_POL_ID3;
screen->pin_vsync = VSYNC_POL_ID3;
screen->pin_den = DEN_POL_ID3;
screen->pin_dclk = DCLK_POL_ID3;
/* Swap rule */
screen->swap_rb = SWAP_RB_ID3;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_rg = SWAP_RG_ID3;
screen->swap_gb = SWAP_GB_ID3;
screen->swap_delta = 0;
screen->swap_dumy = 0;
@@ -390,10 +419,10 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
break;
case BOARD_ID_C7018:
case BOARD_ID_C7018:
/* screen type & face */
screen->type = OUT_TYPE_ID4;
screen->type = SCREEN_TYPE_ID4;
screen->face = OUT_FACE_ID4;
/* Screen size */
@@ -405,7 +434,7 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
/* Timing */
screen->lcdc_aclk = LCDC_ACLK_ID4;
screen->pixclock = OUT_CLK_ID4;
screen->pixclock = DCLK_ID4;
screen->left_margin = H_BP_ID4;
screen->right_margin = H_FP_ID4;
screen->hsync_len = H_PW_ID4;
@@ -414,15 +443,15 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
screen->vsync_len = V_PW_ID4;
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_hsync = HSYNC_POL_ID4;
screen->pin_vsync = VSYNC_POL_ID4;
screen->pin_den = DEN_POL_ID4;
screen->pin_dclk = DCLK_POL_ID4;
/* Swap rule */
screen->swap_rb = SWAP_RB_ID4;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_rg = SWAP_RG_ID4;
screen->swap_gb = SWAP_GB_ID4;
screen->swap_delta = 0;
screen->swap_dumy = 0;
@@ -440,5 +469,6 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
}
#endif
#endif

258
drivers/video/display/screen/lcd_b101uano_1920x1200.c → drivers/video/rockchip/screen/lcd_b101ew05.c Executable file → Normal file
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@@ -1,46 +1,35 @@
#ifndef __LCD_B101EW05__
#define __LCD_B101EW05__
#include <linux/delay.h>
#include <linux/rk_fb.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#if defined(CONFIG_RK_HDMI)
#include "../../rockchip/hdmi/rk_hdmi.h"
#endif
#if defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS)
#if defined(CONFIG_RK610_LVDS)
#include "../transmitter/rk610_lcd.h"
#endif
/* Base */
#if defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS)
#define OUT_TYPE SCREEN_LVDS
#define LVDS_FORMAT LVDS_8BIT_1
#define SCREEN_TYPE SCREEN_LVDS
#else
#define OUT_TYPE SCREEN_RGB
#define SCREEN_TYPE SCREEN_RGB
#endif
#define OUT_FACE OUT_P888
#define LVDS_FORMAT LVDS_8BIT_2
#define OUT_FACE OUT_D888_P666
#define OUT_CLK 160000000
#define LCDC_ACLK 500000000 //29 lcdc axi DMA ƵÂÊ
#define DCLK 71000000
#define LCDC_ACLK 300000000 //29 lcdc axi DMA ƵÂÊ
/* Timing */
#define H_PW 1
#define H_BP 90
#define H_VD 1920
#define H_FP 1
#define H_PW 10
#define H_BP 100
#define H_VD 1280
#define H_FP 18
#define V_PW 1
#define V_BP 12
#define V_VD 1200
#define V_FP 1
#define V_PW 2
#define V_BP 8
#define V_VD 800
#define V_FP 6
#define LCD_WIDTH 217
#define LCD_HEIGHT 136
#define LCD_WIDTH 216
#define LCD_HEIGHT 135
/* Other */
#if defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS)
#define DCLK_POL 1
@@ -55,6 +44,7 @@
#define SWAP_RG 0
#define SWAP_GB 0
#define USE_RK_DSP_LUT
int dsp_lut[256] ={
0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707,
0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f,
@@ -90,11 +80,15 @@ int dsp_lut[256] ={
0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff,
};
#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& ( defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS))
// if we use one lcdc with jetta for dual display,we need these configration
#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)
/* scaler Timing */
//1920*1080*60
#if defined(CONFIG_RK610_LVDS)
#define S_DCLK_POL 1
#define S_OUT_CLK SCALE_RATE(148500000,74250000) //m=16 n=9 no=4
#define S_H_PW 48
#define S_H_BP 98
@@ -108,15 +102,20 @@ int dsp_lut[256] ={
#define S_H_ST 495
#define S_V_ST 2
#endif
#if defined(CONFIG_RK616_LVDS)
#define S_PLL_CFG_VAL 0x01842016
#define S_FRAC 0xc16c2d
#define S_SCL_VST 0x25
#define S_SCL_HST 0x4ba
#define S_VIF_VST 0x1
#define S_VIF_HST 0xca
#define S_VIF_HST 0xca
#endif
//1920*1080*50
#if defined(CONFIG_RK610_LVDS)
#define S1_OUT_CLK SCALE_RATE(148500000,57375000) //m=17 n=11 no=4
#define S1_H_PW 10
#define S1_H_BP 10
@@ -130,16 +129,19 @@ int dsp_lut[256] ={
#define S1_H_ST 459
#define S1_V_ST 13
#endif
#if defined(CONFIG_RK616_LVDS)
#define S1_PLL_CFG_VAL 0x01c42016
#define S1_FRAC 0x1f9ad4
#define S1_SCL_VST 0x25
#define S1_SCL_HST 0x5ab
#define S1_VIF_VST 0x1
#define S1_VIF_HST 0xca
#endif
//1280*720*60
#if defined(CONFIG_RK610_LVDS)
#define S2_OUT_CLK SCALE_RATE(74250000,74250000) //m=32 n=9 no=4
#define S2_H_PW 48
#define S2_H_BP 98
@@ -147,25 +149,26 @@ int dsp_lut[256] ={
#define S2_H_FP 59
#define S2_V_PW 6
#define S2_V_BP 5
#define S2_V_BP 25
#define S2_V_VD 800
#define S2_V_FP 2
#define S2_H_ST 495
#define S2_V_ST 15
#define S2_V_ST 5
#endif
//bellow are for jettaB
#if defined(CONFIG_RK616_LVDS)
#define S2_PLL_CFG_VAL 0x01822016
#define S2_FRAC 0xc16c2d
#define S2_SCL_VST 0x19
#define S2_SCL_HST 0x483
#define S2_VIF_VST 0x1
#define S2_VIF_HST 0xcf
#endif
//1280*720*50
#if defined(CONFIG_RK610_LVDS)
#define S3_OUT_CLK SCALE_RATE(74250000,67500000) // m=34 n=11 no=4
#define S3_H_PW 48
#define S3_H_BP 233
@@ -173,20 +176,25 @@ int dsp_lut[256] ={
#define S3_H_FP 59
#define S3_V_PW 6
#define S3_V_BP 5
#define S3_V_BP 25
#define S3_V_VD 800
#define S3_V_FP 2
#define S3_H_ST 540
#define S3_V_ST 14
#define S3_V_ST 3
#endif
#if defined(CONFIG_RK616_LVDS)
#define S3_PLL_CFG_VAL 0x01c22016
#define S3_FRAC 0x1f9ad4
#define S3_SCL_VST 0x19
#define S3_SCL_HST 0x569
#define S3_VIF_VST 0x1
#define S3_VIF_HST 0xcf
#endif
//720*576*50
#if defined(CONFIG_RK610_LVDS)
#define S4_OUT_CLK SCALE_RATE(27000000,70312500) //m=75 n=4 no=8
#define S4_H_PW 48
#define S4_H_BP 233
@@ -200,16 +208,19 @@ int dsp_lut[256] ={
#define S4_H_ST 90
#define S4_V_ST 2
#endif
#if defined(CONFIG_RK616_LVDS)
#define S4_PLL_CFG_VAL 0x01412016
#define S4_FRAC 0xa23d09
#define S4_SCL_VST 0x2d
#define S4_SCL_HST 0x33d
#define S4_VIF_VST 0x1
#define S4_VIF_HST 0xc1
#endif
//720*480*60
#if defined(CONFIG_RK610_LVDS)
#define S5_OUT_CLK SCALE_RATE(27000000,75000000) //m=100 n=9 no=4
#define S5_H_PW 48
#define S5_H_BP 86
@@ -223,6 +234,8 @@ int dsp_lut[256] ={
#define S5_H_ST 476
#define S5_V_ST 12
#endif
#if defined(CONFIG_RK616_LVDS)
#define S5_PLL_CFG_VAL 0x01c11013
#define S5_FRAC 0x25325e
@@ -230,172 +243,9 @@ int dsp_lut[256] ={
#define S5_SCL_HST 0x2ae
#define S5_VIF_VST 0x1
#define S5_VIF_HST 0xc1
#define S_DCLK_POL 1
static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
{
screen->s_clk_inv = S_DCLK_POL;
screen->s_den_inv = 0;
screen->s_hv_sync_inv = 0;
switch(hdmi_resolution){
case HDMI_1920x1080p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S_OUT_CLK;
screen->s_hsync_len = S_H_PW;
screen->s_left_margin = S_H_BP;
screen->s_right_margin = S_H_FP;
screen->s_hsync_len = S_H_PW;
screen->s_upper_margin = S_V_BP;
screen->s_lower_margin = S_V_FP;
screen->s_vsync_len = S_V_PW;
screen->s_hsync_st = S_H_ST;
screen->s_vsync_st = S_V_ST;
break;
case HDMI_1920x1080p_50Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S1_OUT_CLK;
screen->s_hsync_len = S1_H_PW;
screen->s_left_margin = S1_H_BP;
screen->s_right_margin = S1_H_FP;
screen->s_hsync_len = S1_H_PW;
screen->s_upper_margin = S1_V_BP;
screen->s_lower_margin = S1_V_FP;
screen->s_vsync_len = S1_V_PW;
screen->s_hsync_st = S1_H_ST;
screen->s_vsync_st = S1_V_ST;
break;
case HDMI_1280x720p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S2_OUT_CLK;
screen->s_hsync_len = S2_H_PW;
screen->s_left_margin = S2_H_BP;
screen->s_right_margin = S2_H_FP;
screen->s_hsync_len = S2_H_PW;
screen->s_upper_margin = S2_V_BP;
screen->s_lower_margin = S2_V_FP;
screen->s_vsync_len = S2_V_PW;
screen->s_hsync_st = S2_H_ST;
screen->s_vsync_st = S2_V_ST;
break;
case HDMI_1280x720p_50Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S3_OUT_CLK;
screen->s_hsync_len = S3_H_PW;
screen->s_left_margin = S3_H_BP;
screen->s_right_margin = S3_H_FP;
screen->s_hsync_len = S3_H_PW;
screen->s_upper_margin = S3_V_BP;
screen->s_lower_margin = S3_V_FP;
screen->s_vsync_len = S3_V_PW;
screen->s_hsync_st = S3_H_ST;
screen->s_vsync_st = S3_V_ST;
break;
case HDMI_720x576p_50Hz_4_3:
case HDMI_720x576p_50Hz_16_9:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S4_OUT_CLK;
screen->s_hsync_len = S4_H_PW;
screen->s_left_margin = S4_H_BP;
screen->s_right_margin = S4_H_FP;
screen->s_hsync_len = S4_H_PW;
screen->s_upper_margin = S4_V_BP;
screen->s_lower_margin = S4_V_FP;
screen->s_vsync_len = S4_V_PW;
screen->s_hsync_st = S4_H_ST;
screen->s_vsync_st = S4_V_ST;
break;
case HDMI_720x480p_60Hz_16_9:
case HDMI_720x480p_60Hz_4_3:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S5_OUT_CLK;
screen->s_hsync_len = S5_H_PW;
screen->s_left_margin = S5_H_BP;
screen->s_right_margin = S5_H_FP;
screen->s_hsync_len = S5_H_PW;
screen->s_upper_margin = S5_V_BP;
screen->s_lower_margin = S5_V_FP;
screen->s_vsync_len = S5_V_PW;
screen->s_hsync_st = S5_H_ST;
screen->s_vsync_st = S5_V_ST;
break;
default :
printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution);
return -1;
break;
}
return 0;
}
#else
#define set_scaler_info NULL
#endif
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->face = OUT_FACE;
screen->type = OUT_TYPE;
#if defined(CONFIG_RK610_LVDS)|| defined(CONFIG_RK616_VIF)
screen->hw_format = LVDS_FORMAT;
#endif
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = HSYNC_POL;
screen->pin_vsync = VSYNC_POL;
screen->pin_den = DEN_POL;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = SWAP_RG;
screen->swap_gb = SWAP_GB;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
screen->init = NULL;
screen->standby = NULL;
screen->dsp_lut = dsp_lut;
screen->sscreen_get = set_scaler_info;
#if defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_LVDS)
screen->sscreen_set = rk610_lcd_scaler_set_param;
#endif
}
size_t get_fb_size(void)
{
size_t size = 0;
#if defined(CONFIG_THREE_FB_BUFFER)
size = ((H_VD)*(V_VD)<<2)* 3; //three buffer
#else
size = ((H_VD)*(V_VD)<<2)<<1; //two buffer
#endif
return ALIGN(size,SZ_1M);
}

138
drivers/video/rockchip/screen/lcd_b101uano_1920x1200.c Normal file
View File

@@ -0,0 +1,138 @@
#ifndef __LCD_B101UANO__
#define __LCD_B101UANO__
/* Base */
#if defined(CONFIG_RK616_LVDS)
#define SCREEN_TYPE SCREEN_LVDS
#else
#define SCREEN_TYPE SCREEN_RGB
#endif
#define LVDS_FORMAT LVDS_8BIT_1
#define OUT_FACE OUT_P888
#define DCLK 160000000
#define LCDC_ACLK 500000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 1
#define H_BP 90
#define H_VD 1920
#define H_FP 1
#define V_PW 1
#define V_BP 12
#define V_VD 1200
#define V_FP 1
#define LCD_WIDTH 217
#define LCD_HEIGHT 136
/* Other */
#if defined(CONFIG_RK616_LVDS)
#define DCLK_POL 1
#else
#define DCLK_POL 0
#endif
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#define USE_RK_DSP_LUT
int dsp_lut[256] ={
0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707,
0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f,
0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717,
0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f,
0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727,
0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f,
0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737,
0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f,
0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747,
0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f,
0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757,
0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f,
0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767,
0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f,
0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777,
0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f,
0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787,
0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f,
0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797,
0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f,
0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7,
0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf,
0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7,
0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf,
0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7,
0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf,
0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7,
0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf,
0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7,
0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef,
0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7,
0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff,
};
#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK616_LVDS)
#define S_PLL_CFG_VAL 0x01842016
#define S_FRAC 0xc16c2d
#define S_SCL_VST 0x25
#define S_SCL_HST 0x4ba
#define S_VIF_VST 0x1
#define S_VIF_HST 0xca
//1920*1080*50
#define S1_PLL_CFG_VAL 0x01c42016
#define S1_FRAC 0x1f9ad4
#define S1_SCL_VST 0x25
#define S1_SCL_HST 0x5ab
#define S1_VIF_VST 0x1
#define S1_VIF_HST 0xca
//1280*720*60
//bellow are for jettaB
#define S2_PLL_CFG_VAL 0x01822016
#define S2_FRAC 0xc16c2d
#define S2_SCL_VST 0x19
#define S2_SCL_HST 0x483
#define S2_VIF_VST 0x1
#define S2_VIF_HST 0xcf
//1280*720*50
#define S3_PLL_CFG_VAL 0x01c22016
#define S3_FRAC 0x1f9ad4
#define S3_SCL_VST 0x19
#define S3_SCL_HST 0x569
#define S3_VIF_VST 0x1
#define S3_VIF_HST 0xcf
//720*576*50
#define S4_PLL_CFG_VAL 0x01412016
#define S4_FRAC 0xa23d09
#define S4_SCL_VST 0x2d
#define S4_SCL_HST 0x33d
#define S4_VIF_VST 0x1
#define S4_VIF_HST 0xc1
//720*480*60
#define S5_PLL_CFG_VAL 0x01c11013
#define S5_FRAC 0x25325e
#define S5_SCL_VST 0x26
#define S5_SCL_HST 0x2ae
#define S5_VIF_VST 0x1
#define S5_VIF_HST 0xc1
#endif
#endif

0
drivers/video/display/screen/lcd_byd1024x600.c → drivers/video/rockchip/screen/lcd_byd1024x600.c
View File

0
drivers/video/display/screen/lcd_common.c → drivers/video/rockchip/screen/lcd_common.c
View File

188
drivers/video/display/screen/lcd_ds1006h.c → drivers/video/rockchip/screen/lcd_ds1006h.c Executable file → Normal file
View File

@@ -1,11 +1,5 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include <linux/rk_fb.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include "../../rockchip/hdmi/rk_hdmi.h"
#include "screen.h"
#ifndef __LCD_DS1006H__
#define __LCD_DS1006H__
#ifdef CONFIG_RK610_LVDS
#include "../transmitter/rk610_lcd.h"
@@ -14,16 +8,16 @@
/* Base */
#ifdef CONFIG_RK610_LVDS
#define OUT_TYPE SCREEN_LVDS
#define OUT_FORMAT LVDS_8BIT_1
#define SCREEN_TYPE SCREEN_LVDS
#else
#define OUT_TYPE SCREEN_RGB
#define SCREEN_TYPE SCREEN_RGB
#endif
#define LVDS_FORMAT LVDS_8BIT_1
#define OUT_FACE OUT_P888
#define OUT_CLK 71000000
#define DCLK 71000000
#define LCDC_ACLK 500000000 //29 lcdc axi DMA ƵÂÊ
/* Timing */
@@ -46,7 +40,14 @@
#define DCLK_POL 0
#endif
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
int dsp_lut[256] ={
0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707,
@@ -179,169 +180,8 @@ int dsp_lut[256] ={
#define S5_V_ST 12
#define S_DCLK_POL 1
static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
{
screen->s_clk_inv = S_DCLK_POL;
screen->s_den_inv = 0;
screen->s_hv_sync_inv = 0;
switch(hdmi_resolution){
case HDMI_1920x1080p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S_OUT_CLK;
screen->s_hsync_len = S_H_PW;
screen->s_left_margin = S_H_BP;
screen->s_right_margin = S_H_FP;
screen->s_hsync_len = S_H_PW;
screen->s_upper_margin = S_V_BP;
screen->s_lower_margin = S_V_FP;
screen->s_vsync_len = S_V_PW;
screen->s_hsync_st = S_H_ST;
screen->s_vsync_st = S_V_ST;
break;
case HDMI_1920x1080p_50Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S1_OUT_CLK;
screen->s_hsync_len = S1_H_PW;
screen->s_left_margin = S1_H_BP;
screen->s_right_margin = S1_H_FP;
screen->s_hsync_len = S1_H_PW;
screen->s_upper_margin = S1_V_BP;
screen->s_lower_margin = S1_V_FP;
screen->s_vsync_len = S1_V_PW;
screen->s_hsync_st = S1_H_ST;
screen->s_vsync_st = S1_V_ST;
break;
case HDMI_1280x720p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S2_OUT_CLK;
screen->s_hsync_len = S2_H_PW;
screen->s_left_margin = S2_H_BP;
screen->s_right_margin = S2_H_FP;
screen->s_hsync_len = S2_H_PW;
screen->s_upper_margin = S2_V_BP;
screen->s_lower_margin = S2_V_FP;
screen->s_vsync_len = S2_V_PW;
screen->s_hsync_st = S2_H_ST;
screen->s_vsync_st = S2_V_ST;
break;
case HDMI_1280x720p_50Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S3_OUT_CLK;
screen->s_hsync_len = S3_H_PW;
screen->s_left_margin = S3_H_BP;
screen->s_right_margin = S3_H_FP;
screen->s_hsync_len = S3_H_PW;
screen->s_upper_margin = S3_V_BP;
screen->s_lower_margin = S3_V_FP;
screen->s_vsync_len = S3_V_PW;
screen->s_hsync_st = S3_H_ST;
screen->s_vsync_st = S3_V_ST;
break;
case HDMI_720x576p_50Hz_4_3:
case HDMI_720x576p_50Hz_16_9:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S4_OUT_CLK;
screen->s_hsync_len = S4_H_PW;
screen->s_left_margin = S4_H_BP;
screen->s_right_margin = S4_H_FP;
screen->s_hsync_len = S4_H_PW;
screen->s_upper_margin = S4_V_BP;
screen->s_lower_margin = S4_V_FP;
screen->s_vsync_len = S4_V_PW;
screen->s_hsync_st = S4_H_ST;
screen->s_vsync_st = S4_V_ST;
break;
case HDMI_720x480p_60Hz_16_9:
case HDMI_720x480p_60Hz_4_3:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S5_OUT_CLK;
screen->s_hsync_len = S5_H_PW;
screen->s_left_margin = S5_H_BP;
screen->s_right_margin = S5_H_FP;
screen->s_hsync_len = S5_H_PW;
screen->s_upper_margin = S5_V_BP;
screen->s_lower_margin = S5_V_FP;
screen->s_vsync_len = S5_V_PW;
screen->s_hsync_st = S5_H_ST;
screen->s_vsync_st = S5_V_ST;
break;
default :
printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution);
return -1;
break;
}
return 0;
}
#else
#define set_scaler_info NULL
#endif
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->face = OUT_FACE;
screen->type = OUT_TYPE;
#ifdef CONFIG_RK610_LVDS
screen->hw_format = OUT_FORMAT;
#endif
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
screen->init = NULL;
screen->standby = NULL;
screen->dsp_lut = dsp_lut;
screen->sscreen_get = set_scaler_info;
#ifdef CONFIG_RK610_LVDS
screen->sscreen_set = rk610_lcd_scaler_set_param;
#endif
}
size_t get_fb_size(void)
{
size_t size = 0;
#if defined(CONFIG_THREE_FB_BUFFER)
size = ((H_VD)*(V_VD)<<2)* 3; //three buffer
#else
size = ((H_VD)*(V_VD)<<2)<<1; //two buffer
#endif
return ALIGN(size,SZ_1M);
}

184
drivers/video/display/screen/lcd_hdmi_1024x600.c → drivers/video/rockchip/screen/lcd_hdmi_1024x600.c
View File

@@ -1,11 +1,5 @@
#include <linux/fb.h>
#include <linux/delay.h>
#include <linux/rk_fb.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include "../../rockchip/hdmi/rk_hdmi.h"
#ifndef __LCD_HDMI_1024x600__
#define __LCD_HDMI_1024x600__
#ifdef CONFIG_RK610_LVDS
#include "../transmitter/rk610_lcd.h"
@@ -14,16 +8,15 @@
/* Base */
#ifdef CONFIG_RK610_LVDS
#define OUT_TYPE SCREEN_LVDS
#define LVDS_FORMAT LVDS_8BIT_1
#define SCREEN_TYPE SCREEN_LVDS
#else
#define OUT_TYPE SCREEN_RGB
#define SCREEN_TYPE SCREEN_RGB
#endif
#define LVDS_FORMAT LVDS_8BIT_1
#define OUT_FACE OUT_P888
//#define OUT_FACE OUT_P888
#define OUT_CLK 50000000 // 65000000
#define LCDC_ACLK 312000000//312000000 //29 lcdc axi DMA ƵÂÊ
#define DCLK 50000000 // 65000000
#define LCDC_ACLK 312000000//312000000 //29 lcdc axi DMA ƵÂÊ
/* Timing */
#define H_PW 20
@@ -184,169 +177,6 @@ int dsp_lut[256] ={
#define S5_V_ST 22
#define S_DCLK_POL 1
static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
{
screen->s_clk_inv = S_DCLK_POL;
screen->s_den_inv = 0;
screen->s_hv_sync_inv = 0;
switch(hdmi_resolution){
case HDMI_1920x1080p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S_OUT_CLK;
screen->s_hsync_len = S_H_PW;
screen->s_left_margin = S_H_BP;
screen->s_right_margin = S_H_FP;
screen->s_hsync_len = S_H_PW;
screen->s_upper_margin = S_V_BP;
screen->s_lower_margin = S_V_FP;
screen->s_vsync_len = S_V_PW;
screen->s_hsync_st = S_H_ST;
screen->s_vsync_st = S_V_ST;
break;
case HDMI_1920x1080p_50Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S1_OUT_CLK;
screen->s_hsync_len = S1_H_PW;
screen->s_left_margin = S1_H_BP;
screen->s_right_margin = S1_H_FP;
screen->s_hsync_len = S1_H_PW;
screen->s_upper_margin = S1_V_BP;
screen->s_lower_margin = S1_V_FP;
screen->s_vsync_len = S1_V_PW;
screen->s_hsync_st = S1_H_ST;
screen->s_vsync_st = S1_V_ST;
break;
case HDMI_1280x720p_60Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S2_OUT_CLK;
screen->s_hsync_len = S2_H_PW;
screen->s_left_margin = S2_H_BP;
screen->s_right_margin = S2_H_FP;
screen->s_hsync_len = S2_H_PW;
screen->s_upper_margin = S2_V_BP;
screen->s_lower_margin = S2_V_FP;
screen->s_vsync_len = S2_V_PW;
screen->s_hsync_st = S2_H_ST;
screen->s_vsync_st = S2_V_ST;
break;
case HDMI_1280x720p_50Hz:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S3_OUT_CLK;
screen->s_hsync_len = S3_H_PW;
screen->s_left_margin = S3_H_BP;
screen->s_right_margin = S3_H_FP;
screen->s_hsync_len = S3_H_PW;
screen->s_upper_margin = S3_V_BP;
screen->s_lower_margin = S3_V_FP;
screen->s_vsync_len = S3_V_PW;
screen->s_hsync_st = S3_H_ST;
screen->s_vsync_st = S3_V_ST;
break;
case HDMI_720x576p_50Hz_4_3:
case HDMI_720x576p_50Hz_16_9:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S4_OUT_CLK;
screen->s_hsync_len = S4_H_PW;
screen->s_left_margin = S4_H_BP;
screen->s_right_margin = S4_H_FP;
screen->s_hsync_len = S4_H_PW;
screen->s_upper_margin = S4_V_BP;
screen->s_lower_margin = S4_V_FP;
screen->s_vsync_len = S4_V_PW;
screen->s_hsync_st = S4_H_ST;
screen->s_vsync_st = S4_V_ST;
break;
case HDMI_720x480p_60Hz_16_9:
case HDMI_720x480p_60Hz_4_3:
/* Scaler Timing */
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S5_OUT_CLK;
screen->s_hsync_len = S5_H_PW;
screen->s_left_margin = S5_H_BP;
screen->s_right_margin = S5_H_FP;
screen->s_hsync_len = S5_H_PW;
screen->s_upper_margin = S5_V_BP;
screen->s_lower_margin = S5_V_FP;
screen->s_vsync_len = S5_V_PW;
screen->s_hsync_st = S5_H_ST;
screen->s_vsync_st = S5_V_ST;
break;
default :
printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution);
return -1;
break;
}
return 0;
}
#else
#define set_scaler_info NULL
#endif
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
#ifdef CONFIG_RK610_LVDS
screen->hw_format = LVDS_FORMAT;
#endif
screen->face = OUT_FACE;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = HSYNC_POL;
screen->pin_vsync = VSYNC_POL;
screen->pin_den = DEN_POL;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = SWAP_RG;
screen->swap_gb = SWAP_GB;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
screen->init = NULL;
screen->standby = NULL;
screen->dsp_lut = dsp_lut;
screen->sscreen_get = set_scaler_info;
#ifdef CONFIG_RK610_LVDS
screen->sscreen_set = rk610_lcd_scaler_set_param;
#endif
}
size_t get_fb_size(void)
{
size_t size = 0;
#if defined(CONFIG_THREE_FB_BUFFER)
size = ((H_VD)*(V_VD)<<2)* 3; //three buffer
#else
size = ((H_VD)*(V_VD)<<2)<<1; //two buffer
#endif
return ALIGN(size,SZ_1M);
}

138
drivers/video/rockchip/screen/lcd_hdmi_1024x768.c Normal file
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@@ -0,0 +1,138 @@
#ifndef __LCD_HDMI_1024x768__
#define __LCD_HDMI_1024x768__
#ifdef CONFIG_RK610_LVDS
#include "../transmitter/rk610_lcd.h"
#endif
/* Base */
#define SCREEN_TYPE SCREEN_LVDS
#define LVDS_FORMAT LVDS_8BIT_2
#define OUT_FACE OUT_D888_P666
#define DCLK 65000000
#define LCDC_ACLK 500000000//312000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 10
#define H_BP 100
#define H_VD 1024
#define H_FP 210
#define V_PW 10
#define V_BP 10
#define V_VD 768
#define V_FP 18
#define LCD_WIDTH 202
#define LCD_HEIGHT 152
#define DCLK_POL 1
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS)
/* scaler Timing */
//1920*1080*60
#define S_OUT_CLK SCALE_RATE(148500000,66000000) //m=16 n=9 no=4
#define S_H_PW 100
#define S_H_BP 100
#define S_H_VD 1024
#define S_H_FP 151
#define S_V_PW 5
#define S_V_BP 15
#define S_V_VD 768
#define S_V_FP 12
#define S_H_ST 1757
#define S_V_ST 14
//1920*1080*50
#define S1_OUT_CLK SCALE_RATE(148500000,54000000) //m=16 n=11 no=4
#define S1_H_PW 100
#define S1_H_BP 100
#define S1_H_VD 1024
#define S1_H_FP 126
#define S1_V_PW 5
#define S1_V_BP 15
#define S1_V_VD 768
#define S1_V_FP 12
#define S1_H_ST 1757
#define S1_V_ST 14
//1280*720*60
#define S2_OUT_CLK SCALE_RATE(74250000,66000000) //m=32 n=9 no=4
#define S2_H_PW 100
#define S2_H_BP 100
#define S2_H_VD 1024
#define S2_H_FP 151
#define S2_V_PW 5
#define S2_V_BP 15
#define S2_V_VD 768
#define S2_V_FP 12
#define S2_H_ST 0
#define S2_V_ST 12
//1280*720*50
#define S3_OUT_CLK SCALE_RATE(74250000,54000000) // m=32 n=11 no=4
#define S3_H_PW 100
#define S3_H_BP 100
#define S3_H_VD 1024
#define S3_H_FP 151
#define S3_V_PW 5
#define S3_V_BP 15
#define S3_V_VD 768
#define S3_V_FP 12
#define S3_H_ST 0
#define S3_V_ST 12
//720*576*50
#define S4_OUT_CLK SCALE_RATE(27000000,54375000) //m=145 n=9 no=8
#define S4_H_PW 100
#define S4_H_BP 100
#define S4_H_VD 1024
#define S4_H_FP 81
#define S4_V_PW 5
#define S4_V_BP 15
#define S4_V_VD 768
#define S4_V_FP 45
#define S4_H_ST 435
#define S4_V_ST 45
//720*480*60
#define S5_OUT_CLK SCALE_RATE(27000000,72000000) //m=32 n=3 no=4
#define S5_H_PW 100
#define S5_H_BP 100
#define S5_H_VD 1024
#define S5_H_FP 81
#define S5_V_PW 5
#define S5_V_BP 15
#define S5_V_VD 768
#define S5_V_FP 51
#define S5_H_ST 858
#define S5_V_ST 45
#define S_DCLK_POL 0
#endif
#endif

141
drivers/video/rockchip/screen/lcd_hdmi_1280x800.c Normal file
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@@ -0,0 +1,141 @@
#ifndef __LCD_HDMI_1280x800__
#define __LCD_HDMI_1280x800__
#ifdef CONFIG_RK610_LVDS
#include "../transmitter/rk610_lcd.h"
#endif
/* Base */
#define SCREEN_TYPE SCREEN_LVDS
#define LVDS_FORMAT LVDS_8BIT_2
#define OUT_FACE OUT_D888_P666
#define DCLK 65000000
#define LCDC_ACLK 500000000//312000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 10
#define H_BP 10
#define H_VD 1280
#define H_FP 20
#define V_PW 10
#define V_BP 10
#define V_VD 800
#define V_FP 13
#define LCD_WIDTH 202
#define LCD_HEIGHT 152
#define DCLK_POL 1
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS)
/* scaler Timing */
//1920*1080*60
#define S_OUT_CLK SCALE_RATE(148500000,66000000) //m=16 n=9 no=4
#define S_H_PW 10
#define S_H_BP 10
#define S_H_VD 1280
#define S_H_FP 20
#define S_V_PW 10
#define S_V_BP 10
#define S_V_VD 800
#define S_V_FP 13
#define S_H_ST 440
#define S_V_ST 13
//1920*1080*50
#define S1_OUT_CLK SCALE_RATE(148500000,57375000) //m=17 n=11 no=4
#define S1_H_PW 10
#define S1_H_BP 10
#define S1_H_VD 1280
#define S1_H_FP 77
#define S1_V_PW 10
#define S1_V_BP 10
#define S1_V_VD 800
#define S1_V_FP 13
#define S1_H_ST 459
#define S1_V_ST 13
//1280*720*60
#define S2_OUT_CLK SCALE_RATE(74250000,66000000) //m=32 n=9 no=4
#define S2_H_PW 10
#define S2_H_BP 10
#define S2_H_VD 1280
#define S2_H_FP 20
#define S2_V_PW 10
#define S2_V_BP 10
#define S2_V_VD 800
#define S2_V_FP 13
#define S2_H_ST 440
#define S2_V_ST 13
//1280*720*50
#define S3_OUT_CLK SCALE_RATE(74250000,57375000) // m=34 n=11 no=4
#define S3_H_PW 10
#define S3_H_BP 10
#define S3_H_VD 1280
#define S3_H_FP 77
#define S3_V_PW 10
#define S3_V_BP 10
#define S3_V_VD 800
#define S3_V_FP 13
#define S3_H_ST 459
#define S3_V_ST 13
//720*576*50
#define S4_OUT_CLK SCALE_RATE(27000000,63281250) //m=75 n=4 no=8
#define S4_H_PW 10
#define S4_H_BP 10
#define S4_H_VD 1280
#define S4_H_FP 185
#define S4_V_PW 10
#define S4_V_BP 10
#define S4_V_VD 800
#define S4_V_FP 48
#define S4_H_ST 81
#define S4_V_ST 48
//720*480*60
#define S5_OUT_CLK SCALE_RATE(27000000,75000000) //m=100 n=9 no=4
#define S5_H_PW 10
#define S5_H_BP 10
#define S5_H_VD 1280
#define S5_H_FP 130
#define S5_V_PW 10
#define S5_V_BP 10
#define S5_V_VD 800
#define S5_V_FP 54
#define S5_H_ST 476
#define S5_V_ST 48
#define S_DCLK_POL 0
#endif
#endif

178
drivers/video/rockchip/screen/lcd_hdmi_1366x768.c Normal file
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@@ -0,0 +1,178 @@
#ifndef __LCD_HDMI_1366x768__
#define __LCD_HDMI_1366x768__
#ifdef CONFIG_RK610_LVDS
#include "../transmitter/rk610_lcd.h"
#endif
/* Base */
#define SCREEN_TYPE SCREEN_LVDS
#define LVDS_FORMAT LVDS_8BIT_1
#define OUT_FACE OUT_D888_P666
#define DCLK 95000000 // 1280x800x1.13x60(hz)
#define LCDC_ACLK 500000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 34
#define H_BP 120
#define H_VD 1366
#define H_FP 80
#define V_PW 8
#define V_BP 50
#define V_VD 768
#define V_FP 12
#define DCLK_POL 1
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#define LCD_WIDTH 1366
#define LCD_HEIGHT 768
int dsp_lut[256] ={
0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707,
0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f,
0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717,
0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f,
0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727,
0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f,
0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737,
0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f,
0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747,
0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f,
0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757,
0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f,
0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767,
0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f,
0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777,
0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f,
0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787,
0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f,
0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797,
0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f,
0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7,
0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf,
0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7,
0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf,
0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7,
0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf,
0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7,
0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf,
0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7,
0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef,
0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7,
0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff,
};
#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS)
/* scaler Timing */
//1920*1080*60
#define S_OUT_CLK SCALE_RATE(148500000,79199997) //m=32 n=15 no=4
#define S_H_PW 34
#define S_H_BP 120
#define S_H_VD 1366
#define S_H_FP 130
#define S_V_PW 8
#define S_V_BP 10
#define S_V_VD 768
#define S_V_FP 13
#define S_H_ST 0
#define S_V_ST 15
//1920*1080*50
#define S1_OUT_CLK SCALE_RATE(148500000,66000000) //m=16 n=9 no=4
#define S1_H_PW 34
#define S1_H_BP 120
#define S1_H_VD 1366
#define S1_H_FP 130
#define S1_V_PW 8
#define S1_V_BP 10
#define S1_V_VD 768
#define S1_V_FP 14
#define S1_H_ST 0
#define S1_V_ST 15
//1280*720p 60HZ
#define S2_OUT_CLK SCALE_RATE(74250000,79199997) //m=64 n=15 no=4
#define S2_H_PW 34
#define S2_H_BP 120
#define S2_H_VD 1366
#define S2_H_FP 130
#define S2_V_PW 8
#define S2_V_BP 10
#define S2_V_VD 768
#define S2_V_FP 13
#define S2_H_ST 0
#define S2_V_ST 8
//1280*720*50
#define S3_OUT_CLK SCALE_RATE(74250000,66000000) // m=16 n=5 no=4
#define S3_H_PW 34
#define S3_H_BP 120
#define S3_H_VD 1366
#define S3_H_FP 130
#define S3_V_PW 8
#define S3_V_BP 10
#define S3_V_VD 768
#define S3_V_FP 14
#define S3_H_ST 0
#define S3_V_ST 8
//720*576*50
//run
#define S4_OUT_CLK SCALE_RATE(27000000,60000000) //m=91 n=9 no=4
#define S4_H_PW 34
#define S4_H_BP 20
#define S4_H_VD 1366
#define S4_H_FP 20
#define S4_V_PW 8
#define S4_V_BP 10
#define S4_V_VD 768
#define S4_V_FP 47
#define S4_H_ST 0
#define S4_V_ST 33
//720*480*60
#define S5_OUT_CLK SCALE_RATE(27000000,72000000) //m=79 n=7 no=4
#define S5_H_PW 34
#define S5_H_BP 20
#define S5_H_VD 1366
#define S5_H_FP 10
#define S5_V_PW 8
#define S5_V_BP 10
#define S5_V_VD 768
#define S5_V_FP 53
#define S5_H_ST 0
#define S5_V_ST 29
#define S_DCLK_POL 1
/* Other */
#endif

138
drivers/video/rockchip/screen/lcd_hdmi_800x480.c Normal file
View File

@@ -0,0 +1,138 @@
#ifndef __LCD_HDMI_800x480__
#define __LCD_HDMI_800x480__
#ifdef CONFIG_RK610_LVDS
#include "../transmitter/rk610_lcd.h"
#endif
/* Base */
#define SCREEN_TYPE SCREEN_RGB
#define LVDS_FORMAT LVDS_8BIT_1
#define OUT_FACE OUT_P888
#define DCLK 33000000
#define LCDC_ACLK 150000000//312000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 1
#define H_BP 88
#define H_VD 800
#define H_FP 40
#define V_PW 3
#define V_BP 29
#define V_VD 480
#define V_FP 13
#define LCD_WIDTH 154
#define LCD_HEIGHT 85
/* Other */
#define DCLK_POL 0
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS)
/* scaler Timing */
//1920*1080*60
#define S_OUT_CLK SCALE_RATE(148500000,33000000)
#define S_H_PW 1
#define S_H_BP 88
#define S_H_VD 800
#define S_H_FP 211
#define S_V_PW 3
#define S_V_BP 10
#define S_V_VD 480
#define S_V_FP 7
#define S_H_ST 244
#define S_V_ST 11
//1920*1080*50
#define S1_OUT_CLK SCALE_RATE(148500000,30375000)
#define S1_H_PW 1
#define S1_H_BP 88
#define S1_H_VD 800
#define S1_H_FP 326
#define S1_V_PW 3
#define S1_V_BP 9
#define S1_V_VD 480
#define S1_V_FP 8
#define S1_H_ST 270
#define S1_V_ST 13
//1280*720*60
#define S2_OUT_CLK SCALE_RATE(74250000,33000000)
#define S2_H_PW 1
#define S2_H_BP 88
#define S2_H_VD 800
#define S2_H_FP 211
#define S2_V_PW 3
#define S2_V_BP 9
#define S2_V_VD 480
#define S2_V_FP 8
#define S2_H_ST 0
#define S2_V_ST 8
//1280*720*50
#define S3_OUT_CLK SCALE_RATE(74250000,30375000)
#define S3_H_PW 1
#define S3_H_BP 88
#define S3_H_VD 800
#define S3_H_FP 326
#define S3_V_PW 3
#define S3_V_BP 9
#define S3_V_VD 480
#define S3_V_FP 8
#define S3_H_ST 0
#define S3_V_ST 8
//720*576*50
#define S4_OUT_CLK SCALE_RATE(27000000,30000000)
#define S4_H_PW 1
#define S4_H_BP 88
#define S4_H_VD 800
#define S4_H_FP 263
#define S4_V_PW 3
#define S4_V_BP 9
#define S4_V_VD 480
#define S4_V_FP 28
#define S4_H_ST 0
#define S4_V_ST 33
//720*480*60
#define S5_OUT_CLK SCALE_RATE(27000000,31500000)
#define S5_H_PW 1
#define S5_H_BP 88
#define S5_H_VD 800
#define S5_H_FP 112
#define S5_V_PW 3
#define S5_V_BP 9
#define S5_V_VD 480
#define S5_V_FP 28
#define S5_H_ST 0
#define S5_V_ST 29
#define S_DCLK_POL 0
#endif
#endif

85
drivers/video/rockchip/screen/lcd_hdmi_rk3168m_b101ew05.c Normal file
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@@ -0,0 +1,85 @@
#ifndef __LCD_RK3168M__
#define __LCD_RK3168M__
#ifdef CONFIG_RK610_LVDS
#include "../transmitter/rk610_lcd.h"
#endif
/* Base */
#ifdef CONFIG_RK610_LVDS
#define SCREEN_TYPE SCREEN_LVDS
#else
#define SCREEN_TYPE SCREEN_RGB
#endif
#define LVDS_FORMAT LVDS_8BIT_2
#define OUT_FACE OUT_D888_P666
#define DCLK 71000000
#define LCDC_ACLK 300000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 10
#define H_BP 100
#define H_VD 1280
#define H_FP 18
#define V_PW 2
#define V_BP 8
#define V_VD 800
#define V_FP 6
#define LCD_WIDTH 216
#define LCD_HEIGHT 135
/* Other */
#ifdef CONFIG_RK610_LVDS
#define DCLK_POL 1
#else
#define DCLK_POL 0
#endif
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
int dsp_lut[256] ={
0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707,
0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f,
0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717,
0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f,
0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727,
0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f,
0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737,
0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f,
0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747,
0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f,
0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757,
0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f,
0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767,
0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f,
0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777,
0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f,
0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787,
0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f,
0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797,
0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f,
0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7,
0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf,
0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7,
0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf,
0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7,
0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf,
0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7,
0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf,
0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7,
0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef,
0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7,
0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff,
};
#endif

0
drivers/video/display/screen/lcd_hh070d_lvds.c → drivers/video/rockchip/screen/lcd_hh070d_lvds.c Executable file → Normal file
View File

92
drivers/video/display/screen/lcd_hj050na_06a.c → drivers/video/rockchip/screen/lcd_hj050na_06a.c
View File

@@ -14,24 +14,21 @@
* GNU General Public License for more details.
*/
#ifndef __LCD_HJ050NA__
#define __LCD_HJ050NA__
#include <linux/fb.h>
#include <linux/delay.h>
#include <linux/rk_fb.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include<linux/rk_screen.h>
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_D888_P666// OUT_D888_P666 //OUT_P888
#define OUT_CLK 50000000 //50MHz
#define LCDC_ACLK 300000000 //29 lcdc axi DMA
#define SCREEN_TYPE SCREEN_RGB
#define LVDS_FORMAT LVDS_8BIT_2
#define OUT_FACE OUT_D888_P666// OUT_D888_P666 //OUT_P888
#define DCLK 50000000 //50MHz
#define LCDC_ACLK 300000000 //29 lcdc axi DMA
/* Timing */
#define H_PW 5
@@ -44,12 +41,21 @@
#define V_VD 960
#define V_FP 12
#define LCD_WIDTH 71 //uint mm the lenth of lcd active area
#define LCD_HEIGHT 106
#define LCD_WIDTH 71 //uint mm the lenth of lcd active area
#define LCD_HEIGHT 106
/* Other */
#define DCLK_POL 0
#define SWAP_RB 0
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#define RK_SCREEN_INIT //this screen need to init
#define CONFIG_DEEP_STANDBY_MODE 0
@@ -101,8 +107,8 @@
static struct rk29lcd_info *gLcd_info = NULL;
int lcd_init(void);
int lcd_standby(u8 enable);
int rk_lcd_init(void);
int rk_lcd_standby(u8 enable);
/* spi write a data frame,type mean command or data */
@@ -134,7 +140,7 @@ int spi_write_9bit(u32 type, u32 value)
}
int lcd_init(void)
int rk_lcd_init(void)
{
if(gLcd_info)
gLcd_info->io_init();
@@ -340,7 +346,7 @@ int lcd_init(void)
int lcd_standby(u8 enable)
int rk_lcd_standby(u8 enable)
{
if(enable) {
if(gLcd_info)
@@ -362,59 +368,11 @@ int lcd_standby(u8 enable)
gLcd_info->io_deinit();
} else {
lcd_init();
rk_lcd_init();
}
return 0;
}
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
#endif
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
screen->upper_margin = V_BP;
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
screen->init = lcd_init;
screen->standby = lcd_standby;
if(lcd_info)
gLcd_info = lcd_info;
if(LCD_RST_PORT){
if (gpio_request(LCD_RST_PORT, NULL) != 0) {
gpio_free(LCD_RST_PORT);
printk("%s: request LCD_RST_PORT error\n", __func__);
}
}
}

4
drivers/video/display/screen/lcd_hj080na.c → drivers/video/rockchip/screen/lcd_hj080na.c Executable file → Normal file
View File

@@ -9,10 +9,10 @@
/* Base */
#define OUT_TYPE SCREEN_RGB
#define LVDS_FORMAT LVDS_8BIT_2
#define OUT_FACE OUT_P888
#define OUT_CLK 65000000
#define LCDC_ACLK 500000000//312000000 //29 lcdc axi DMA ƵÂÊ
#define LCDC_ACLK 500000000//312000000 //29 lcdc axi DMA ƵÂÊ
/* Timing */
#define H_PW 100

42
drivers/video/rockchip/screen/lcd_hj101na.c Normal file
View File

@@ -0,0 +1,42 @@
/*
* This Lcd Driver is for BYD 5' LCD BM800480-8545FTGE.
* written by Michael Lin, 2010-06-18
*/
#ifndef __LCD_HJ101NA__
#define __LCD_HJ101NA__
/* Base */
#define SCREEN_TYPE SCREEN_RGB
#define OUT_FACE OUT_P888
#define DCLK 71000000
#define LCDC_ACLK 300000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 10
#define H_BP 160
#define H_VD 1280
#define H_FP 16
#define V_PW 3
#define V_BP 23
#define V_VD 800
#define V_FP 12
/* Other */
#define DCLK_POL 0
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#define LCD_WIDTH 216 //need modify
#define LCD_HEIGHT 135
#endif

0
drivers/video/display/screen/lcd_hl070vm4.c → drivers/video/rockchip/screen/lcd_hl070vm4.c
View File

130
drivers/video/rockchip/screen/lcd_hsd100pxn.c Normal file
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@@ -0,0 +1,130 @@
#ifndef __LCD_HSD100PXN__
#define __LCD_HSD100PXN__
/* Base */
#define SCREEN_TYPE SCREEN_LVDS
#define LVDS_FORMAT LVDS_8BIT_2
#define OUT_FACE OUT_D888_P666
#define DCLK 65000000
#define LCDC_ACLK 300000000//312000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 10
#define H_BP 100
#define H_VD 1024
#define H_FP 210
#define V_PW 10
#define V_BP 10
#define V_VD 768
#define V_FP 18
#define LCD_WIDTH 202
#define LCD_HEIGHT 152
/* Other */
#define DCLK_POL 1
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#ifdef CONFIG_ONE_LCDC_DUAL_OUTPUT_INF
/* scaler Timing */
//1920*1080*60
#define S_OUT_CLK 64512000
#define S_H_PW 114
#define S_H_BP 210
#define S_H_VD 1024
#define S_H_FP 0
#define S_V_PW 4
#define S_V_BP 10
#define S_V_VD 768
#define S_V_FP 0
#define S_H_ST 0
#define S_V_ST 23
//1920*1080*50
#define S1_OUT_CLK 53760000
#define S1_H_PW 114
#define S1_H_BP 210
#define S1_H_VD 1024
#define S1_H_FP 0
#define S1_V_PW 4
#define S1_V_BP 10
#define S1_V_VD 768
#define S1_V_FP 0
#define S1_H_ST 0
#define S1_V_ST 23
//1280*720*60
#define S2_OUT_CLK 64512000
#define S2_H_PW 114
#define S2_H_BP 210
#define S2_H_VD 1024
#define S2_H_FP 0
#define S2_V_PW 4
#define S2_V_BP 10
#define S2_V_VD 768
#define S2_V_FP 0
#define S2_H_ST 0
#define S2_V_ST 23
//1280*720*50
#define S3_OUT_CLK 53760000
#define S3_H_PW 114
#define S3_H_BP 210
#define S3_H_VD 1024
#define S3_H_FP 0
#define S3_V_PW 4
#define S3_V_BP 10
#define S3_V_VD 768
#define S3_V_FP 0
#define S3_H_ST 0
#define S3_V_ST 23
//720*576*50
#define S4_OUT_CLK 30000000
#define S4_H_PW 1
#define S4_H_BP 88
#define S4_H_VD 800
#define S4_H_FP 263
#define S4_V_PW 3
#define S4_V_BP 9
#define S4_V_VD 480
#define S4_V_FP 28
#define S4_H_ST 0
#define S4_V_ST 33
//720*480*60
#define S5_OUT_CLK 30000000
#define S5_H_PW 1
#define S5_H_BP 88
#define S5_H_VD 800
#define S5_H_FP 112
#define S5_V_PW 3
#define S5_V_BP 9
#define S5_V_VD 480
#define S5_V_FP 28
#define S5_H_ST 0
#define S5_V_ST 29
#define S_DCLK_POL 1
#endif
#endif

607
drivers/video/display/screen/lcd_hsd100pxn_for_tdw851.c → drivers/video/rockchip/screen/lcd_hsd100pxn_for_tdw851.c
View File

@@ -1,323 +1,284 @@
/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */
#include <linux/fb.h>
#include <linux/delay.h>
#include "../../rk29_fb.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include "screen.h"
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P888//OUT_D888_P666 //OUT_D888_P565
#define OUT_CLK 24000000
#define LCDC_ACLK 456000000 //29 lcdc axi DMA ƵÂÊ
/* Timing */
#define H_PW 10
#define H_BP 10
#define H_VD 480
#define H_FP 12
#define V_PW 4
#define V_BP 4
#define V_VD 800
#define V_FP 8
/* Other */
#define DCLK_POL 1
#define SWAP_RB 0
#define LCD_WIDTH 68//800 //need modify
#define LCD_HEIGHT 112//480
static struct rk29lcd_info *gLcd_info = NULL;
#define TXD_PORT gLcd_info->txd_pin
#define CLK_PORT gLcd_info->clk_pin
#define CS_PORT gLcd_info->cs_pin
#define RST_PORT gLcd_info->reset_pin
#define CS_OUT() gpio_direction_output(CS_PORT, 1)
#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH)
#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH)
#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 1)
#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH)
#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW)
#define RST_OUT() gpio_direction_output(RST_PORT, 1)
#define RST_SET() gpio_set_value(RST_PORT, GPIO_HIGH)
#define RST_CLR() gpio_set_value(RST_PORT, GPIO_LOW)
#define UDELAY_TIME 1
#define MDELAY_TIME 120
void Spi_Write_index(unsigned char index)
{
int j;
CS_CLR();
TXD_CLR(); //0
udelay(UDELAY_TIME);
CLK_CLR();
udelay(3);//
CLK_SET();
udelay(UDELAY_TIME);
TXD_CLR();
CLK_CLR();
for(j=0;j<8;j++)
{
if(index&0x80)
{
TXD_SET();
}
else
{
TXD_CLR();
}
index<<=1;
CLK_CLR();
udelay(UDELAY_TIME);
CLK_SET();
udelay(UDELAY_TIME);
}
CS_SET();
}
void Spi_Write_data(unsigned char data)
{
int j;
CS_CLR();
TXD_SET();
udelay(UDELAY_TIME);
CLK_CLR();
udelay(3);
CLK_SET();
udelay(UDELAY_TIME);
TXD_CLR();
CLK_CLR();
for(j=0;j<8;j++)
{
if(data&0x80)
{
TXD_SET();
}
else
{
TXD_CLR();
}
data<<=1;
CLK_CLR();
udelay(UDELAY_TIME);
CLK_SET();
udelay(UDELAY_TIME);
}
CS_SET();
}
void Lcd_WriteSpi_initial3(void) //HX8363A+IVO 20111128 canshu
{
//FOR IVO5.2 + HX8363-A
//Set_EXTC
printk("Lcd_WriteSpi_initial3-------------\n");
Spi_Write_index(0xB9);
Spi_Write_data(0xFF);
Spi_Write_data(0x83);
Spi_Write_data(0x63);
//Set_VCOM
Spi_Write_index(0xB6);
Spi_Write_data(0x27);//09
//Set_POWER
Spi_Write_index(0xB1);
Spi_Write_data(0x81);
Spi_Write_data(0x30);
Spi_Write_data(0x07);//04
Spi_Write_data(0x33);
Spi_Write_data(0x02);
Spi_Write_data(0x13);
Spi_Write_data(0x11);
Spi_Write_data(0x00);
Spi_Write_data(0x24);
Spi_Write_data(0x2B);
Spi_Write_data(0x3F);
Spi_Write_data(0x3F);
Spi_Write_index(0xBf); //
Spi_Write_data(0x00);
Spi_Write_data(0x10);
//Sleep Out
Spi_Write_index(0x11);
mdelay(MDELAY_TIME);
//Set COLMOD
Spi_Write_index(0x3A);
Spi_Write_data(0x70);
//Set_RGBIF
Spi_Write_index(0xB3);
Spi_Write_data(0x01);
//Set_CYC
Spi_Write_index(0xB4);
Spi_Write_data(0x08);
Spi_Write_data(0x16);
Spi_Write_data(0x5C);
Spi_Write_data(0x0B);
Spi_Write_data(0x01);
Spi_Write_data(0x1E);
Spi_Write_data(0x7B);
Spi_Write_data(0x01);
Spi_Write_data(0x4D);
//Set_PANEL
Spi_Write_index(0xCC);
//Spi_Write_data(0x01);
Spi_Write_data(0x09);
mdelay(5);
//Set Gamma 2.2
Spi_Write_index(0xE0);
Spi_Write_data(0x00);
Spi_Write_data(0x1E);
Spi_Write_data(0x63);
Spi_Write_data(0x15);
Spi_Write_data(0x11);
Spi_Write_data(0x30);
Spi_Write_data(0x0C);
Spi_Write_data(0x8F);
Spi_Write_data(0x8F);
Spi_Write_data(0x15);
Spi_Write_data(0x17);
Spi_Write_data(0xD5);
Spi_Write_data(0x56);
Spi_Write_data(0x0e);
Spi_Write_data(0x15);
Spi_Write_data(0x00);
Spi_Write_data(0x1E);
Spi_Write_data(0x63);
Spi_Write_data(0x15);
Spi_Write_data(0x11);
Spi_Write_data(0x30);
Spi_Write_data(0x0C);
Spi_Write_data(0x8F);
Spi_Write_data(0x8F);
Spi_Write_data(0x15);
Spi_Write_data(0x17);
Spi_Write_data(0xD5);
Spi_Write_data(0x56);
Spi_Write_data(0x0e);
Spi_Write_data(0x15);
mdelay(5);
//Display On
Spi_Write_index(0x29);
Spi_Write_index(0x2c);
}
static int init(void)
{
if(gLcd_info)
gLcd_info->io_init();
TXD_OUT();
CLK_OUT();
CS_OUT();
RST_CLR();
CS_SET();
CLK_SET();
mdelay(5);
RST_SET();
mdelay(2);
Lcd_WriteSpi_initial3();
return 0;
}
static int deinit(void)
{
Spi_Write_index(0x10);
if(gLcd_info)
gLcd_info->io_deinit();
return 0;
}
static int standby(u8 enable)
{
if(!enable)
init();
else
deinit();
return 0;
}
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
printk("%s\n",__func__);
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
/* Screen size */
screen->x_res = H_VD;
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin= H_FP;
screen->hsync_len = H_PW;
screen->upper_margin= V_BP;
screen->lower_margin= V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = 0;
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rg = 0;
screen->swap_gb = 0;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
/*screen->init = init;*/
screen->init = init;
screen->standby = standby;
if(lcd_info)
gLcd_info = lcd_info;
}
/* This Lcd Driver is HSD070IDW1 write by cst 2009.10.27 */
#include <linux/delay.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
/* Base */
#define SCREEN_TYPE SCREEN_RGB
#define LVDS_FORMAT LVDS_8BIT_2
#define OUT_FACE OUT_P888//OUT_D888_P666 //OUT_D888_P565
#define DCLK 24000000
#define LCDC_ACLK 456000000 //29 lcdc axi DMA ƵÂÊ
/* Timing */
#define H_PW 10
#define H_BP 10
#define H_VD 480
#define H_FP 12
#define V_PW 4
#define V_BP 4
#define V_VD 800
#define V_FP 8
/* Other */
#define DCLK_POL 1
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#define LCD_WIDTH 68//800 //need modify
#define LCD_HEIGHT 112//480
static struct rk29lcd_info *gLcd_info = NULL;
#define RK_SCREEN_INIT //this screen need to init
#define TXD_PORT gLcd_info->txd_pin
#define CLK_PORT gLcd_info->clk_pin
#define CS_PORT gLcd_info->cs_pin
#define RST_PORT gLcd_info->reset_pin
#define CS_OUT() gpio_direction_output(CS_PORT, 1)
#define CS_SET() gpio_set_value(CS_PORT, GPIO_HIGH)
#define CS_CLR() gpio_set_value(CS_PORT, GPIO_LOW)
#define CLK_OUT() gpio_direction_output(CLK_PORT, 0)
#define CLK_SET() gpio_set_value(CLK_PORT, GPIO_HIGH)
#define CLK_CLR() gpio_set_value(CLK_PORT, GPIO_LOW)
#define TXD_OUT() gpio_direction_output(TXD_PORT, 1)
#define TXD_SET() gpio_set_value(TXD_PORT, GPIO_HIGH)
#define TXD_CLR() gpio_set_value(TXD_PORT, GPIO_LOW)
#define RST_OUT() gpio_direction_output(RST_PORT, 1)
#define RST_SET() gpio_set_value(RST_PORT, GPIO_HIGH)
#define RST_CLR() gpio_set_value(RST_PORT, GPIO_LOW)
#define UDELAY_TIME 1
#define MDELAY_TIME 120
void Spi_Write_index(unsigned char index)
{
int j;
CS_CLR();
TXD_CLR(); //0
udelay(UDELAY_TIME);
CLK_CLR();
udelay(3);//
CLK_SET();
udelay(UDELAY_TIME);
TXD_CLR();
CLK_CLR();
for(j=0;j<8;j++)
{
if(index&0x80)
{
TXD_SET();
}
else
{
TXD_CLR();
}
index<<=1;
CLK_CLR();
udelay(UDELAY_TIME);
CLK_SET();
udelay(UDELAY_TIME);
}
CS_SET();
}
void Spi_Write_data(unsigned char data)
{
int j;
CS_CLR();
TXD_SET();
udelay(UDELAY_TIME);
CLK_CLR();
udelay(3);
CLK_SET();
udelay(UDELAY_TIME);
TXD_CLR();
CLK_CLR();
for(j=0;j<8;j++)
{
if(data&0x80)
{
TXD_SET();
}
else
{
TXD_CLR();
}
data<<=1;
CLK_CLR();
udelay(UDELAY_TIME);
CLK_SET();
udelay(UDELAY_TIME);
}
CS_SET();
}
void Lcd_WriteSpi_initial3(void) //HX8363A+IVO 20111128 canshu
{
//FOR IVO5.2 + HX8363-A
//Set_EXTC
printk("Lcd_WriteSpi_initial3-------------\n");
Spi_Write_index(0xB9);
Spi_Write_data(0xFF);
Spi_Write_data(0x83);
Spi_Write_data(0x63);
//Set_VCOM
Spi_Write_index(0xB6);
Spi_Write_data(0x27);//09
//Set_POWER
Spi_Write_index(0xB1);
Spi_Write_data(0x81);
Spi_Write_data(0x30);
Spi_Write_data(0x07);//04
Spi_Write_data(0x33);
Spi_Write_data(0x02);
Spi_Write_data(0x13);
Spi_Write_data(0x11);
Spi_Write_data(0x00);
Spi_Write_data(0x24);
Spi_Write_data(0x2B);
Spi_Write_data(0x3F);
Spi_Write_data(0x3F);
Spi_Write_index(0xBf); //
Spi_Write_data(0x00);
Spi_Write_data(0x10);
//Sleep Out
Spi_Write_index(0x11);
mdelay(MDELAY_TIME);
//Set COLMOD
Spi_Write_index(0x3A);
Spi_Write_data(0x70);
//Set_RGBIF
Spi_Write_index(0xB3);
Spi_Write_data(0x01);
//Set_CYC
Spi_Write_index(0xB4);
Spi_Write_data(0x08);
Spi_Write_data(0x16);
Spi_Write_data(0x5C);
Spi_Write_data(0x0B);
Spi_Write_data(0x01);
Spi_Write_data(0x1E);
Spi_Write_data(0x7B);
Spi_Write_data(0x01);
Spi_Write_data(0x4D);
//Set_PANEL
Spi_Write_index(0xCC);
//Spi_Write_data(0x01);
Spi_Write_data(0x09);
mdelay(5);
//Set Gamma 2.2
Spi_Write_index(0xE0);
Spi_Write_data(0x00);
Spi_Write_data(0x1E);
Spi_Write_data(0x63);
Spi_Write_data(0x15);
Spi_Write_data(0x11);
Spi_Write_data(0x30);
Spi_Write_data(0x0C);
Spi_Write_data(0x8F);
Spi_Write_data(0x8F);
Spi_Write_data(0x15);
Spi_Write_data(0x17);
Spi_Write_data(0xD5);
Spi_Write_data(0x56);
Spi_Write_data(0x0e);
Spi_Write_data(0x15);
Spi_Write_data(0x00);
Spi_Write_data(0x1E);
Spi_Write_data(0x63);
Spi_Write_data(0x15);
Spi_Write_data(0x11);
Spi_Write_data(0x30);
Spi_Write_data(0x0C);
Spi_Write_data(0x8F);
Spi_Write_data(0x8F);
Spi_Write_data(0x15);
Spi_Write_data(0x17);
Spi_Write_data(0xD5);
Spi_Write_data(0x56);
Spi_Write_data(0x0e);
Spi_Write_data(0x15);
mdelay(5);
//Display On
Spi_Write_index(0x29);
Spi_Write_index(0x2c);
}
static int rk_lcd_init(void)
{
if(gLcd_info)
gLcd_info->io_init();
TXD_OUT();
CLK_OUT();
CS_OUT();
RST_CLR();
CS_SET();
CLK_SET();
mdelay(5);
RST_SET();
mdelay(2);
Lcd_WriteSpi_initial3();
return 0;
}
static int deinit(void)
{
Spi_Write_index(0x10);
if(gLcd_info)
gLcd_info->io_deinit();
return 0;
}
static int rk_lcd_standby(u8 enable)
{
if(!enable)
rk_lcd_init();
else
deinit();
return 0;
}

0
drivers/video/display/screen/lcd_hsd800x480.c → drivers/video/rockchip/screen/lcd_hsd800x480.c
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36
drivers/video/rockchip/screen/lcd_hv070wsa.c Normal file
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@@ -0,0 +1,36 @@
#ifndef __LCD_HV070WSA__
#define __LCD_HV070WSA__
/* Base */
#define SCREEN_TYPE SCREEN_RGB
#define LVDS_FORMAT LVDS_8BIT_2
#define OUT_FACE OUT_P888
#define DCLK 50000000
#define LCDC_ACLK 500000000//312000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 100
#define H_BP 100
#define H_VD 1024
#define H_FP 120
#define V_PW 10
#define V_BP 10
#define V_VD 600
#define V_FP 15
#define LCD_WIDTH 202
#define LCD_HEIGHT 152
/* Other */
#define DCLK_POL 0
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#endif

0
drivers/video/display/screen/lcd_hx8357.c → drivers/video/rockchip/screen/lcd_hx8357.c
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0
drivers/video/display/screen/lcd_ili9803_cpt4_3.c → drivers/video/rockchip/screen/lcd_ili9803_cpt4_3.c Executable file → Normal file
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0
drivers/video/display/screen/lcd_ips1p5680_v1_e.c → drivers/video/rockchip/screen/lcd_ips1p5680_v1_e.c
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0
drivers/video/display/screen/lcd_mcu_tft480800_25_e.c → drivers/video/rockchip/screen/lcd_mcu_tft480800_25_e.c
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186
drivers/video/rockchip/screen/lcd_mq0801d.c Normal file
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@@ -0,0 +1,186 @@
#ifndef __LCD_H__
#define __LCD_H__
#if defined(CONFIG_RK610_LVDS)
#include "../transmitter/rk610_lcd.h"
#endif
#ifdef CONFIG_RK610_LVDS
#define SCREEN_TYPE SCREEN_LVDS
#else
#define SCREEN_TYPE SCREEN_RGB
#endif
#define LVDS_FORMAT LVDS_8BIT_1
#define OUT_FACE OUT_P888
#define DCLK 67000000 // 65000000
#define LCDC_ACLK 312000000//312000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 10
#define H_BP 10
#define H_VD 1024
#define H_FP 300
#define V_PW 4
#define V_BP 4
#define V_VD 768
#define V_FP 30
#define LCD_WIDTH 162
#define LCD_HEIGHT 121
/* Other */
#ifdef CONFIG_RK610_LVDS
#define DCLK_POL 1
#else
#define DCLK_POL 0
#endif
#define SWAP_RB 0
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#define USE_RK_DSP_LUT
int dsp_lut[256] ={
0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707,
0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f,
0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717,
0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f,
0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727,
0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f,
0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737,
0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f,
0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747,
0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f,
0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757,
0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f,
0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767,
0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f,
0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777,
0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f,
0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787,
0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f,
0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797,
0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f,
0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7,
0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf,
0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7,
0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf,
0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7,
0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf,
0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7,
0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf,
0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7,
0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef,
0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7,
0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff,
};
#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS)
/* scaler Timing */
//1920*1080*60
#define S_OUT_CLK SCALE_RATE(148500000,54000000)
#define S_H_PW 20
#define S_H_BP 20
#define S_H_VD 1024
#define S_H_FP 61
#define S_V_PW 10
#define S_V_BP 10
#define S_V_VD 768
#define S_V_FP 12
#define S_H_ST 0
#define S_V_ST 12
//1920*1080*50
#define S1_OUT_CLK SCALE_RATE(148500000,53035713)
#define S1_H_PW 10
#define S1_H_BP 10
#define S1_H_VD 1024
#define S1_H_FP 282
#define S1_V_PW 10
#define S1_V_BP 10
#define S1_V_VD 768
#define S1_V_FP 11
#define S1_H_ST 1145
#define S1_V_ST 11
//1280*720*60
#define S2_OUT_CLK SCALE_RATE(74250000,54000000)
#define S2_H_PW 10
#define S2_H_BP 10
#define S2_H_VD 1024
#define S2_H_FP 81
#define S2_V_PW 8
#define S2_V_BP 7
#define S2_V_VD 768
#define S2_V_FP 15
#define S2_H_ST 0
#define S2_V_ST 12
//1280*720*50
#define S3_OUT_CLK SCALE_RATE(74250000,52117790)
#define S3_H_PW 10
#define S3_H_BP 10
#define S3_H_VD 1024
#define S3_H_FP 259
#define S3_V_PW 10
#define S3_V_BP 10
#define S3_V_VD 768
#define S3_V_FP 8
#define S3_H_ST 1040
#define S3_V_ST 7
//720*576*50
#define S4_OUT_CLK SCALE_RATE(27000000,52125000)
#define S4_H_PW 10
#define S4_H_BP 10
#define S4_H_VD 1024
#define S4_H_FP 207
#define S4_V_PW 15
#define S4_V_BP 12
#define S4_V_VD 768
#define S4_V_FP 10
#define S4_H_ST 417
#define S4_V_ST 25
//720*480*60
#define S5_OUT_CLK SCALE_RATE(27000000,58153847) //m=100 n=9 no=4
#define S5_H_PW 10
#define S5_H_BP 10
#define S5_H_VD 1024
#define S5_H_FP 111
#define S5_V_PW 4
#define S5_V_BP 3
#define S5_V_VD 768
#define S5_V_FP 31
#define S5_H_ST 693
#define S5_V_ST 35
#define S_DCLK_POL 1
#endif
#endif

1600
drivers/video/rockchip/screen/lcd_nt35510.c Normal file
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File diff suppressed because it is too large Load Diff

0
drivers/video/display/screen/lcd_nt35580.c → drivers/video/rockchip/screen/lcd_nt35580.c
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0
drivers/video/display/screen/lcd_nt35582.c → drivers/video/rockchip/screen/lcd_nt35582.c
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41
drivers/video/rockchip/screen/lcd_null.c Normal file
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@@ -0,0 +1,41 @@
#ifndef __LCD_NULL__
#define __LCD_NULL__
/* Base */
#define SCREEN_TYPE SCREEN_NULL
#define LVDS_FORMAT LVDS_8BIT_1
#define OUT_FACE 0
#define DCLK 0
#define LCDC_ACLK 0 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 0
#define H_BP 0
#define H_VD 0
#define H_FP 0
#define V_PW 0
#define V_BP 0
#define V_VD 0
#define V_FP 0
#define LCD_WIDTH 0 //need modify
#define LCD_HEIGHT 0
/* Other */
#define DCLK_POL 0
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_DUMMY 0
#define SWAP_GB 0
#define SWAP_RG 0
#endif

0
drivers/video/display/screen/lcd_rgb_tft480800_25_e.c → drivers/video/rockchip/screen/lcd_rgb_tft480800_25_e.c
View File

0
drivers/video/display/screen/lcd_rk2928.c → drivers/video/rockchip/screen/lcd_rk2928.c Executable file → Normal file
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0
drivers/video/display/screen/lcd_s1d13521.c → drivers/video/rockchip/screen/lcd_s1d13521.c
View File

40
drivers/video/rockchip/screen/lcd_td043mgea1.c Normal file
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@@ -0,0 +1,40 @@
#ifndef __LCD_TD043MGEA__
#define __LCD_TD043MGEA__
/* Base */
#define SCREEN_TYPE SCREEN_RGB
#define LVDS_FORMAT LVDS_8BIT_2
#define OUT_FACE OUT_P888
#define DCLK 27000000
#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 10
#define H_BP 206
#define H_VD 800
#define H_FP 40
#define V_PW 10
#define V_BP 25
#define V_VD 480
#define V_FP 10
#define LCD_WIDTH 800 //need modify
#define LCD_HEIGHT 480
/* Other */
#define DCLK_POL 0
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_DUMMY 0
#define SWAP_GB 0
#define SWAP_RG 0
#endif

0
drivers/video/display/screen/lcd_tj048nc01ca.c → drivers/video/rockchip/screen/lcd_tj048nc01ca.c
View File

0
drivers/video/display/screen/lcd_tl5001_mipi.c → drivers/video/rockchip/screen/lcd_tl5001_mipi.c
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0
drivers/video/display/screen/lcd_tx23d88vm.c → drivers/video/rockchip/screen/lcd_tx23d88vm.c
View File

0
drivers/video/display/screen/lcd_wy_800x480.c → drivers/video/rockchip/screen/lcd_wy_800x480.c Executable file → Normal file
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282
drivers/video/display/screen/lcd_hdmi_800x480.c → drivers/video/rockchip/screen/rk_screen.c
View File

@@ -1,149 +1,30 @@
#include <linux/delay.h>
#include <mach/gpio.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include <linux/rk_fb.h>
#include "lcd.h"
#if defined(CONFIG_RK_HDMI)
#include "../../rockchip/hdmi/rk_hdmi.h"
#endif
#ifdef CONFIG_RK610_LVDS
#include "../transmitter/rk610_lcd.h"
#include "../hdmi/rk_hdmi.h"
#endif
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P888
#define OUT_CLK 33000000
#define LCDC_ACLK 150000000//312000000 //29 lcdc axi DMA ƵÂÊ
/* Timing */
#define H_PW 1
#define H_BP 88
#define H_VD 800
#define H_FP 40
#define V_PW 3
#define V_BP 29
#define V_VD 480
#define V_FP 13
#define LCD_WIDTH 154
#define LCD_HEIGHT 85
/* scaler Timing */
//1920*1080*60
#define S_OUT_CLK SCALE_RATE(148500000,33000000)
#define S_H_PW 1
#define S_H_BP 88
#define S_H_VD 800
#define S_H_FP 211
#define S_V_PW 3
#define S_V_BP 10
#define S_V_VD 480
#define S_V_FP 7
#define S_H_ST 244
#define S_V_ST 11
//1920*1080*50
#define S1_OUT_CLK SCALE_RATE(148500000,30375000)
#define S1_H_PW 1
#define S1_H_BP 88
#define S1_H_VD 800
#define S1_H_FP 326
#define S1_V_PW 3
#define S1_V_BP 9
#define S1_V_VD 480
#define S1_V_FP 8
#define S1_H_ST 270
#define S1_V_ST 13
//1280*720*60
#define S2_OUT_CLK SCALE_RATE(74250000,33000000)
#define S2_H_PW 1
#define S2_H_BP 88
#define S2_H_VD 800
#define S2_H_FP 211
#define S2_V_PW 3
#define S2_V_BP 9
#define S2_V_VD 480
#define S2_V_FP 8
#define S2_H_ST 0
#define S2_V_ST 8
//1280*720*50
#define S3_OUT_CLK SCALE_RATE(74250000,30375000)
#define S3_H_PW 1
#define S3_H_BP 88
#define S3_H_VD 800
#define S3_H_FP 326
#define S3_V_PW 3
#define S3_V_BP 9
#define S3_V_VD 480
#define S3_V_FP 8
#define S3_H_ST 0
#define S3_V_ST 8
//720*576*50
#define S4_OUT_CLK SCALE_RATE(27000000,30000000)
#define S4_H_PW 1
#define S4_H_BP 88
#define S4_H_VD 800
#define S4_H_FP 263
#define S4_V_PW 3
#define S4_V_BP 9
#define S4_V_VD 480
#define S4_V_FP 28
#define S4_H_ST 0
#define S4_V_ST 33
//720*480*60
#define S5_OUT_CLK SCALE_RATE(27000000,31500000)
#define S5_H_PW 1
#define S5_H_BP 88
#define S5_H_VD 800
#define S5_H_FP 112
#define S5_V_PW 3
#define S5_V_BP 9
#define S5_V_VD 480
#define S5_V_FP 28
#define S5_H_ST 0
#define S5_V_ST 29
#define S_DCLK_POL 0
/* Other */
#define DCLK_POL 0
#define DEN_POL 0
#define VSYNC_POL 0
#define HSYNC_POL 0
#define SWAP_RB 0
#define SWAP_RG 0
#define SWAP_GB 0
#if ( defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) ) || defined(CONFIG_HDMI_DUAL_DISP)
// if we use one lcdc with jetta for dual display,we need these configration
#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF) && defined(CONFIG_RK_HDMI)
static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
{
#if defined(CONFIG_RK610_LVDS)
screen->s_clk_inv = S_DCLK_POL;
screen->s_den_inv = 0;
screen->s_hv_sync_inv = 0;
switch(hdmi_resolution){
#endif
switch(hdmi_resolution)
{
case HDMI_1920x1080p_60Hz:
/* Scaler Timing */
/* Scaler Timing */
#if defined(CONFIG_RK610_LVDS)
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S_OUT_CLK;
screen->s_hsync_len = S_H_PW;
@@ -155,9 +36,21 @@ static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
screen->s_vsync_len = S_V_PW;
screen->s_hsync_st = S_H_ST;
screen->s_vsync_st = S_V_ST;
#endif
//bellow are for JettaB
#if defined(CONFIG_RK616_LVDS)
screen->pll_cfg_val = S_PLL_CFG_VAL;
screen->frac = S_FRAC;
screen->scl_vst = S_SCL_VST;
screen->scl_hst = S_SCL_HST;
screen->vif_vst = S_VIF_VST;
screen->vif_hst = S_VIF_HST;
#endif
break;
case HDMI_1920x1080p_50Hz:
/* Scaler Timing */
/* Scaler Timing */
#if defined(CONFIG_RK610_LVDS)
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S1_OUT_CLK;
screen->s_hsync_len = S1_H_PW;
@@ -169,9 +62,20 @@ static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
screen->s_vsync_len = S1_V_PW;
screen->s_hsync_st = S1_H_ST;
screen->s_vsync_st = S1_V_ST;
#endif
#if defined(CONFIG_RK616_LVDS)
screen->pll_cfg_val = S1_PLL_CFG_VAL;
screen->frac = S1_FRAC;
screen->scl_vst = S1_SCL_VST;
screen->scl_hst = S1_SCL_HST;
screen->vif_vst = S1_VIF_VST;
screen->vif_hst = S1_VIF_HST;
#endif
break;
case HDMI_1280x720p_60Hz:
/* Scaler Timing */
/* Scaler Timing */
#if defined(CONFIG_RK610_LVDS)
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S2_OUT_CLK;
screen->s_hsync_len = S2_H_PW;
@@ -183,9 +87,20 @@ static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
screen->s_vsync_len = S2_V_PW;
screen->s_hsync_st = S2_H_ST;
screen->s_vsync_st = S2_V_ST;
#endif
#if defined(CONFIG_RK616_LVDS)
screen->pll_cfg_val = S2_PLL_CFG_VAL;
screen->frac = S2_FRAC;
screen->scl_vst = S2_SCL_VST;
screen->scl_hst = S2_SCL_HST;
screen->vif_vst = S2_VIF_VST;
screen->vif_hst = S2_VIF_HST;
#endif
break;
case HDMI_1280x720p_50Hz:
/* Scaler Timing */
/* Scaler Timing */
#if defined(CONFIG_RK610_LVDS)
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S3_OUT_CLK;
screen->s_hsync_len = S3_H_PW;
@@ -197,10 +112,21 @@ static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
screen->s_vsync_len = S3_V_PW;
screen->s_hsync_st = S3_H_ST;
screen->s_vsync_st = S3_V_ST;
#endif
#if defined(CONFIG_RK616_LVDS)
screen->pll_cfg_val = S3_PLL_CFG_VAL;
screen->frac = S3_FRAC;
screen->scl_vst = S3_SCL_VST;
screen->scl_hst = S3_SCL_HST;
screen->vif_vst = S3_VIF_VST;
screen->vif_hst = S3_VIF_HST;
#endif
break;
case HDMI_720x576p_50Hz_4_3:
case HDMI_720x576p_50Hz_16_9:
/* Scaler Timing */
/* Scaler Timing */
#if defined(CONFIG_RK610_LVDS)
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S4_OUT_CLK;
screen->s_hsync_len = S4_H_PW;
@@ -212,10 +138,22 @@ static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
screen->s_vsync_len = S4_V_PW;
screen->s_hsync_st = S4_H_ST;
screen->s_vsync_st = S4_V_ST;
#endif
#if defined(CONFIG_RK616_LVDS)
screen->pll_cfg_val = S4_PLL_CFG_VAL;
screen->frac = S4_FRAC;
screen->scl_vst = S4_SCL_VST;
screen->scl_hst = S4_SCL_HST;
screen->vif_vst = S4_VIF_VST;
screen->vif_hst = S4_VIF_HST;
#endif
break;
case HDMI_720x480p_60Hz_16_9:
case HDMI_720x480p_60Hz_4_3:
/* Scaler Timing */
/* Scaler Timing */
#if defined(CONFIG_RK610_LVDS)
screen->hdmi_resolution = hdmi_resolution;
screen->s_pixclock = S5_OUT_CLK;
screen->s_hsync_len = S5_H_PW;
@@ -227,35 +165,49 @@ static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
screen->s_vsync_len = S5_V_PW;
screen->s_hsync_st = S5_H_ST;
screen->s_vsync_st = S5_V_ST;
#endif
#if defined(CONFIG_RK616_LVDS)
screen->pll_cfg_val = S5_PLL_CFG_VAL;
screen->frac = S5_FRAC;
screen->scl_vst = S5_SCL_VST;
screen->scl_hst = S5_SCL_HST;
screen->vif_vst = S5_VIF_VST;
screen->vif_hst = S5_VIF_HST;
#endif
break;
default :
printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution);
return -1;
break;
printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution);
return -1;
break;
}
return 0;
}
#else
static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution){return 0;}
#define set_scaler_info NULL
#endif
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
{
/* screen type & face */
screen->type = OUT_TYPE;
screen->face = OUT_FACE;
/* Screen size */
screen->x_res = H_VD;
#if defined(RK_USE_SCREEN_ID)
set_lcd_info_by_id(screen,lcd_info);
#else
screen->type = SCREEN_TYPE;
screen->face = OUT_FACE;
screen->lvds_format = LVDS_FORMAT; //lvds data format
screen->x_res = H_VD; //screen resolution
screen->y_res = V_VD;
screen->width = LCD_WIDTH;
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->lcdc_aclk = LCDC_ACLK; // Timing
screen->pixclock = DCLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;
@@ -263,26 +215,37 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
screen->lower_margin = V_FP;
screen->vsync_len = V_PW;
/* Pin polarity */
screen->pin_hsync = HSYNC_POL;
screen->pin_hsync = HSYNC_POL; //Pin polarity
screen->pin_vsync = VSYNC_POL;
screen->pin_den = DEN_POL;
screen->pin_dclk = DCLK_POL;
/* Swap rule */
screen->swap_rb = SWAP_RB;
screen->swap_rb = SWAP_RB; // Swap rule
screen->swap_rg = SWAP_RG;
screen->swap_gb = SWAP_GB;
screen->swap_delta = 0;
screen->swap_dumy = 0;
/* Operation function*/
screen->init = NULL;
screen->standby = NULL;
screen->sscreen_get = set_scaler_info;
#ifdef CONFIG_RK610_LVDS
screen->sscreen_set = rk610_lcd_scaler_set_param;
#if defined(RK_SCREEN_INIT) //some screen need to init by spi or i2c
screen->init = rk_lcd_init;
screen->standby = rk_lcd_standby;
if(lcd_info)
gLcd_info = lcd_info;
#endif
#if defined(USE_RK_DSP_LUT)
screen->dsp_lut = dsp_lut;
#endif
#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)
screen->sscreen_get = set_scaler_info;
#endif
#endif
}
size_t get_fb_size(void)
@@ -295,4 +258,3 @@ size_t get_fb_size(void)
#endif
return ALIGN(size,SZ_1M);
}

0
drivers/video/display/screen/s1d13521.h → drivers/video/rockchip/screen/s1d13521.h Executable file → Normal file
View File

0
drivers/video/display/screen/s1d13521ioctl.h → drivers/video/rockchip/screen/s1d13521ioctl.h Executable file → Normal file
View File

21
drivers/video/display/transmitter/Kconfig → drivers/video/rockchip/transmitter/Kconfig
View File

@@ -1,39 +1,44 @@
choice
depends on DISPLAY_SUPPORT
prompt "Display interface transmitter Select"
config NO_TRSM
bool "no transmitter needed"
menuconfig RK_TRSM
bool "RockChip display transmitter support"
depends on FB_ROCKCHIP
config RK2928_LVDS
bool "RK2928、RK2926 lvds transmitter support"
depends on ARCH_RK2928 && RK_TRSM
config RK610_LVDS
bool "RK610(Jetta) lvds transmitter support"
depends on MFD_RK610
depends on MFD_RK610 && RK_TRSM
help
Support Jetta(RK610) to output LCD1 and LVDS.
config RK616_LVDS
bool "RK616(JettaB) lvds,lcd,scaler vido interface support"
depends on MFD_RK616
depends on MFD_RK616 && RK_TRSM
help
RK616(Jetta B) LVDS,LCD,scaler transmitter support.
config DP_ANX6345
bool "RGB to Display Port transmitter anx6345,anx9804,anx9805 support"
depends on RK_TRSM
config DP501
bool"RGB to Display Port transmitter dp501 support"
depends on RK_TRSM
config TC358768_RGB2MIPI
bool "toshiba TC358768 RGB to MIPI DSI"
depends on RK_TRSM
help
"a chip that change RGB interface parallel signal into DSI serial signal"
config SSD2828_RGB2MIPI
bool "solomon SSD2828 RGB to MIPI DSI"
depends on RK_TRSM
help
"a chip that change RGB interface parallel signal into DSI serial signal"
endchoice

1
drivers/video/display/transmitter/Makefile → drivers/video/rockchip/transmitter/Makefile
View File

@@ -1,6 +1,7 @@
#
# Makefile for display transmitter like lvds edp mipi
#
obj-$(CONFIG_RK2928_LVDS) += rk2928_lvds.o
obj-$(CONFIG_RK610_LVDS) += rk610_lcd.o
obj-$(CONFIG_RK616_LVDS) += rk616_lvds.o
obj-$(CONFIG_TC358768_RGB2MIPI) += mipi_dsi.o tc358768.o

0
drivers/video/display/transmitter/dp501.c → drivers/video/rockchip/transmitter/dp501.c
View File

0
drivers/video/display/transmitter/dp_anx6345.c → drivers/video/rockchip/transmitter/dp_anx6345.c Executable file → Normal file
View File

0
drivers/video/display/transmitter/mipi_dsi.c → drivers/video/rockchip/transmitter/mipi_dsi.c
View File

0
drivers/video/display/transmitter/mipi_dsi.h → drivers/video/rockchip/transmitter/mipi_dsi.h
View File

0
drivers/video/rockchip/lvds/rk_lvds.c → drivers/video/rockchip/transmitter/rk2928_lvds.c
View File

0
drivers/video/rockchip/lvds/rk_lvds.h → drivers/video/rockchip/transmitter/rk2928_lvds.h
View File

0
drivers/video/display/transmitter/rk610_lcd.c → drivers/video/rockchip/transmitter/rk610_lcd.c
View File

0
drivers/video/display/transmitter/rk610_lcd.h → drivers/video/rockchip/transmitter/rk610_lcd.h
View File

0
drivers/video/display/transmitter/rk616_lvds.c → drivers/video/rockchip/transmitter/rk616_lvds.c
View File

0
drivers/video/display/transmitter/rk616_lvds.h → drivers/video/rockchip/transmitter/rk616_lvds.h
View File

0
drivers/video/display/transmitter/ssd2828.c → drivers/video/rockchip/transmitter/ssd2828.c
View File

0
drivers/video/display/transmitter/tc358768.c → drivers/video/rockchip/transmitter/tc358768.c
View File

3
drivers/video/display/tve/Kconfig → drivers/video/rockchip/tve/Kconfig
View File

@@ -1,13 +1,14 @@
config RK610_TVOUT
bool "RK610(Jetta) tvout support"
depends on MFD_RK610
default y if MFD_RK610
default n
help
Support Jetta(RK610) to output YPbPr and CVBS.
config RK610_TVOUT_YPbPr
bool "support YPbPr output"
depends on RK610_TVOUT
config RK610_TVOUT_CVBS
bool "support CVBS output"
depends on RK610_TVOUT

Some files were not shown because too many files have changed in this diff Show More