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arm: dts: tl1: add initial device tree for tl1

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PD#172587: arm: dts: tl1: add initial device tree for tl1

Change-Id: I17734ee00d88a84ff19bf17f8edf519e3ed2f0e4
Signed-off-by: Bo Yang <bo.yang@amlogic.com>
This commit is contained in:
Bo Yang
2018-09-27 17:14:42 +08:00
committed by Jianxin Pan
parent 565f193b8a
commit ae2e8e908a
4 changed files with 1465 additions and 0 deletions
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998
arch/arm/boot/dts/amlogic/mesontl1.dtsi Normal file
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/*
* arch/arm/boot/dts/amlogic/mesontl1.dtsi
*
* Copyright (C) 2018 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/meson-tl1-gpio.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/meson_rc.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pwm/meson.h>
#include <dt-bindings/clock/amlogic,tl1-clkc.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
cpus:cpus {
#address-cells = <1>;
#size-cells = <0>;
#cooling-cells = <2>;/* min followed by max */
CPU0:cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x0>;
//timer=<&timer_a>;
enable-method = "psci";
clocks = <&scpi_dvfs 0>;
clock-names = "cpu-cluster.0";
//cpu-idle-states = <&SYSTEM_SLEEP_0>;
};
CPU1:cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x1>;
//timer=<&timer_b>;
enable-method = "psci";
clocks = <&scpi_dvfs 0>;
clock-names = "cpu-cluster.0";
//cpu-idle-states = <&SYSTEM_SLEEP_0>;
};
CPU2:cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x2>;
//timer=<&timer_c>;
enable-method = "psci";
clocks = <&scpi_dvfs 0>;
clock-names = "cpu-cluster.0";
//cpu-idle-states = <&SYSTEM_SLEEP_0>;
};
CPU3:cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x0 0x3>;
//timer=<&timer_d>;
enable-method = "psci";
clocks = <&scpi_dvfs 0>;
clock-names = "cpu-cluster.0";
//cpu-idle-states = <&SYSTEM_SLEEP_0>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 0xff01>,
<GIC_PPI 14 0xff01>,
<GIC_PPI 11 0xff01>,
<GIC_PPI 10 0xff01>;
};
timer_bc {
compatible = "arm, meson-bc-timer";
reg = <0xffd0f190 0x4 0xffd0f194 0x4>;
timer_name = "Meson TimerF";
clockevent-rating =<300>;
clockevent-shift =<20>;
clockevent-features =<0x23>;
interrupts = <0 60 1>;
bit_enable =<16>;
bit_mode =<12>;
bit_resolution =<0>;
};
gic: interrupt-controller@2c001000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0xffc01000 0x1000>,
<0xffc02000 0x0100>;
interrupts = <GIC_PPI 9 0xf04>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
scpi_clocks {
compatible = "arm, scpi-clks";
scpi_dvfs: scpi_clocks@0 {
compatible = "arm, scpi-clk-indexed";
#clock-cells = <1>;
clock-indices = <0>;
clock-output-names = "vcpu";
};
};
secmon {
compatible = "amlogic, secmon";
memory-region = <&secmon_reserved>;
in_base_func = <0x82000020>;
out_base_func = <0x82000021>;
reserve_mem_size = <0x00300000>;
};
securitykey {
compatible = "amlogic, securitykey";
status = "okay";
storage_query = <0x82000060>;
storage_read = <0x82000061>;
storage_write = <0x82000062>;
storage_tell = <0x82000063>;
storage_verify = <0x82000064>;
storage_status = <0x82000065>;
storage_list = <0x82000067>;
storage_remove = <0x82000068>;
storage_in_func = <0x82000023>;
storage_out_func = <0x82000024>;
storage_block_func = <0x82000025>;
storage_size_func = <0x82000027>;
storage_set_enctype = <0x8200006A>;
storage_get_enctype = <0x8200006B>;
storage_version = <0x8200006C>;
};
cpu_iomap {
compatible = "amlogic, iomap";
#address-cells = <1>;
#size-cells = <1>;
ranges;
io_cbus_base {
reg = <0xffd00000 0x101000>;
};
io_apb_base {
reg = <0xffe01000 0x19f000>;
};
io_aobus_base {
reg = <0xff800000 0x100000>;
};
io_vapb_base {
reg = <0xff900000 0x200000>;
};
io_hiu_base {
reg = <0xff63c000 0x2000>;
};
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
meson_suspend: pm {
compatible = "amlogic, pm";
/*gxbaby-suspend;*/
status = "okay";
reg = <0xff8000a8 0x4>,
<0xff80023c 0x4>;
};
cpuinfo {
compatible = "amlogic, cpuinfo";
status = "okay";
cpuinfo_cmd = <0x82000044>;
};
reboot {
compatible = "amlogic,reboot";
sys_reset = <0x84000009>;
sys_poweroff = <0x84000008>;
};
ram-dump {
compatible = "amlogic, ram_dump";
status = "okay";
};
vpu {
compatible = "amlogic, vpu-tl1";
status = "okay";
clocks = <&clkc CLKID_VAPB_MUX>,
<&clkc CLKID_VPU_INTR>,
<&clkc CLKID_VPU_P0_COMP>,
<&clkc CLKID_VPU_P1_COMP>,
<&clkc CLKID_VPU_MUX>;
clock-names = "vapb_clk",
"vpu_intr_gate",
"vpu_clk0",
"vpu_clk1",
"vpu_clk";
clk_level = <7>;
/* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
/* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */
};
pinctrl_aobus: pinctrl@ff800014 {
compatible = "amlogic,meson-tl1-aobus-pinctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio_ao: ao-bank@ff800014 {
reg = <0xff800014 0x8>,
<0xff800024 0x14>,
<0xff80001c 0x8>;
reg-names = "mux", "gpio", "drive-strength";
gpio-controller;
#gpio-cells = <2>;
};
};
pinctrl_periphs: pinctrl@ff6346c0 {
compatible = "amlogic,meson-tl1-periphs-pinctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio: banks@ff6346c0 {
reg = <0xff6346c0 0x40>,
<0xff6344e8 0x18>,
<0xff634520 0x18>,
<0xff634440 0x4c>,
<0xff634740 0x1c>;
reg-names = "mux",
"pull",
"pull-enable",
"gpio",
"drive-strength";
gpio-controller;
#gpio-cells = <2>;
};
};
wdt: watchdog@0xffd0f0d0 {
compatible = "amlogic,meson-tl1-wdt";
status = "okay";
reg = <0xffd0f0d0 0x10>;
clock-names = "xtal";
clocks = <&xtal>;
};
jtag {
compatible = "amlogic, jtag";
status = "disabled";
select = "apao"; /* disable/apao/apee */
jtagao-gpios = <&gpio_ao GPIOAO_6 0
&gpio_ao GPIOAO_7 0
&gpio_ao GPIOAO_8 0
&gpio_ao GPIOAO_9 0>;
jtagee-gpios = <&gpio GPIOC_0 0
&gpio GPIOC_1 0
&gpio GPIOC_4 0
&gpio GPIOC_5 0>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
hiubus: hiubus@ff63c000 {
compatible = "simple-bus";
reg = <0xff63c000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xff63c000 0x2000>;
clkc: clock-controller@0 {
compatible = "amlogic,tl1-clkc";
#clock-cells = <1>;
reg = <0x0 0x3fc>;
};
};/* end of hiubus*/
cbus: cbus@ffd00000 {
compatible = "simple-bus";
reg = <0xffd00000 0x27000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xffd00000 0x27000>;
clk-measure@18004 {
compatible = "amlogic,tl1-measure";
reg = <0x18004 0x4 0x1800c 0x4>;
};
i2c0: i2c@1f000 {
compatible = "amlogic,meson-i2c";
status = "disabled";
reg = <0x1f000 0x20>;
interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 91 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C>;
clock-frequency = <100000>;
};
i2c1: i2c@1e000 {
compatible = "amlogic,meson-i2c";
status = "disabled";
reg = <0x1e000 0x20>;
interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 92 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C>;
clock-frequency = <100000>;
};
i2c2: i2c@1d000 {
compatible = "amlogic,meson-i2c";
status = "disabled";
reg = <0x1d000 0x20>;
interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 94 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C>;
clock-frequency = <100000>;
};
i2c3: i2c@1c000 {
compatible = "amlogic,meson-i2c";
status = "disabled";
reg = <0x1c000 0x20>;
interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 95 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C>;
clock-frequency = <100000>;
};
gpio_intc: interrupt-controller@f080 {
compatible = "amlogic,meson-gpio-intc",
"amlogic,meson-tl1-gpio-intc";
reg = <0xf080 0x10>;
interrupt-controller;
#interrupt-cells = <2>;
amlogic,channel-interrupts =
<64 65 66 67 68 69 70 71>;
status = "okay";
};
pwm_ab: pwm@1b000 {
compatible = "amlogic,tl1-ee-pwm";
reg = <0x1b000 0x20>;
#pwm-cells = <3>;
clocks = <&xtal>,
<&xtal>,
<&xtal>,
<&xtal>;
clock-names = "clkin0",
"clkin1",
"clkin2",
"clkin3";
/* default xtal 24m clkin0-clkin2 and
* clkin1-clkin3 should be set the same
*/
status = "disabled";
};
pwm_cd: pwm@1a000 {
compatible = "amlogic,tl1-ee-pwm";
reg = <0x1a000 0x20>;
#pwm-cells = <3>;
clocks = <&xtal>,
<&xtal>,
<&xtal>,
<&xtal>;
clock-names = "clkin0",
"clkin1",
"clkin2",
"clkin3";
status = "disabled";
};
pwm_ef: pwm@19000 {
compatible = "amlogic,tl1-ee-pwm";
reg = <0x19000 0x20>;
#pwm-cells = <3>;
clocks = <&xtal>,
<&xtal>,
<&xtal>,
<&xtal>;
clock-names = "clkin0",
"clkin1",
"clkin2",
"clkin3";
status = "disabled";
};
spicc0: spi@13000 {
compatible = "amlogic,meson-tl1-spicc",
"amlogic,meson-g12a-spicc";
reg = <0x13000 0x44>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC0>,
<&clkc CLKID_SPICC0_COMP>;
clock-names = "core", "comp";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spicc1: spi@15000 {
compatible = "amlogic,meson-tl1-spicc",
"amlogic,meson-g12a-spicc";
reg = <0x15000 0x44>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC1>,
<&clkc CLKID_SPICC1_COMP>;
clock-names = "core", "comp";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
aobus: aobus@ff800000 {
compatible = "simple-bus";
reg = <0xff800000 0xb000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xff800000 0xb000>;
cpu_version {
reg = <0x220 0x4>;
};
aoclkc: clock-controller@0 {
compatible = "amlogic,tl1-aoclkc";
#clock-cells = <1>;
reg = <0x0 0x1000>;
};
pwm_AO_ab: pwm@7000 {
compatible = "amlogic,tl1-ao-pwm";
reg = <0x7000 0x20>;
#pwm-cells = <3>;
clocks = <&xtal>,
<&xtal>,
<&xtal>,
<&xtal>;
clock-names = "clkin0",
"clkin1",
"clkin2",
"clkin3";
status = "disabled";
};
pwm_AO_cd: pwm@2000 {
compatible = "amlogic,tl1-ao-pwm";
reg = <0x2000 0x20>;
#pwm-cells = <3>;
clocks = <&xtal>,
<&xtal>,
<&xtal>,
<&xtal>;
clock-names = "clkin0",
"clkin1",
"clkin2",
"clkin3";
status = "disabled";
};
uart_AO: serial@3000 {
compatible = "amlogic, meson-uart";
reg = <0x3000 0x18>;
interrupts = <0 193 1>;
status = "okay";
clocks = <&xtal>;
clock-names = "clk_uart";
xtal_tick_en = <1>;
fifosize = < 64 >;
//pinctrl-names = "default";
//pinctrl-0 = <&ao_a_uart_pins>;
/* 0 not support; 1 support */
support-sysrq = <0>;
};
remote: rc@8040 {
compatible = "amlogic, aml_remote";
reg = <0x8040 0x44>,
<0x8000 0x20>;
status = "okay";
protocol = <REMOTE_TYPE_NEC>;
interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&remote_pins>;
map = <&custom_maps>;
max_frame_time = <200>;
};
i2c_AO: i2c@5000 {
compatible = "amlogic,meson-i2c";
status = "disabled";
reg = <0x05000 0x20>;
interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 201 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C>;
clock-frequency = <100000>;
};
i2c_AO_slave:i2c_slave@6000 {
compatible = "amlogic, meson-i2c-slave";
status = "disabled";
reg = <0x0 0x6000 0x0 0x20>;
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
pinctrl-names="default";
pinctrl-0=<&i2c_ao_slave_pins>;
};
};/* end of aobus */
}; /* end of soc*/
custom_maps: custom_maps {
mapnum = <3>;
map0 = <&map_0>;
map1 = <&map_1>;
map2 = <&map_2>;
map_0: map_0{
mapname = "amlogic-remote-1";
customcode = <0xfb04>;
release_delay = <80>;
size = <44>; /*keymap size*/
keymap = <REMOTE_KEY(0x01, KEY_1)
REMOTE_KEY(0x02, KEY_2)
REMOTE_KEY(0x03, KEY_3)
REMOTE_KEY(0x04, KEY_4)
REMOTE_KEY(0x05, KEY_5)
REMOTE_KEY(0x06, KEY_6)
REMOTE_KEY(0x07, KEY_7)
REMOTE_KEY(0x08, KEY_8)
REMOTE_KEY(0x09, KEY_9)
REMOTE_KEY(0x0a, KEY_0)
REMOTE_KEY(0x1F, KEY_FN_F1)
REMOTE_KEY(0x15, KEY_MENU)
REMOTE_KEY(0x16, KEY_TAB)
REMOTE_KEY(0x0c, KEY_CHANNELUP)
REMOTE_KEY(0x0d, KEY_CHANNELDOWN)
REMOTE_KEY(0x0e, KEY_VOLUMEUP)
REMOTE_KEY(0x0f, KEY_VOLUMEDOWN)
REMOTE_KEY(0x11, KEY_HOME)
REMOTE_KEY(0x1c, KEY_RIGHT)
REMOTE_KEY(0x1b, KEY_LEFT)
REMOTE_KEY(0x19, KEY_UP)
REMOTE_KEY(0x1a, KEY_DOWN)
REMOTE_KEY(0x1d, KEY_ENTER)
REMOTE_KEY(0x17, KEY_MUTE)
REMOTE_KEY(0x49, KEY_FINANCE)
REMOTE_KEY(0x43, KEY_BACK)
REMOTE_KEY(0x12, KEY_FN_F4)
REMOTE_KEY(0x14, KEY_FN_F5)
REMOTE_KEY(0x18, KEY_FN_F6)
REMOTE_KEY(0x59, KEY_INFO)
REMOTE_KEY(0x5a, KEY_STOPCD)
REMOTE_KEY(0x10, KEY_POWER)
REMOTE_KEY(0x42, KEY_PREVIOUSSONG)
REMOTE_KEY(0x44, KEY_NEXTSONG)
REMOTE_KEY(0x1e, KEY_REWIND)
REMOTE_KEY(0x4b, KEY_FASTFORWARD)
REMOTE_KEY(0x58, KEY_PLAYPAUSE)
REMOTE_KEY(0x46, KEY_PROPS)
REMOTE_KEY(0x40, KEY_UNDO)
REMOTE_KEY(0x38, KEY_SCROLLLOCK)
REMOTE_KEY(0x57, KEY_FN)
REMOTE_KEY(0x5b, KEY_FN_ESC)
REMOTE_KEY(0x13, 195)
REMOTE_KEY(0x54, KEY_RED)
REMOTE_KEY(0x4c, KEY_GREEN)
REMOTE_KEY(0x4e, KEY_YELLOW)
REMOTE_KEY(0x55, KEY_BLUE)
REMOTE_KEY(0x53, KEY_BLUETOOTH)
REMOTE_KEY(0x52, KEY_WLAN)
REMOTE_KEY(0x39, KEY_CAMERA)
REMOTE_KEY(0x41, KEY_SOUND)
REMOTE_KEY(0x0b, KEY_QUESTION)
REMOTE_KEY(0x00, KEY_CHAT)
REMOTE_KEY(0x13, KEY_SEARCH)>;
};
map_1: map_1{
mapname = "amlogic-remote-2";
customcode = <0xfe01>;
release_delay = <80>;
size = <53>;
keymap = <REMOTE_KEY(0x01, KEY_1)
REMOTE_KEY(0x02, KEY_2)
REMOTE_KEY(0x03, KEY_3)
REMOTE_KEY(0x04, KEY_4)
REMOTE_KEY(0x05, KEY_5)
REMOTE_KEY(0x06, KEY_6)
REMOTE_KEY(0x07, KEY_7)
REMOTE_KEY(0x08, KEY_8)
REMOTE_KEY(0x09, KEY_9)
REMOTE_KEY(0x0a, KEY_0)
REMOTE_KEY(0x1F, KEY_FN_F1)
REMOTE_KEY(0x15, KEY_MENU)
REMOTE_KEY(0x16, KEY_TAB)
REMOTE_KEY(0x0c, KEY_CHANNELUP)
REMOTE_KEY(0x0d, KEY_CHANNELDOWN)
REMOTE_KEY(0x0e, KEY_VOLUMEUP)
REMOTE_KEY(0x0f, KEY_VOLUMEDOWN)
REMOTE_KEY(0x11, KEY_HOME)
REMOTE_KEY(0x1c, KEY_RIGHT)
REMOTE_KEY(0x1b, KEY_LEFT)
REMOTE_KEY(0x19, KEY_UP)
REMOTE_KEY(0x1a, KEY_DOWN)
REMOTE_KEY(0x1d, KEY_ENTER)
REMOTE_KEY(0x17, KEY_MUTE)
REMOTE_KEY(0x49, KEY_FINANCE)
REMOTE_KEY(0x43, KEY_BACK)
REMOTE_KEY(0x12, KEY_FN_F4)
REMOTE_KEY(0x14, KEY_FN_F5)
REMOTE_KEY(0x18, KEY_FN_F6)
REMOTE_KEY(0x59, KEY_INFO)
REMOTE_KEY(0x5a, KEY_STOPCD)
REMOTE_KEY(0x10, KEY_POWER)
REMOTE_KEY(0x42, KEY_PREVIOUSSONG)
REMOTE_KEY(0x44, KEY_NEXTSONG)
REMOTE_KEY(0x1e, KEY_REWIND)
REMOTE_KEY(0x4b, KEY_FASTFORWARD)
REMOTE_KEY(0x58, KEY_PLAYPAUSE)
REMOTE_KEY(0x46, KEY_PROPS)
REMOTE_KEY(0x40, KEY_UNDO)
REMOTE_KEY(0x38, KEY_SCROLLLOCK)
REMOTE_KEY(0x57, KEY_FN)
REMOTE_KEY(0x5b, KEY_FN_ESC)
REMOTE_KEY(0x54, KEY_RED)
REMOTE_KEY(0x4c, KEY_GREEN)
REMOTE_KEY(0x4e, KEY_YELLOW)
REMOTE_KEY(0x55, KEY_BLUE)
REMOTE_KEY(0x53, KEY_BLUETOOTH)
REMOTE_KEY(0x52, KEY_WLAN)
REMOTE_KEY(0x39, KEY_CAMERA)
REMOTE_KEY(0x41, KEY_SOUND)
REMOTE_KEY(0x0b, KEY_QUESTION)
REMOTE_KEY(0x00, KEY_CHAT)
REMOTE_KEY(0x13, KEY_SEARCH)>;
};
map_2: map_2{
mapname = "amlogic-remote-3";
customcode = <0xbd02>;
release_delay = <80>;
size = <17>;
keymap = <REMOTE_KEY(0xca,KEY_UP)
REMOTE_KEY(0xd2,KEY_DOWN)
REMOTE_KEY(0x99,KEY_LEFT)
REMOTE_KEY(0xc1,KEY_RIGHT)
REMOTE_KEY(0xce,KEY_RIGHTCTRL)
REMOTE_KEY(0x45,KEY_POWER)
REMOTE_KEY(0xc5,KEY_COPY)
REMOTE_KEY(0x80,KEY_MUTE)
REMOTE_KEY(0xd0,KEY_TAB)
REMOTE_KEY(0xd6,KEY_LEFTMETA)
REMOTE_KEY(0x95,KEY_HOME)
REMOTE_KEY(0xdd,KEY_PAGEUP)
REMOTE_KEY(0x8c,KEY_PAGEDOWN)
REMOTE_KEY(0x89,KEY_UNDO)
REMOTE_KEY(0x9c,KEY_PROPS)
REMOTE_KEY(0x9a,KEY_SCALE)
REMOTE_KEY(0xcd,KEY_KPCOMMA)>;
};
};
}; /* end of / */
&pinctrl_aobus {
remote_pins:remote_pin {
mux {
groups = "remote_input_ao";
function = "remote_input_ao";
};
};
pwm_ao_a_pins: pwm_ao_a {
mux {
groups = "pwm_ao_a";
function = "pwm_ao_a";
};
};
pwm_ao_a_hiz_pins: pwm_ao_a_hiz {
mux {
groups = "pwm_ao_a_hiz";
function = "pwm_ao_a";
};
};
pwm_ao_b_pins: pwm_ao_b {
mux {
groups = "pwm_ao_b";
function = "pwm_ao_b";
};
};
pwm_ao_c_pins1: pwm_ao_c_pins1 {
mux {
groups = "pwm_ao_c_4";
function = "pwm_ao_c";
};
};
pwm_ao_c_pins2: pwm_ao_c_pins2 {
mux {
groups = "pwm_ao_c_6";
function = "pwm_ao_c";
};
};
pwm_ao_c_hiz_pins1: pwm_ao_c_hiz1 {
mux {
groups = "pwm_ao_c_hiz_4";
function = "pwm_ao_c";
};
};
pwm_ao_c_hiz_pins2: pwm_ao_c_hiz2 {
mux {
groups = "pwm_ao_c_hiz_7";
function = "pwm_ao_c";
};
};
pwm_ao_d_pins1: pwm_ao_d_pins1 {
mux {
groups = "pwm_ao_d_5";
function = "pwm_ao_d";
};
};
pwm_ao_d_pins2: pwm_ao_d_pins2 {
mux {
groups = "pwm_ao_d_10";
function = "pwm_ao_d";
};
};
pwm_ao_d_pins3: pwm_ao_d_pins3 {
mux {
groups = "pwm_ao_d_e";
function = "pwm_ao_d";
};
};
pwm_a_e2: pwm_a_e2 {
mux {
groups = "pwm_a_e2";
function = "pwm_a_e2";
};
};
i2c_ao_2_pins:i2c_ao_2 {
mux {
groups = "i2c_ao_sck_2",
"i2c_ao_sda_3";
function = "i2c_ao";
};
};
i2c_ao_e_pins:i2c_ao_e {
mux {
groups = "i2c_ao_sck_e",
"i2c_ao_sda_e";
function = "i2c_ao";
};
};
i2c_ao_slave_pins:i2c_ao_slave {
mux {
groups = "i2c_ao_slave_sck",
"i2c_ao_slave_sda";
function = "i2c_ao_slave";
};
};
};
&pinctrl_periphs {
pwm_a_pins: pwm_a {
mux {
groups = "pwm_a";
function = "pwm_a";
};
};
pwm_b_pins1: pwm_b_pins1 {
mux {
groups = "pwm_b_c";
function = "pwm_b";
};
};
pwm_b_pins2: pwm_b_pins2 {
mux {
groups = "pwm_b_z";
function = "pwm_b";
};
};
pwm_c_pins1: pwm_c_pins1 {
mux {
groups = "pwm_c_dv";
function = "pwm_c";
};
};
pwm_c_pins2: pwm_c_pins2 {
mux {
groups = "pwm_c_h";
function = "pwm_c";
};
};
pwm_c_pins3: pwm_c_pins3 {
mux {
groups = "pwm_c_z";
function = "pwm_c";
};
};
pwm_d_pins1: pwm_d_pins1 {
mux {
groups = "pwm_d_dv";
function = "pwm_d";
};
};
pwm_d_pins2: pwm_d_pins2 {
mux {
groups = "pwm_d_z";
function = "pwm_d";
};
};
pwm_e_pins1: pwm_e1 {
mux {
groups = "pwm_e_dv";
function = "pwm_e";
};
};
pwm_e_pins2: pwm_e2 {
mux {
groups = "pwm_e_z";
function = "pwm_e";
};
};
pwm_f_pins1: pwm_f_pins1 {
mux {
groups = "pwm_f_dv";
function = "pwm_f";
};
};
pwm_f_pins2: pwm_f_pins2 {
mux {
groups = "pwm_f_z";
function = "pwm_f";
};
};
i2c0_c_pins:i2c0_c {
mux {
groups = "i2c0_sda_c",
"i2c0_sck_c";
function = "i2c0";
};
};
i2c0_dv_pins:i2c0_dv {
mux {
groups = "i2c0_sda_dv",
"i2c0_sck_dv";
function = "i2c0";
};
};
i2c1_z_pins:i2c1_z {
mux {
groups = "i2c1_sda_z",
"i2c1_sck_z";
function = "i2c1";
};
};
i2c1_h_pins:i2c1_h {
mux {
groups = "i2c1_sda_h",
"i2c1_sck_h";
function = "i2c1";
};
};
i2c2_h_pins:i2c2_h {
mux {
groups = "i2c2_sda_h",
"i2c2_sck_h";
function = "i2c2";
};
};
i2c2_z_pins:i2c2_z {
mux {
groups = "i2c2_sda_z",
"i2c2_sck_z";
function = "i2c2";
};
};
i2c3_h1_pins:i2c3_h1 {
mux {
groups = "i2c3_sda_h1",
"i2c3_sck_h0";
function = "i2c3";
};
};
i2c3_h20_pins:i2c3_h3 {
mux {
groups = "i2c3_sda_h20",
"i2c3_sck_h19";
function = "i2c3";
};
};
i2c3_dv_pins:i2c3_dv {
mux {
groups = "i2c3_sda_dv",
"i2c3_sck_dv";
function = "i2c3";
};
};
i2c3_c_pins:i2c3_c {
mux {
groups = "i2c3_sda_c",
"i2c3_sck_c";
function = "i2c3";
};
};
spicc0_pins_h: spicc0_pins_h {
mux {
groups = "spi0_mosi_h",
"spi0_miso_h",
"spi0_clk_h";
function = "spi0";
drive-strength = <1>;
};
};
spicc1_pins_dv: spicc1_pins_dv {
mux {
groups = "spi1_mosi_dv",
"spi1_miso_dv",
"spi1_clk_dv";
function = "spi1";
drive-strength = <1>;
};
};
};

60
arch/arm/boot/dts/amlogic/tl1_pxp.dts Normal file
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/*
* arch/arm/boot/dts/amlogic/tl1_pxp.dts
*
* Copyright (C) 2018 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
/dts-v1/;
#include "mesontl1.dtsi"
/ {
model = "Amlogic TL1 PXP";
amlogic-dt-id = "tl1_pxp";
compatible = "amlogic, tl1_pxp";
aliases {
serial0 = &uart_AO;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c_AO;
};
memory@00000000 {
device_type = "memory";
linux,usable-memory = <0x100000 0x7ff00000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* global autoconfigured region for contiguous allocations */
secmon_reserved: linux,secmon {
compatible = "shared-dma-pool";
reusable;
size = <0x400000>;
alignment = <0x400000>;
alloc-ranges = <0x05000000 0x400000>;
};
};
}; /* end of / */
&spicc0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spicc0_pins_h>;
cs-gpios = <&gpio GPIOH_20 0>;
};

269
include/dt-bindings/clock/amlogic,tl1-clkc.h Normal file
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/*
* include/dt-bindings/clock/tl1-clkc.h
*
* Copyright (C) 2018 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __DT_BINDINGS_TL1_CLKC_H
#define __DT_BINDINGS_TL1_CLKC_H
/*
* CLKID index values
*/
#define CLKID_SYS_PLL 0
#define CLKID_FIXED_PLL 1
#define CLKID_FCLK_DIV2 2
#define CLKID_FCLK_DIV3 3
#define CLKID_FCLK_DIV4 4
#define CLKID_FCLK_DIV5 5
#define CLKID_FCLK_DIV7 6
#define CLKID_FCLK_DIV2P5 7
#define CLKID_GP0_PLL 8
#define CLKID_GP1_PLL 9
#define CLKID_HIFI_PLL 10
#define CLKID_MPEG_SEL 11
#define CLKID_MPEG_DIV 12
#define CLKID_CLK81 13
#define CLKID_MPLL0 14
#define CLKID_MPLL1 15
#define CLKID_MPLL2 16
#define CLKID_MPLL3 17
#define CLKID_CPU_FCLK_P00 18
#define CLKID_CPU_FCLK_P01 19
#define CLKID_CPU_FCLK_P0 20
#define CLKID_CPU_FCLK_P10 21
#define CLKID_CPU_FCLK_P11 22
#define CLKID_CPU_FCLK_P1 23
#define CLKID_CPU_FCLK_P 24
#define CLKID_CPU_CLK 25
/*#define CLKID_ADC_PLL 24*/
/*HHI_GCLK_MPEG0: 0x50*/
#define GATE_BASE0 (26)
#define CLKID_DDR (GATE_BASE0 + 0)
#define CLKID_DOS (GATE_BASE0 + 1)
#define CLKID_ETH_PHY (GATE_BASE0 + 2)
#define CLKID_ISA (GATE_BASE0 + 3)
#define CLKID_PL310 (GATE_BASE0 + 4)
#define CLKID_PERIPHS (GATE_BASE0 + 5)
#define CLKID_SPICC0 (GATE_BASE0 + 6)
#define CLKID_I2C (GATE_BASE0 + 7)
#define CLKID_SANA (GATE_BASE0 + 8)
#define CLKID_SMART_CARD (GATE_BASE0 + 9)
#define CLKID_UART0 (GATE_BASE0 + 10)
#define CLKID_SPICC1 (GATE_BASE0 + 11)
#define CLKID_STREAM (GATE_BASE0 + 12)
#define CLKID_ASYNC_FIFO (GATE_BASE0 + 13)
#define CLKID_TVFE (GATE_BASE0 + 14)
#define CLKID_HIU_REG (GATE_BASE0 + 15)
#define CLKID_HDMIRX_PCLK (GATE_BASE0 + 16)
#define CLKID_ATV_DEMOD (GATE_BASE0 + 17)
#define CLKID_ASSIST_MISC (GATE_BASE0 + 18)
#define CLKID_SD_EMMC_B (GATE_BASE0 + 19)
#define CLKID_SD_EMMC_C (GATE_BASE0 + 20)
#define CLKID_ADEC (GATE_BASE0 + 21)
#define CLKID_ACODEC (GATE_BASE0 + 22)
#define CLKID_TCON (GATE_BASE0 + 23)
#define CLKID_SPI (GATE_BASE0 + 24)
#define CLKID_DSP (GATE_BASE0 + 25)
/*HHI_GCLK_MPEG1: 0x51*/
#define GATE_BASE1 (GATE_BASE0 + 26)
#define CLKID_AUDIO (GATE_BASE1 + 0)
#define CLKID_ETH_CORE (GATE_BASE1 + 1)
#define CLKID_DEMUX (GATE_BASE1 + 2)
#define CLKID_AIFIFO (GATE_BASE1 + 3)
#define CLKID_ADC (GATE_BASE1 + 4)
#define CLKID_UART1 (GATE_BASE1 + 5)
#define CLKID_G2D (GATE_BASE1 + 6)
#define CLKID_RESET (GATE_BASE1 + 7)
#define CLKID_U_PARSER (GATE_BASE1 + 8)
#define CLKID_USB_GENERAL (GATE_BASE1 + 9)
#define CLKID_AHB_ARB0 (GATE_BASE1 + 10)
/*HHI_GCLK_MPEG2: 0x52*/
#define GATE_BASE2 (GATE_BASE1 + 11)
#define CLKID_AHB_DATA_BUS (GATE_BASE2 + 0)
#define CLKID_AHB_CTRL_BUS (GATE_BASE2 + 1)
#define CLKID_BT656 (GATE_BASE2 + 2)
#define CLKID_USB1_TO_DDR (GATE_BASE2 + 3)
#define CLKID_MMC_PCLK (GATE_BASE2 + 4)
#define CLKID_HDCP22_PCLK (GATE_BASE0 + 5)
#define CLKID_UART2 (GATE_BASE2 + 6)
#define CLKID_TS (GATE_BASE2 + 7)
#define CLKID_VPU_INTR (GATE_BASE2 + 8)
#define CLKID_DEMOD_COMB (GATE_BASE2 + 9)
#define CLKID_GIC (GATE_BASE2 + 10)
/*HHI_GCLK_OTHER: 0x55*/
#define GATE_OTHER (GATE_BASE2 + 11)
#define CLKID_VCLK2_VENCI0 (GATE_OTHER + 0)
#define CLKID_VCLK2_VENCI1 (GATE_OTHER + 1)
#define CLKID_VCLK2_VENCP0 (GATE_OTHER + 2)
#define CLKID_VCLK2_VENCP1 (GATE_OTHER + 3)
#define CLKID_VCLK2_VENCT0 (GATE_OTHER + 4)
#define CLKID_VCLK2_VENCT1 (GATE_OTHER + 5)
#define CLKID_VCLK2_OTHER (GATE_OTHER + 6)
#define CLKID_VCLK2_ENCI (GATE_OTHER + 7)
#define CLKID_VCLK2_ENCP (GATE_OTHER + 8)
#define CLKID_DAC_CLK (GATE_OTHER + 9)
#define CLKID_ENC480P (GATE_OTHER + 10)
#define CLKID_RNG1 (GATE_OTHER + 11)
#define CLKID_VCLK2_ENCT (GATE_OTHER + 12)
#define CLKID_VCLK2_ENCL (GATE_OTHER + 13)
#define CLKID_VCLK2_VENCLMMC (GATE_OTHER + 14)
#define CLKID_VCLK2_VENCL (GATE_OTHER + 15)
#define CLKID_VCLK2_OTHER1 (GATE_OTHER + 16)
/*HHI_GCLK_OTHER: 0x55*/
#define GATE_AO_BASE (GATE_OTHER + 17)
#define CLKID_DMA (GATE_AO_BASE + 0)
#define CLKID_EFUSE (GATE_AO_BASE + 1)
#define CLKID_ROM_BOOT (GATE_AO_BASE + 2)
#define CLKID_RESET_SEC (GATE_AO_BASE + 3)
#define CLKID_SEC_AHB_APB3 (GATE_AO_BASE + 4)
#define CLOCK_GATE (GATE_AO_BASE + 5)
#define CLKID_SD_EMMC_B_P0_MUX (CLOCK_GATE + 0)
#define CLKID_SD_EMMC_B_P0_DIV (CLOCK_GATE + 1)
#define CLKID_SD_EMMC_B_P0_GATE (CLOCK_GATE + 2)
#define CLKID_SD_EMMC_B_P0_COMP (CLOCK_GATE + 3)
#define CLKID_SD_EMMC_C_P0_MUX (CLOCK_GATE + 4)
#define CLKID_SD_EMMC_C_P0_DIV (CLOCK_GATE + 5)
#define CLKID_SD_EMMC_C_P0_GATE (CLOCK_GATE + 6)
#define CLKID_SD_EMMC_C_P0_COMP (CLOCK_GATE + 7)
#define CLKID_SD_EMMC_B_MUX (CLOCK_GATE + 8)
#define CLKID_SD_EMMC_B_DIV (CLOCK_GATE + 9)
#define CLKID_SD_EMMC_B_GATE (CLOCK_GATE + 10)
#define CLKID_SD_EMMC_B_COMP (CLOCK_GATE + 11)
#define CLKID_SD_EMMC_C_MUX (CLOCK_GATE + 12)
#define CLKID_SD_EMMC_C_DIV (CLOCK_GATE + 13)
#define CLKID_SD_EMMC_C_GATE (CLOCK_GATE + 14)
#define CLKID_SD_EMMC_C_COMP (CLOCK_GATE + 15)
#define CLKID_MEDIA_BASE (CLOCK_GATE + 16)
#define CLKID_VPU_P0_MUX (CLKID_MEDIA_BASE + 0)
#define CLKID_VPU_P0_DIV (CLKID_MEDIA_BASE + 1)
#define CLKID_VPU_P0_GATE (CLKID_MEDIA_BASE + 2)
#define CLKID_VPU_P0_COMP (CLKID_MEDIA_BASE + 3)
#define CLKID_VPU_P1_MUX (CLKID_MEDIA_BASE + 4)
#define CLKID_VPU_P1_DIV (CLKID_MEDIA_BASE + 5)
#define CLKID_VPU_P1_GATE (CLKID_MEDIA_BASE + 6)
#define CLKID_VPU_P1_COMP (CLKID_MEDIA_BASE + 7)
#define CLKID_VPU_MUX (CLKID_MEDIA_BASE + 8)
#define CLKID_VAPB_P0_MUX (CLKID_MEDIA_BASE + 9)
#define CLKID_VAPB_P0_DIV (CLKID_MEDIA_BASE + 10)
#define CLKID_VAPB_P0_GATE (CLKID_MEDIA_BASE + 11)
#define CLKID_VAPB_P0_COMP (CLKID_MEDIA_BASE + 12)
#define CLKID_VAPB_P1_MUX (CLKID_MEDIA_BASE + 13)
#define CLKID_VAPB_P1_DIV (CLKID_MEDIA_BASE + 14)
#define CLKID_VAPB_P1_GATE (CLKID_MEDIA_BASE + 15)
#define CLKID_VAPB_P1_COMP (CLKID_MEDIA_BASE + 16)
#define CLKID_VAPB_MUX (CLKID_MEDIA_BASE + 17)
#define CLKID_GE2D_GATE (CLKID_MEDIA_BASE + 18)
#define CLKID_VDIN_MEAS_MUX (CLKID_MEDIA_BASE + 19)
#define CLKID_VDIN_MEAS_DIV (CLKID_MEDIA_BASE + 20)
#define CLKID_VDIN_MEAS_GATE (CLKID_MEDIA_BASE + 21)
#define CLKID_VDIN_MEAS_COMP (CLKID_MEDIA_BASE + 22)
#define CLKID_VPU_CLKB_TMP_MUX (CLKID_MEDIA_BASE + 23)
#define CLKID_VPU_CLKB_TMP_DIV (CLKID_MEDIA_BASE + 24)
#define CLKID_VPU_CLKB_TMP_GATE (CLKID_MEDIA_BASE + 25)
#define CLKID_VPU_CLKB_DIV (CLKID_MEDIA_BASE + 26)
#define CLKID_VPU_CLKB_GATE (CLKID_MEDIA_BASE + 27)
#define CLKID_VPU_CLKB_TMP_COMP (CLKID_MEDIA_BASE + 28)
#define CLKID_VPU_CLKB_COMP (CLKID_MEDIA_BASE + 29)
#define CLKID_VID_LOCK_COMP (CLKID_MEDIA_BASE + 30)
#define CLKID_BT656_CLK0_COMP (CLKID_MEDIA_BASE + 31)
#define CLKID_TCON_PLL_COMP (CLKID_MEDIA_BASE + 32)
#define CLKID_DEMOD_COMP (CLKID_MEDIA_BASE + 33)
#define CLKID_ADC_EXTCLK_COMP (CLKID_MEDIA_BASE + 34)
#define CLKID_VPU_CLKC_P0_COMP (CLKID_MEDIA_BASE + 35)
#define CLKID_VPU_CLKC_P1_COMP (CLKID_MEDIA_BASE + 36)
#define CLKID_VPU_CLKC_MUX (CLKID_MEDIA_BASE + 37)
#define CLKID_HDMIRX_BASE (CLKID_MEDIA_BASE + 38)
#define CLKID_HDMIRX_CFG_COMP (CLKID_HDMIRX_BASE + 0)
#define CLKID_HDMIRX_MODET_COMP (CLKID_HDMIRX_BASE + 1)
#define CLKID_HDMIRX_AUDMEAS_COMP (CLKID_HDMIRX_BASE + 2)
#define CLKID_HDMIRX_ACR_COMP (CLKID_HDMIRX_BASE + 3)
#define CLKID_HDCP22_SKP_COMP (CLKID_HDMIRX_BASE + 4)
#define CLKID_HDCP22_ESM_COMP (CLKID_HDMIRX_BASE + 5)
#define CLKID_VHDEC_BASE (CLKID_HDMIRX_BASE + 6)
#define CLKID_VDEC_P0_MUX (CLKID_VHDEC_BASE + 0)
#define CLKID_VDEC_P0_DIV (CLKID_VHDEC_BASE + 1)
#define CLKID_VDEC_P0_GATE (CLKID_VHDEC_BASE + 2)
#define CLKID_VDEC_P0_COMP (CLKID_VHDEC_BASE + 3)
#define CLKID_VDEC_P1_MUX (CLKID_VHDEC_BASE + 4)
#define CLKID_VDEC_P1_DIV (CLKID_VHDEC_BASE + 5)
#define CLKID_VDEC_P1_GATE (CLKID_VHDEC_BASE + 6)
#define CLKID_VDEC_P1_COMP (CLKID_VHDEC_BASE + 7)
#define CLKID_HCODEC_P0_MUX (CLKID_VHDEC_BASE + 8)
#define CLKID_HCODEC_P0_DIV (CLKID_VHDEC_BASE + 9)
#define CLKID_HCODEC_P0_GATE (CLKID_VHDEC_BASE + 10)
#define CLKID_HCODEC_P0_COMP (CLKID_VHDEC_BASE + 11)
#define CLKID_HCODEC_P1_MUX (CLKID_VHDEC_BASE + 12)
#define CLKID_HCODEC_P1_DIV (CLKID_VHDEC_BASE + 13)
#define CLKID_HCODEC_P1_GATE (CLKID_VHDEC_BASE + 14)
#define CLKID_HCODEC_P1_COMP (CLKID_VHDEC_BASE + 15)
#define CLKID_HEVC_P0_MUX (CLKID_VHDEC_BASE + 16)
#define CLKID_HEVC_P0_DIV (CLKID_VHDEC_BASE + 17)
#define CLKID_HEVC_P0_GATE (CLKID_VHDEC_BASE + 18)
#define CLKID_HEVC_P0_COMP (CLKID_VHDEC_BASE + 19)
#define CLKID_HEVC_P1_MUX (CLKID_VHDEC_BASE + 20)
#define CLKID_HEVC_P1_DIV (CLKID_VHDEC_BASE + 21)
#define CLKID_HEVC_P1_GATE (CLKID_VHDEC_BASE + 22)
#define CLKID_HEVC_P1_COMP (CLKID_VHDEC_BASE + 23)
#define CLKID_VDEC_MUX (CLKID_VHDEC_BASE + 24)
#define CLKID_HCODEC_MUX (CLKID_VHDEC_BASE + 25)
#define CLKID_HEVC_MUX (CLKID_VHDEC_BASE + 26)
#define CLKID_HEVCF_P0_COMP (CLKID_VHDEC_BASE + 27)
#define CLKID_HEVCF_P1_COMP (CLKID_VHDEC_BASE + 28)
#define CLKID_HEVCF_MUX (CLKID_VHDEC_BASE + 29)
#define CLKID_MISC_BASE (CLKID_VHDEC_BASE + 30)
#define CLKID_TS_CLK_COMP (CLKID_MISC_BASE + 0)
#define CLKID_SPICC0_COMP (CLKID_MISC_BASE + 1)
#define CLKID_SPICC1_COMP (CLKID_MISC_BASE + 2)
#define CLKID_GPU_BASE (CLKID_MISC_BASE + 3)
#define CLKID_GPU_P0_COMP (CLKID_GPU_BASE + 0)
#define CLKID_GPU_P1_COMP (CLKID_GPU_BASE + 1)
#define CLKID_GPU_MUX (CLKID_GPU_BASE + 2)
#define CLKID_AO_BASE (CLKID_GPU_BASE + 3)
#define CLKID_AO_CLK81 (CLKID_AO_BASE + 0)
#define CLKID_SARADC_MUX (CLKID_AO_BASE + 1)
#define CLKID_SARADC_DIV (CLKID_AO_BASE + 2)
#define CLKID_SARADC_GATE (CLKID_AO_BASE + 3)
#define CLKID_AO_AHB_BUS (CLKID_AO_BASE + 4)
#define CLKID_AO_IR (CLKID_AO_BASE + 5)
#define CLKID_AO_I2C_MASTER (CLKID_AO_BASE + 6)
#define CLKID_AO_I2C_SLAVE (CLKID_AO_BASE + 7)
#define CLKID_AO_UART1 (CLKID_AO_BASE + 8)
#define CLKID_AO_PROD_I2C (CLKID_AO_BASE + 9)
#define CLKID_AO_UART2 (CLKID_AO_BASE + 10)
#define CLKID_AO_IR_BLASTER (CLKID_AO_BASE + 11)
#define CLKID_AO_SAR_ADC (CLKID_AO_BASE + 12)
#define NR_CLKS (CLKID_AO_BASE + 13)
#endif /* __DT_BINDINGS_TL1_CLKC_H */

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include/dt-bindings/gpio/meson-tl1-gpio.h Normal file
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/*
* include/dt-bindings/gpio/meson-tl1-gpio.h
*
* Copyright (C) 2018 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __DT_BINDINGS_MESON_TL1_GPIO_H
#define __DT_BINDINGS_MESON_TL1_GPIO_H
/*
* NOTICE: The gpio number sequence according to the gpio interrupts.
*/
/* AO Bank */
#define GPIOAO_0 0
#define GPIOAO_1 1
#define GPIOAO_2 2
#define GPIOAO_3 3
#define GPIOAO_4 4
#define GPIOAO_5 5
#define GPIOAO_6 6
#define GPIOAO_7 7
#define GPIOAO_8 8
#define GPIOAO_9 9
#define GPIOAO_10 10
#define GPIOAO_11 11
#define GPIOE_0 12
#define GPIOE_1 13
#define GPIOE_2 14
#define GPIO_TEST_N 15
/* EE Bank */
#define GPIOZ_0 0
#define GPIOZ_1 1
#define GPIOZ_2 2
#define GPIOZ_3 3
#define GPIOZ_4 4
#define GPIOZ_5 5
#define GPIOZ_6 6
#define GPIOZ_7 7
#define GPIOZ_8 8
#define GPIOZ_9 9
#define GPIOZ_10 10
#define GPIOH_0 11
#define GPIOH_1 12
#define GPIOH_2 13
#define GPIOH_3 14
#define GPIOH_4 15
#define GPIOH_5 16
#define GPIOH_6 17
#define GPIOH_7 18
#define GPIOH_8 19
#define GPIOH_9 20
#define GPIOH_10 21
#define GPIOH_11 22
#define GPIOH_12 23
#define GPIOH_13 24
#define GPIOH_14 25
#define GPIOH_15 26
#define GPIOH_16 27
#define GPIOH_17 28
#define GPIOH_18 29
#define GPIOH_19 30
#define GPIOH_20 31
#define GPIOH_21 32
#define GPIOH_22 33
#define BOOT_0 34
#define BOOT_1 35
#define BOOT_2 36
#define BOOT_3 37
#define BOOT_4 38
#define BOOT_5 39
#define BOOT_6 40
#define BOOT_7 41
#define BOOT_8 42
#define BOOT_9 43
#define BOOT_10 44
#define BOOT_11 45
#define BOOT_12 46
#define BOOT_13 47
#define GPIOC_0 48
#define GPIOC_1 49
#define GPIOC_2 50
#define GPIOC_3 51
#define GPIOC_4 52
#define GPIOC_5 53
#define GPIOC_6 54
#define GPIOC_7 55
#define GPIOC_8 56
#define GPIOC_9 57
#define GPIOC_10 58
#define GPIOC_11 59
#define GPIOC_12 60
#define GPIOC_13 61
#define GPIOC_14 62
#define GPIOW_0 63
#define GPIOW_1 64
#define GPIOW_2 65
#define GPIOW_3 66
#define GPIOW_4 67
#define GPIOW_5 68
#define GPIOW_6 69
#define GPIOW_7 70
#define GPIOW_8 71
#define GPIOW_9 72
#define GPIOW_10 73
#define GPIOW_11 74
#define GPIODV_0 75
#define GPIODV_1 76
#define GPIODV_2 77
#define GPIODV_3 78
#define GPIODV_4 79
#define GPIODV_5 80
#define GPIODV_6 81
#define GPIODV_7 82
#define GPIODV_8 83
#define GPIODV_9 84
#define GPIODV_10 85
#define GPIODV_11 86
#endif