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Support the Rk312X Codec & SPDIF
This commit is contained in:
Sun Mingjun
@@ -34,3 +34,100 @@ rockchip-audio {
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};
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};
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};
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- compatible : "audio-rk312x"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- clocks: must include clock specifiers corresponding to entries in the
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clock-names property.
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- clocks-names: list of clock names sorted in the same order as the clocks
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property. Must contain "rockchip-i2s" and "rk3036-codec".
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- interrupts: interrupt number to the cpu.
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- dmas: list of DMA controller phandle and DMA request line ordered pairs.
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- dma-names: identifier string for each DMA request line in the dmas property.
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These strings correspond 1:1 with the ordered pairs in dmas.
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- pinctrl-names: must contain a "default" entry.
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- pinctrl-0: pin control group to be used for this controller.
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- pinctrl-1: pin control group to be used for gpio.
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Example:
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rockchip-audio {
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compatible = "audio-rk312x";
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dais {
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dai0 {
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audio-codec = <&codec>;
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i2s-controller = <&i2s1>;
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format = "i2s";
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//continuous-clock;
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//bitclock-inversion;
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//frame-inversion;
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//bitclock-master;
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//frame-master;
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};
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};
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};
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- compatible : "rk312x-spdif"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- clocks: must include clock specifiers corresponding to entries in the
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clock-names property.
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- clocks-names: list of clock names sorted in the same order as the clocks
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property. Must contain "rockchip-i2s" and "rk3036-codec".
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- interrupts: interrupt number to the cpu.
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- dmas: list of DMA controller phandle and DMA request line ordered pairs.
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- dma-names: identifier string for each DMA request line in the dmas property.
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These strings correspond 1:1 with the ordered pairs in dmas.
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- pinctrl-names: must contain a "default" entry.
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- pinctrl-0: pin control group to be used for this controller.
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- pinctrl-1: pin control group to be used for gpio.
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Example:
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spdif: spdif@10204000 {
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compatible = "rk312x-spdif";
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reg = <0x10204000 0x1000>;
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clocks = <&clk_spdif>, <&clk_gates10 9>;
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clock-names = "spdif_8ch_mclk", "spdif_hclk";
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&pdma 13>;
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//#dma-cells = <1>;
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dma-names = "tx";
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pinctrl-names = "default";
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pinctrl-0 = <&spdif_tx>;
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};
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- compatible : "rk312x-codec"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- clocks: must include clock specifiers corresponding to entries in the
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clock-names property.
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- clocks-names: list of clock names sorted in the same order as the clocks
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property. Must contain "rockchip-i2s" and "rk3036-codec".
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- interrupts: interrupt number to the cpu.
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- dmas: list of DMA controller phandle and DMA request line ordered pairs.
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- dma-names: identifier string for each DMA request line in the dmas property.
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These strings correspond 1:1 with the ordered pairs in dmas.
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- pinctrl-names: must contain a "default" entry.
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- pinctrl-0: pin control group to be used for this controller.
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- pinctrl-1: pin control group to be used for gpio.
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Example:
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codec: codec@20030000 {
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compatible = "rk312x-codec";
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reg = <0x20030000 0x1000>;
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spk_ctl_io = <&gpio1 GPIO_A3 0>;
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//pinctrl-names = "default";
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//pinctrl-0 = <&i2s_gpio>;
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boot_depop = <1>;
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pa_enable_time = <1000>;
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clocks = <&clk_gates5 14>;
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clock-names = "g_pclk_acodec";
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};
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@@ -438,18 +438,31 @@
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dma-names = "tx", "rx";
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};
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codec: codec@20030000 {
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compatible = "rk312x-codec";
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reg = <0x20030000 0x1000>;
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spk_ctl_io = <&gpio1 GPIO_A3 0>;
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//pinctrl-names = "default";
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//pinctrl-0 = <&i2s_gpio>;
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boot_depop = <1>;
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pa_enable_time = <1000>;
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clocks = <&clk_gates5 14>;
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clock-names = "g_pclk_acodec";
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};
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spdif: spdif@10204000 {
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compatible = "rockchip-spdif";
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compatible = "rk312x-spdif";
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reg = <0x10204000 0x1000>;
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clocks = <&clk_spdif>, <&clk_gates10 8>;
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clock-names = "spdif_8ch_mclk", "spdif_hclk";
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clocks = <&clk_spdif>, <&clk_gates10 9>;
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clock-names = "spdif_mclk", "spdif_hclk";
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&pdma 13>;
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//#dma-cells = <1>;
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dma-names = "tx";
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//pinctrl-names = "default";
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//pinctrl-0 = <&spdif_tx>;
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};
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pinctrl-names = "default";
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pinctrl-0 = <&spdif_tx>;
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};
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dsihost0: mipi@10110000{
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compatible = "rockchip,rk32-dsi";
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@@ -843,4 +856,44 @@
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clock-names = "pd_cif0", "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
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status = "okay";
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};
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codec_hdmi_spdif: codec-hdmi-spdif {
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compatible = "hdmi-spdif";
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};
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rockchip-hdmi-spdif {
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compatible = "rockchip-hdmi-spdif";
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dais {
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dai0 {
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audio-codec = <&codec_hdmi_spdif>;
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i2s-controller = <&spdif>;
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};
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};
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};
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rockchip-audio {
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compatible = "audio-rk312x";
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dais {
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dai0 {
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audio-codec = <&codec>;
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i2s-controller = <&i2s1>;
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format = "i2s";
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//continuous-clock;
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//bitclock-inversion;
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//frame-inversion;
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//bitclock-master;
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//frame-master;
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};
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dai1 {
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audio-codec = <&codec>;
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i2s-controller = <&i2s1>;
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format = "i2s";
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//continuous-clock;
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//bitclock-inversion;
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//frame-inversion;
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//bitclock-master;
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//frame-master;
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};
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};
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};
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};
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@@ -317,6 +317,9 @@ config SND_SOC_PCM3008
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config SND_SOC_RK3036
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tristate
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config SND_SOC_RK312X
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tristate
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#Freescale sgtl5000 codec
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config SND_SOC_SGTL5000
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tristate
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@@ -136,6 +136,7 @@ snd-soc-rt3261-objs := rt3261-dsp.o
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snd-soc-cs42l52-objs := cs42l52.o
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snd-soc-rk1000-objs := rk1000_codec.o
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snd-soc-rk3036-objs := rk3036_codec.o
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snd-soc-rk312x-objs := rk312x_codec.o
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snd-soc-rk610-objs := rk610_codec.o
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snd-soc-rk616-objs := rk616_codec.o
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snd-soc-rk2928-objs := rk2928_codec.o
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@@ -284,6 +285,7 @@ obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o
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obj-$(CONFIG_SND_SOC_CS42L52) += snd-soc-cs42l52.o
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obj-$(CONFIG_SND_SOC_RK1000) += snd-soc-rk1000.o
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obj-$(CONFIG_SND_SOC_RK3036) += snd-soc-rk3036.o
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obj-$(CONFIG_SND_SOC_RK312X) += snd-soc-rk312x.o
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obj-$(CONFIG_SND_SOC_RK610) += snd-soc-rk610.o
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obj-$(CONFIG_SND_SOC_RK616) += snd-soc-rk616.o
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obj-$(CONFIG_SND_SOC_RK2928) += snd-soc-rk2928.o
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2360
sound/soc/codecs/rk312x_codec.c
Executable file
2360
sound/soc/codecs/rk312x_codec.c
Executable file
File diff suppressed because it is too large
Load Diff
564
sound/soc/codecs/rk312x_codec.h
Executable file
564
sound/soc/codecs/rk312x_codec.h
Executable file
@@ -0,0 +1,564 @@
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/*
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* rk3036.h -- RK312x CODEC ALSA SoC audio driver
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*
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* Copyright 2013 Rockship
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* Author: chenjq <chenjq@rock-chips.com>
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*
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*/
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#ifndef __RK312x_CODEC_H__
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#define __RK312x_CODEC_H__
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/* codec register */
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#define RK312x_CODEC_BASE (0x0)
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#define RK312x_RESET (RK312x_CODEC_BASE + 0x00)
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#define RK312x_ADC_INT_CTL1 (RK312x_CODEC_BASE + 0x08)
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#define RK312x_ADC_INT_CTL2 (RK312x_CODEC_BASE + 0x0c)
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#define RK312x_DAC_INT_CTL1 (RK312x_CODEC_BASE + 0x10)
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#define RK312x_DAC_INT_CTL2 (RK312x_CODEC_BASE + 0x14)
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#define RK312x_DAC_INT_CTL3 (RK312x_CODEC_BASE + 0x18)
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#define RK312x_ADC_MIC_CTL (RK312x_CODEC_BASE + 0x88)
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#define RK312x_BST_CTL (RK312x_CODEC_BASE + 0x8c)
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#define RK312x_ALC_MUNIN_CTL (RK312x_CODEC_BASE + 0x90)
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#define RK312x_BSTL_ALCL_CTL (RK312x_CODEC_BASE + 0x94)
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#define RK312x_ALCR_GAIN_CTL (RK312x_CODEC_BASE + 0x98)
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#define RK312x_ADC_ENABLE (RK312x_CODEC_BASE + 0x9c)
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#define RK312x_DAC_CTL (RK312x_CODEC_BASE + 0xa0)
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#define RK312x_DAC_ENABLE (RK312x_CODEC_BASE + 0xa4)
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#define RK312x_HPMIX_CTL (RK312x_CODEC_BASE + 0xa8)
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#define RK312x_HPMIX_S_SELECT (RK312x_CODEC_BASE + 0xac)
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#define RK312x_HPOUT_CTL (RK312x_CODEC_BASE + 0xB0)
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#define RK312x_HPOUTL_GAIN (RK312x_CODEC_BASE + 0xB4)
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#define RK312x_HPOUTR_GAIN (RK312x_CODEC_BASE + 0xB8)
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#define RK312x_SELECT_CURRENT (RK312x_CODEC_BASE + 0xBC)
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#define RK312x_PGAL_AGC_CTL1 (RK312x_CODEC_BASE + 0x100)
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#define RK312x_PGAL_AGC_CTL2 (RK312x_CODEC_BASE + 0x104)
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#define RK312x_PGAL_AGC_CTL3 (RK312x_CODEC_BASE + 0x108)
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#define RK312x_PGAL_AGC_CTL4 (RK312x_CODEC_BASE + 0x10c)
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#define RK312x_PGAL_ASR_CTL (RK312x_CODEC_BASE + 0x110)
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#define RK312x_PGAL_AGC_MAX_H (RK312x_CODEC_BASE + 0x114)
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#define RK312x_PGAL_AGC_MAX_L (RK312x_CODEC_BASE + 0x118)
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#define RK312x_PGAL_AGC_MIN_H (RK312x_CODEC_BASE + 0x11c)
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#define RK312x_PGAL_AGC_MIN_L (RK312x_CODEC_BASE + 0x120)
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#define RK312x_PGAL_AGC_CTL5 (RK312x_CODEC_BASE + 0x124)
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#define RK312x_PGAR_AGC_CTL1 (RK312x_CODEC_BASE + 0x140)
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#define RK312x_PGAR_AGC_CTL2 (RK312x_CODEC_BASE + 0x144)
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#define RK312x_PGAR_AGC_CTL3 (RK312x_CODEC_BASE + 0x148)
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#define RK312x_PGAR_AGC_CTL4 (RK312x_CODEC_BASE + 0x14c)
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#define RK312x_PGAR_ASR_CTL (RK312x_CODEC_BASE + 0x150)
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#define RK312x_PGAR_AGC_MAX_H (RK312x_CODEC_BASE + 0x154)
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#define RK312x_PGAR_AGC_MAX_L (RK312x_CODEC_BASE + 0x158)
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#define RK312x_PGAR_AGC_MIN_H (RK312x_CODEC_BASE + 0x15c)
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#define RK312x_PGAR_AGC_MIN_L (RK312x_CODEC_BASE + 0x160)
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#define RK312x_PGAR_AGC_CTL5 (RK312x_CODEC_BASE + 0x164)
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/* ADC Interface Control 1 (0x08) */
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#define RK312x_ALRCK_POL_MASK (0x1 << 7)
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#define RK312x_ALRCK_POL_SFT 7
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#define RK312x_ALRCK_POL_EN (0x1 << 7)
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#define RK312x_ALRCK_POL_DIS (0x0 << 7)
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#define RK312x_ADC_VWL_MASK (0x3 << 5)
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#define RK312x_ADC_VWL_SFT 5
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#define RK312x_ADC_VWL_32 (0x3 << 5)
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#define RK312x_ADC_VWL_24 (0x2 << 5)
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#define RK312x_ADC_VWL_20 (0x1 << 5)
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#define RK312x_ADC_VWL_16 (0x0 << 5)
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#define RK312x_ADC_DF_MASK (0x3 << 3)
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#define RK312x_ADC_DF_SFT 3
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#define RK312x_ADC_DF_PCM (0x3 << 3)
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#define RK312x_ADC_DF_I2S (0x2 << 3)
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#define RK312x_ADC_DF_LJ (0x1 << 3)
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#define RK312x_ADC_DF_RJ (0x0 << 3)
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#define RK312x_ADC_SWAP_MASK (0x1 << 1)
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#define RK312x_ADC_SWAP_SFT 1
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#define RK312x_ADC_SWAP_EN (0x1 << 1)
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#define RK312x_ADC_SWAP_DIS (0x0 << 1)
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#define RK312x_ADC_TYPE_MASK 0x1
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#define RK312x_ADC_TYPE_SFT 0
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#define RK312x_ADC_TYPE_MONO 0x1
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#define RK312x_ADC_TYPE_STEREO 0x0
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/* ADC Interface Control 2 (0x0c) */
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#define RK312x_I2S_MODE_MASK (0x1 << 4)
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#define RK312x_I2S_MODE_SFT (4)
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#define RK312x_I2S_MODE_MST (0x1 << 4)
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#define RK312x_I2S_MODE_SLV (0x0 << 4)
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#define RK312x_ADC_WL_MASK (0x3 << 2)
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#define RK312x_ADC_WL_SFT (2)
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#define RK312x_ADC_WL_32 (0x3 << 2)
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#define RK312x_ADC_WL_24 (0x2 << 2)
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#define RK312x_ADC_WL_20 (0x1 << 2)
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#define RK312x_ADC_WL_16 (0x0 << 2)
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#define RK312x_ADC_RST_MASK (0x1 << 1)
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#define RK312x_ADC_RST_SFT (1)
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#define RK312x_ADC_RST_DIS (0x1 << 1)
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#define RK312x_ADC_RST_EN (0x0 << 1)
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#define RK312x_ABCLK_POL_MASK 0x1
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#define RK312x_ABCLK_POL_SFT 0
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#define RK312x_ABCLK_POL_EN 0x1
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#define RK312x_ABCLK_POL_DIS 0x0
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/* DAC Interface Control 1 (0x10) */
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#define RK312x_DLRCK_POL_MASK (0x1 << 7)
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#define RK312x_DLRCK_POL_SFT 7
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#define RK312x_DLRCK_POL_EN (0x1 << 7)
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#define RK312x_DLRCK_POL_DIS (0x0 << 7)
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#define RK312x_DAC_VWL_MASK (0x3 << 5)
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#define RK312x_DAC_VWL_SFT 5
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#define RK312x_DAC_VWL_32 (0x3 << 5)
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#define RK312x_DAC_VWL_24 (0x2 << 5)
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#define RK312x_DAC_VWL_20 (0x1 << 5)
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#define RK312x_DAC_VWL_16 (0x0 << 5)
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#define RK312x_DAC_DF_MASK (0x3 << 3)
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#define RK312x_DAC_DF_SFT 3
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#define RK312x_DAC_DF_PCM (0x3 << 3)
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#define RK312x_DAC_DF_I2S (0x2 << 3)
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#define RK312x_DAC_DF_LJ (0x1 << 3)
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#define RK312x_DAC_DF_RJ (0x0 << 3)
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#define RK312x_DAC_SWAP_MASK (0x1 << 2)
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#define RK312x_DAC_SWAP_SFT 2
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#define RK312x_DAC_SWAP_EN (0x1 << 2)
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#define RK312x_DAC_SWAP_DIS (0x0 << 2)
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/* DAC Interface Control 2 (0x14) */
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#define RK312x_DAC_WL_MASK (0x3 << 2)
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#define RK312x_DAC_WL_SFT 2
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#define RK312x_DAC_WL_32 (0x3 << 2)
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#define RK312x_DAC_WL_24 (0x2 << 2)
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#define RK312x_DAC_WL_20 (0x1 << 2)
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#define RK312x_DAC_WL_16 (0x0 << 2)
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#define RK312x_DAC_RST_MASK (0x1 << 1)
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#define RK312x_DAC_RST_SFT 1
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#define RK312x_DAC_RST_DIS (0x1 << 1)
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#define RK312x_DAC_RST_EN (0x0 << 1)
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#define RK312x_DBCLK_POL_MASK 0x1
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||||
#define RK312x_DBCLK_POL_SFT 0
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#define RK312x_DBCLK_POL_EN 0x1
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||||
#define RK312x_DBCLK_POL_DIS 0x0
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||||
/* ADC & MICBIAS (0x88) */
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#define RK312x_ADC_CURRENT_ENABLE (0x1 << 7)
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#define RK312x_ADC_CURRENT_DISABLE (0x0 << 7)
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||||
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#define RK312x_MICBIAS_VOL_ENABLE (6)
|
||||
|
||||
#define RK312x_ADCL_ZERO_DET_EN_SFT (5)
|
||||
#define RK312x_ADCL_ZERO_DET_EN (0x1 << 5)
|
||||
#define RK312x_ADCL_ZERO_DET_DIS (0x0 << 5)
|
||||
|
||||
#define RK312x_ADCR_ZERO_DET_EN_SFT (4)
|
||||
#define RK312x_ADCR_ZERO_DET_EN (0x1 << 4)
|
||||
#define RK312x_ADCR_ZERO_DET_DIS (0x0 << 4)
|
||||
|
||||
#define RK312x_MICBIAS_VOL_SHT 0
|
||||
#define RK312x_MICBIAS_VOL_MSK 7
|
||||
#define RK312x_MICBIAS_VOL_MIN (0x0 << 0)
|
||||
#define RK312x_MICBIAS_VOL_MAX (0x7 << 0)
|
||||
|
||||
/* BST_L BST_R CONTROL (0x8C) */
|
||||
#define RK312x_BSTL_PWRD_SFT (6)
|
||||
#define RK312x_BSTL_EN (0x1 << 6)
|
||||
#define RK312x_BSTL_DIS (0x0 << 6)
|
||||
#define RK312x_BSTL_GAIN_SHT (5)
|
||||
#define RK312x_BSTL_GAIN_20 (0x1 << 5)
|
||||
#define RK312x_BSTL_GAIN_0 (0x0 << 5)
|
||||
#define RK312x_BSTL_MUTE_SHT (4)
|
||||
|
||||
#define RK312x_BSTR_PWRD_SFT (2)
|
||||
#define RK312x_BSTR_EN (0x1 << 2)
|
||||
#define RK312x_BSTR_DIS (0x0 << 2)
|
||||
#define RK312x_BSTR_GAIN_SHT (1)
|
||||
#define RK312x_BSTR_GAIN_20 (0x1 << 1)
|
||||
#define RK312x_BSTR_GAIN_0 (0x0 << 1)
|
||||
#define RK312x_BSTR_MUTE_SHT (0)
|
||||
|
||||
|
||||
/* MUXINL ALCL MUXINR ALCR (0x90) */
|
||||
#define RK312x_MUXINL_F_SHT (6)
|
||||
#define RK312x_MUXINL_F_MSK (0x03 << 6)
|
||||
#define RK312x_MUXINL_F_INL (0x02 << 6)
|
||||
#define RK312x_MUXINL_F_BSTL (0x01 << 6)
|
||||
#define RK312x_ALCL_PWR_SHT (5)
|
||||
#define RK312x_ALCL_EN (0x1 << 5)
|
||||
#define RK312x_ALCL_DIS (0x0 << 5)
|
||||
#define RK312x_ALCL_MUTE_SHT (4)
|
||||
#define RK312x_MUXINR_F_SHT (2)
|
||||
#define RK312x_MUXINR_F_MSK (0x03 << 2)
|
||||
#define RK312x_MUXINR_F_INR (0x02 << 2)
|
||||
#define RK312x_MUXINR_F_BSTR (0x01 << 2)
|
||||
#define RK312x_ALCR_PWR_SHT (1)
|
||||
#define RK312x_ALCR_EN (0x1 << 1)
|
||||
#define RK312x_ALCR_DIS (0x0 << 1)
|
||||
#define RK312x_ALCR_MUTE_SHT (0)
|
||||
|
||||
/* BST_L MODE & ALC_L GAIN (0x94) */
|
||||
#define RK312x_BSTL_MODE_SFT (5)
|
||||
#define RK312x_BSTL_MODE_SINGLE (0x1 << 5)
|
||||
#define RK312x_BSTL_MODE_DIFF (0x0 << 5)
|
||||
|
||||
#define RK312x_ALCL_GAIN_SHT (0)
|
||||
#define RK312x_ALCL_GAIN_MSK (0x1f)
|
||||
|
||||
/* ALC_R GAIN (0x98) */
|
||||
#define RK312x_ALCR_GAIN_SHT (0)
|
||||
#define RK312x_ALCR_GAIN_MSK (0x1f)
|
||||
|
||||
/* ADC control (0x9C) */
|
||||
#define RK312x_ADCL_REF_VOL_EN_SFT (3)
|
||||
#define RK312x_ADCL_REF_VOL_EN (0x1 << 7)
|
||||
#define RK312x_ADCL_REF_VOL_DIS (0x0 << 7)
|
||||
|
||||
#define RK312x_ADCL_CLK_EN_SFT (6)
|
||||
#define RK312x_ADCL_CLK_EN (0x1 << 6)
|
||||
#define RK312x_ADCL_CLK_DIS (0x0 << 6)
|
||||
|
||||
#define RK312x_ADCL_AMP_EN_SFT (5)
|
||||
#define RK312x_ADCL_AMP_EN (0x1 << 5)
|
||||
#define RK312x_ADCL_AMP_DIS (0x0 << 5)
|
||||
|
||||
#define RK312x_ADCL_RST_EN (0x1 << 4)
|
||||
#define RK312x_ADCL_RST_DIS (0x0 << 4)
|
||||
|
||||
#define RK312x_ADCR_REF_VOL_EN_SFT (3)
|
||||
#define RK312x_ADCR_REF_VOL_EN (0x1 << 3)
|
||||
#define RK312x_ADCR_REF_VOL_DIS (0x0 << 3)
|
||||
|
||||
#define RK312x_ADCR_CLK_EN_SFT (2)
|
||||
#define RK312x_ADCR_CLK_EN (0x1 << 2)
|
||||
#define RK312x_ADCR_CLK_DIS (0x0 << 2)
|
||||
|
||||
#define RK312x_ADCR_AMP_EN_SFT (1)
|
||||
#define RK312x_ADCR_AMP_EN (0x1 << 1)
|
||||
#define RK312x_ADCR_AMP_DIS (0x0 << 1)
|
||||
|
||||
#define RK312x_ADCR_RST_EN (0x1 << 0)
|
||||
#define RK312x_ADCR_RST_DIS (0x0 << 0)
|
||||
|
||||
/* DAC & VOUT Control (0xa0) */
|
||||
#define RK312x_CURRENT_EN (0x1 << 6)
|
||||
#define RK312x_CURRENT_DIS (0x0 << 6)
|
||||
#define RK312x_REF_VOL_DACL_EN_SFT (5)
|
||||
#define RK312x_REF_VOL_DACL_EN (0x1 << 5)
|
||||
#define RK312x_REF_VOL_DACL_DIS (0x0 << 5)
|
||||
#define RK312x_ZO_DET_VOUTL_SFT (4)
|
||||
#define RK312x_ZO_DET_VOUTL_EN (0x1 << 4)
|
||||
#define RK312x_ZO_DET_VOUTL_DIS (0x0 << 4)
|
||||
#define RK312x_DET_ERAPHONE_DIS (0x0 << 3)
|
||||
#define RK312x_DET_ERAPHONE_EN (0x1 << 3)
|
||||
#define RK312x_REF_VOL_DACR_EN_SFT (1)
|
||||
#define RK312x_REF_VOL_DACR_EN (0x1 << 1)
|
||||
#define RK312x_REF_VOL_DACR_DIS (0x0 << 1)
|
||||
#define RK312x_ZO_DET_VOUTR_SFT (0)
|
||||
#define RK312x_ZO_DET_VOUTR_EN (0x1 << 0)
|
||||
#define RK312x_ZO_DET_VOUTR_DIS (0x0 << 0)
|
||||
|
||||
/* DAC control (0xa4) */
|
||||
#define RK312x_DACL_REF_VOL_EN_SFT (7)
|
||||
#define RK312x_DACL_REF_VOL_EN (0x1 << 7)
|
||||
#define RK312x_DACL_REF_VOL_DIS (0x0 << 7)
|
||||
|
||||
#define RK312x_DACL_CLK_EN (0x1 << 6)
|
||||
#define RK312x_DACL_CLK_DIS (0x0 << 6)
|
||||
|
||||
#define RK312x_DACL_EN (0x1 << 5)
|
||||
#define RK312x_DACL_DIS (0x0 << 5)
|
||||
|
||||
#define RK312x_DACL_INIT (0x0 << 4)
|
||||
#define RK312x_DACL_WORK (0x1 << 4)
|
||||
|
||||
#define RK312x_DACR_REF_VOL_EN_SFT (3)
|
||||
#define RK312x_DACR_REF_VOL_EN (0x1 << 3)
|
||||
#define RK312x_DACR_REF_VOL_DIS (0x0 << 3)
|
||||
|
||||
#define RK312x_DACR_CLK_EN (0x1 << 2)
|
||||
#define RK312x_DACR_CLK_DIS (0x0 << 2)
|
||||
|
||||
#define RK312x_DACR_EN (0x1 << 1)
|
||||
#define RK312x_DACR_DIS (0x0 << 1)
|
||||
|
||||
#define RK312x_DACR_INIT (0x0 << 0)
|
||||
#define RK312x_DACR_WORK (0x1 << 0)
|
||||
|
||||
/* HPMIXL HPMIXR Control (0xa8) */
|
||||
#define RK312x_HPMIXL_SFT (6)
|
||||
#define RK312x_HPMIXL_EN (0x1 << 6)
|
||||
#define RK312x_HPMIXL_DIS (0x0 << 6)
|
||||
#define RK312x_HPMIXL_INIT1 (0x0 << 5)
|
||||
#define RK312x_HPMIXL_WORK1 (0x1 << 5)
|
||||
#define RK312x_HPMIXL_INIT2 (0x0 << 4)
|
||||
#define RK312x_HPMIXL_WORK2 (0x1 << 4)
|
||||
#define RK312x_HPMIXR_SFT (2)
|
||||
#define RK312x_HPMIXR_EN (0x1 << 2)
|
||||
#define RK312x_HPMIXR_DIS (0x0 << 2)
|
||||
#define RK312x_HPMIXR_INIT1 (0x0 << 1)
|
||||
#define RK312x_HPMIXR_WORK1 (0x1 << 1)
|
||||
#define RK312x_HPMIXR_INIT2 (0x0 << 0)
|
||||
#define RK312x_HPMIXR_WORK2 (0x1 << 0)
|
||||
|
||||
/* HPMIXL Control (0xac) */
|
||||
#define RK312x_HPMIXL_BYPASS_SFT (7)
|
||||
#define RK312x_HPMIXL_SEL_ALCL_SFT (6)
|
||||
#define RK312x_HPMIXL_SEL_ALCR_SFT (5)
|
||||
#define RK312x_HPMIXL_SEL_DACL_SFT (4)
|
||||
#define RK312x_HPMIXR_BYPASS_SFT (3)
|
||||
#define RK312x_HPMIXR_SEL_ALCL_SFT (2)
|
||||
#define RK312x_HPMIXR_SEL_ALCR_SFT (1)
|
||||
#define RK312x_HPMIXR_SEL_DACR_SFT (0)
|
||||
|
||||
/* HPOUT Control (0xb0) */
|
||||
#define RK312x_HPOUTL_PWR_SHT (7)
|
||||
#define RK312x_HPOUTL_MSK (0x1 << 7)
|
||||
#define RK312x_HPOUTL_EN (0x1 << 7)
|
||||
#define RK312x_HPOUTL_DIS (0x0 << 7)
|
||||
#define RK312x_HPOUTL_INIT_MSK (0x1 << 6)
|
||||
#define RK312x_HPOUTL_INIT (0x0 << 6)
|
||||
#define RK312x_HPOUTL_WORK (0x1 << 6)
|
||||
#define RK312x_HPOUTL_MUTE_SHT (5)
|
||||
#define RK312x_HPOUTL_MUTE_MSK (0x1 << 5)
|
||||
#define RK312x_HPOUTL_MUTE_EN (0x0 << 5)
|
||||
#define RK312x_HPOUTL_MUTE_DIS (0x1 << 5)
|
||||
#define RK312x_HPOUTR_PWR_SHT (4)
|
||||
#define RK312x_HPOUTR_MSK (0x1 << 4)
|
||||
#define RK312x_HPOUTR_EN (0x1 << 4)
|
||||
#define RK312x_HPOUTR_DIS (0x0 << 4)
|
||||
#define RK312x_HPOUTR_INIT_MSK (0x1 << 3)
|
||||
#define RK312x_HPOUTR_WORK (0x1 << 3)
|
||||
#define RK312x_HPOUTR_INIT (0x0 << 3)
|
||||
#define RK312x_HPOUTR_MUTE_SHT (2)
|
||||
#define RK312x_HPOUTR_MUTE_MSK (0x1 << 2)
|
||||
#define RK312x_HPOUTR_MUTE_EN (0x0 << 2)
|
||||
#define RK312x_HPOUTR_MUTE_DIS (0x1 << 2)
|
||||
|
||||
#define RK312x_HPVREF_PWR_SHT (1)
|
||||
#define RK312x_HPVREF_EN (0x1 << 1)
|
||||
#define RK312x_HPVREF_DIS (0x0 << 1)
|
||||
#define RK312x_HPVREF_WORK (0x1 << 0)
|
||||
#define RK312x_HPVREF_INIT (0x0 << 0)
|
||||
|
||||
/* HPOUT GAIN (0xb4 0xb8) */
|
||||
#define RK312x_HPOUT_GAIN_SFT (0)
|
||||
|
||||
/* SELECT CURR prechagrge/discharge (0xbc) */
|
||||
#define RK312x_PRE_HPOUT (0x1 << 5)
|
||||
#define RK312x_DIS_HPOUT (0x0 << 5)
|
||||
#define RK312x_CUR_10UA_EN (0x0 << 4)
|
||||
#define RK312x_CUR_10UA_DIS (0x1 << 4)
|
||||
#define RK312x_CUR_I_EN (0x0 << 3)
|
||||
#define RK312x_CUR_I_DIS (0x1 << 3)
|
||||
#define RK312x_CUR_2I_EN (0x0 << 2)
|
||||
#define RK312x_CUR_2I_DIS (0x1 << 2)
|
||||
#define RK312x_CUR_4I_EN (0x0 << 0)
|
||||
#define RK312x_CUR_4I_DIS (0x3 << 0)
|
||||
|
||||
/* PGA AGC control 1 (0xc0 0x100) */
|
||||
#define RK312x_PGA_AGC_WAY_MASK (0x1 << 6)
|
||||
#define RK312x_PGA_AGC_WAY_SFT 6
|
||||
#define RK312x_PGA_AGC_WAY_JACK (0x1 << 6)
|
||||
#define RK312x_PGA_AGC_WAY_NOR (0x0 << 6)
|
||||
|
||||
#define RK312x_PGA_AGC_BK_WAY_SFT 4
|
||||
#define RK312x_PGA_AGC_BK_WAY_JACK1 (0x1 << 4)
|
||||
#define RK312x_PGA_AGC_BK_WAY_NOR (0x0 << 4)
|
||||
#define RK312x_PGA_AGC_BK_WAY_JACK2 (0x2 << 4)
|
||||
#define RK312x_PGA_AGC_BK_WAY_JACK3 (0x3 << 4)
|
||||
|
||||
#define RK312x_PGA_AGC_HOLD_T_MASK 0xf
|
||||
#define RK312x_PGA_AGC_HOLD_T_SFT 0
|
||||
#define RK312x_PGA_AGC_HOLD_T_1024 0xa
|
||||
#define RK312x_PGA_AGC_HOLD_T_512 0x9
|
||||
#define RK312x_PGA_AGC_HOLD_T_256 0x8
|
||||
#define RK312x_PGA_AGC_HOLD_T_128 0x7
|
||||
#define RK312x_PGA_AGC_HOLD_T_64 0x6
|
||||
#define RK312x_PGA_AGC_HOLD_T_32 0x5
|
||||
#define RK312x_PGA_AGC_HOLD_T_16 0x4
|
||||
#define RK312x_PGA_AGC_HOLD_T_8 0x3
|
||||
#define RK312x_PGA_AGC_HOLD_T_4 0x2
|
||||
#define RK312x_PGA_AGC_HOLD_T_2 0x1
|
||||
#define RK312x_PGA_AGC_HOLD_T_0 0x0
|
||||
|
||||
/* PGA AGC control 2 (0xc4 0x104) */
|
||||
#define RK312x_PGA_AGC_GRU_T_MASK (0xf << 4)
|
||||
#define RK312x_PGA_AGC_GRU_T_SFT 4
|
||||
#define RK312x_PGA_AGC_GRU_T_512 (0xa << 4)
|
||||
#define RK312x_PGA_AGC_GRU_T_256 (0x9 << 4)
|
||||
#define RK312x_PGA_AGC_GRU_T_128 (0x8 << 4)
|
||||
#define RK312x_PGA_AGC_GRU_T_64 (0x7 << 4)
|
||||
#define RK312x_PGA_AGC_GRU_T_32 (0x6 << 4)
|
||||
#define RK312x_PGA_AGC_GRU_T_16 (0x5 << 4)
|
||||
#define RK312x_PGA_AGC_GRU_T_8 (0x4 << 4)
|
||||
#define RK312x_PGA_AGC_GRU_T_4 (0x3 << 4)
|
||||
#define RK312x_PGA_AGC_GRU_T_2 (0x2 << 4)
|
||||
#define RK312x_PGA_AGC_GRU_T_1 (0x1 << 4)
|
||||
#define RK312x_PGA_AGC_GRU_T_0_5 (0x0 << 4)
|
||||
|
||||
#define RK312x_PGA_AGC_GRD_T_MASK 0xf
|
||||
#define RK312x_PGA_AGC_GRD_T_SFT 0
|
||||
#define RK312x_PGA_AGC_GRD_T_128_32 0xa
|
||||
#define RK312x_PGA_AGC_GRD_T_64_16 0x9
|
||||
#define RK312x_PGA_AGC_GRD_T_32_8 0x8
|
||||
#define RK312x_PGA_AGC_GRD_T_16_4 0x7
|
||||
#define RK312x_PGA_AGC_GRD_T_8_2 0x6
|
||||
#define RK312x_PGA_AGC_GRD_T_4_1 0x5
|
||||
#define RK312x_PGA_AGC_GRD_T_2_0_512 0x4
|
||||
#define RK312x_PGA_AGC_GRD_T_1_0_256 0x3
|
||||
#define RK312x_PGA_AGC_GRD_T_0_500_128 0x2
|
||||
#define RK312x_PGA_AGC_GRD_T_0_250_64 0x1
|
||||
#define RK312x_PGA_AGC_GRD_T_0_125_32 0x0
|
||||
|
||||
/* PGA AGC control 3 (0xc8 0x108) */
|
||||
#define RK312x_PGA_AGC_MODE_MASK (0x1 << 7)
|
||||
#define RK312x_PGA_AGC_MODE_SFT 7
|
||||
#define RK312x_PGA_AGC_MODE_LIMIT (0x1 << 7)
|
||||
#define RK312x_PGA_AGC_MODE_NOR (0x0 << 7)
|
||||
|
||||
#define RK312x_PGA_AGC_ZO_MASK (0x1 << 6)
|
||||
#define RK312x_PGA_AGC_ZO_SFT 6
|
||||
#define RK312x_PGA_AGC_ZO_EN (0x1 << 6)
|
||||
#define RK312x_PGA_AGC_ZO_DIS (0x0 << 6)
|
||||
|
||||
#define RK312x_PGA_AGC_REC_MODE_MASK (0x1 << 5)
|
||||
#define RK312x_PGA_AGC_REC_MODE_SFT 5
|
||||
#define RK312x_PGA_AGC_REC_MODE_AC (0x1 << 5)
|
||||
#define RK312x_PGA_AGC_REC_MODE_RN (0x0 << 5)
|
||||
|
||||
#define RK312x_PGA_AGC_FAST_D_MASK (0x1 << 4)
|
||||
#define RK312x_PGA_AGC_FAST_D_SFT 4
|
||||
#define RK312x_PGA_AGC_FAST_D_EN (0x1 << 4)
|
||||
#define RK312x_PGA_AGC_FAST_D_DIS (0x0 << 4)
|
||||
|
||||
#define RK312x_PGA_AGC_NG_MASK (0x1 << 3)
|
||||
#define RK312x_PGA_AGC_NG_SFT 3
|
||||
#define RK312x_PGA_AGC_NG_EN (0x1 << 3)
|
||||
#define RK312x_PGA_AGC_NG_DIS (0x0 << 3)
|
||||
|
||||
#define RK312x_PGA_AGC_NG_THR_MASK 0x7
|
||||
#define RK312x_PGA_AGC_NG_THR_SFT 0
|
||||
#define RK312x_PGA_AGC_NG_THR_N81DB 0x7
|
||||
#define RK312x_PGA_AGC_NG_THR_N75DB 0x6
|
||||
#define RK312x_PGA_AGC_NG_THR_N69DB 0x5
|
||||
#define RK312x_PGA_AGC_NG_THR_N63DB 0x4
|
||||
#define RK312x_PGA_AGC_NG_THR_N57DB 0x3
|
||||
#define RK312x_PGA_AGC_NG_THR_N51DB 0x2
|
||||
#define RK312x_PGA_AGC_NG_THR_N45DB 0x1
|
||||
#define RK312x_PGA_AGC_NG_THR_N39DB 0x0
|
||||
|
||||
/* PGA AGC Control 4 (0xcc 0x10c) */
|
||||
#define RK312x_PGA_AGC_ZO_MODE_MASK (0x1 << 5)
|
||||
#define RK312x_PGA_AGC_ZO_MODE_SFT 5
|
||||
#define RK312x_PGA_AGC_ZO_MODE_UWRC (0x1 << 5)
|
||||
#define RK312x_PGA_AGC_ZO_MODE_UARC (0x0 << 5)
|
||||
|
||||
#define RK312x_PGA_AGC_VOL_MASK 0x1f
|
||||
#define RK312x_PGA_AGC_VOL_SFT 0
|
||||
|
||||
/* PGA ASR Control (0xd0 0x110) */
|
||||
#define RK312x_PGA_SLOW_CLK_MASK (0x1 << 3)
|
||||
#define RK312x_PGA_SLOW_CLK_SFT 3
|
||||
#define RK312x_PGA_SLOW_CLK_EN (0x1 << 3)
|
||||
#define RK312x_PGA_SLOW_CLK_DIS (0x0 << 3)
|
||||
|
||||
#define RK312x_PGA_ASR_MASK 0x7
|
||||
#define RK312x_PGA_ASR_SFT 0
|
||||
#define RK312x_PGA_ASR_8KHz 0x7
|
||||
#define RK312x_PGA_ASR_12KHz 0x6
|
||||
#define RK312x_PGA_ASR_16KHz 0x5
|
||||
#define RK312x_PGA_ASR_24KHz 0x4
|
||||
#define RK312x_PGA_ASR_32KHz 0x3
|
||||
#define RK312x_PGA_ASR_441KHz 0x2
|
||||
#define RK312x_PGA_ASR_48KHz 0x1
|
||||
#define RK312x_PGA_ASR_96KHz 0x0
|
||||
|
||||
/* PGA AGC Control 5 (0xe4 0x124) */
|
||||
#define RK312x_PGA_AGC_MASK (0x1 << 6)
|
||||
#define RK312x_PGA_AGC_SFT 6
|
||||
#define RK312x_PGA_AGC_EN (0x1 << 6)
|
||||
#define RK312x_PGA_AGC_DIS (0x0 << 6)
|
||||
|
||||
#define RK312x_PGA_AGC_MAX_G_MASK (0x7 << 3)
|
||||
#define RK312x_PGA_AGC_MAX_G_SFT 3
|
||||
#define RK312x_PGA_AGC_MAX_G_28_5DB (0x7 << 3)
|
||||
#define RK312x_PGA_AGC_MAX_G_22_5DB (0x6 << 3)
|
||||
#define RK312x_PGA_AGC_MAX_G_16_5DB (0x5 << 3)
|
||||
#define RK312x_PGA_AGC_MAX_G_10_5DB (0x4 << 3)
|
||||
#define RK312x_PGA_AGC_MAX_G_4_5DB (0x3 << 3)
|
||||
#define RK312x_PGA_AGC_MAX_G_N1_5DB (0x2 << 3)
|
||||
#define RK312x_PGA_AGC_MAX_G_N7_5DB (0x1 << 3)
|
||||
#define RK312x_PGA_AGC_MAX_G_N13_5DB (0x0 << 3)
|
||||
|
||||
#define RK312x_PGA_AGC_MIN_G_MASK 0x7
|
||||
#define RK312x_PGA_AGC_MIN_G_SFT 0
|
||||
#define RK312x_PGA_AGC_MIN_G_24DB 0x7
|
||||
#define RK312x_PGA_AGC_MIN_G_18DB 0x6
|
||||
#define RK312x_PGA_AGC_MIN_G_12DB 0x5
|
||||
#define RK312x_PGA_AGC_MIN_G_6DB 0x4
|
||||
#define RK312x_PGA_AGC_MIN_G_0DB 0x3
|
||||
#define RK312x_PGA_AGC_MIN_G_N6DB 0x2
|
||||
#define RK312x_PGA_AGC_MIN_G_N12DB 0x1
|
||||
#define RK312x_PGA_AGC_MIN_G_N18DB 0x0
|
||||
|
||||
enum {
|
||||
RK312x_HIFI,
|
||||
RK312x_VOICE,
|
||||
};
|
||||
|
||||
enum {
|
||||
RK312x_MONO = 1,
|
||||
RK312x_STEREO,
|
||||
};
|
||||
|
||||
enum {
|
||||
OFF,
|
||||
RCV,
|
||||
SPK_PATH,
|
||||
HP_PATH,
|
||||
HP_NO_MIC,
|
||||
BT,
|
||||
SPK_HP,
|
||||
RING_SPK,
|
||||
RING_HP,
|
||||
RING_HP_NO_MIC,
|
||||
RING_SPK_HP,
|
||||
};
|
||||
|
||||
enum {
|
||||
MIC_OFF,
|
||||
Main_Mic,
|
||||
Hands_Free_Mic,
|
||||
BT_Sco_Mic,
|
||||
};
|
||||
|
||||
struct rk312x_reg_val_typ {
|
||||
unsigned int reg;
|
||||
unsigned int value;
|
||||
};
|
||||
|
||||
struct rk312x_init_bit_typ {
|
||||
unsigned int reg;
|
||||
unsigned int power_bit;
|
||||
unsigned int init2_bit;
|
||||
unsigned int init1_bit;
|
||||
unsigned int init0_bit;
|
||||
};
|
||||
|
||||
struct rk312x_codec_pdata {
|
||||
int spk_ctl_gpio;
|
||||
int hp_ctl_gpio;
|
||||
int delay_time;
|
||||
};
|
||||
|
||||
#endif /* __RK312x_CODEC_H__ */
|
||||
@@ -249,6 +249,15 @@ config SND_RK_SOC_RK3036
|
||||
Say Y if you want to add support for SoC audio on rockchip
|
||||
with the RK3036 s40.
|
||||
|
||||
config SND_RK_SOC_RK312X
|
||||
tristate "SoC I2S Audio support for rockchip - RK312X"
|
||||
depends on SND_RK_SOC
|
||||
select SND_RK_SOC_I2S
|
||||
select SND_SOC_RK312X
|
||||
help
|
||||
Say Y if you want to add support for SoC audio on rockchip
|
||||
with the RK3036 s40.
|
||||
|
||||
config SND_RK_SOC_RK610
|
||||
tristate "SoC I2S Audio support for rockchip - RK610"
|
||||
depends on SND_RK_SOC && MFD_RK610
|
||||
|
||||
@@ -28,6 +28,7 @@ snd-soc-aic3111-objs := rk_aic3111.o
|
||||
snd-soc-wm8988-objs := rk_wm8988.o
|
||||
snd-soc-rk1000-objs := rk_rk1000codec.o
|
||||
snd-soc-rk3036-objs := rk_rk3036.o
|
||||
snd-soc-rk312x-objs := rk_rk312x.o
|
||||
snd-soc-wm8994-objs := rk_wm8994.o
|
||||
snd-soc-rk610-objs := rk_jetta_codec.o
|
||||
snd-soc-rk616-objs := rk_rk616.o
|
||||
@@ -56,6 +57,7 @@ obj-$(CONFIG_SND_RK_SOC_RT5639) += snd-soc-rt5639.o
|
||||
obj-$(CONFIG_SND_RK_SOC_RT5616) += snd-soc-rt5616.o
|
||||
obj-$(CONFIG_SND_RK_SOC_RK1000) += snd-soc-rk1000.o
|
||||
obj-$(CONFIG_SND_RK_SOC_RK3036) += snd-soc-rk3036.o
|
||||
obj-$(CONFIG_SND_RK_SOC_RK312X) += snd-soc-rk312x.o
|
||||
obj-$(CONFIG_SND_RK_SOC_CS42L52) += snd-soc-cs42l52.o
|
||||
obj-$(CONFIG_SND_RK_SOC_AIC3111) += snd-soc-aic3111.o
|
||||
obj-$(CONFIG_SND_RK_SOC_AIC3262) += snd-soc-aic3262.o
|
||||
|
||||
297
sound/soc/rockchip/rk_rk312x.c
Executable file
297
sound/soc/rockchip/rk_rk312x.c
Executable file
@@ -0,0 +1,297 @@
|
||||
/*
|
||||
* rk_rk312x.c -- SoC audio for rockchip
|
||||
*
|
||||
* Driver for rockchip rk312x audio
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_gpio.h>
|
||||
#include <sound/core.h>
|
||||
#include <sound/pcm.h>
|
||||
#include <sound/soc.h>
|
||||
#include <sound/soc-dapm.h>
|
||||
|
||||
#include "../codecs/rk312x_codec.h"
|
||||
#include "card_info.h"
|
||||
#include "rk_pcm.h"
|
||||
#include "rk_i2s.h"
|
||||
|
||||
#if 1
|
||||
#define DBG(x...) pr_info("rk_rk312x" x)
|
||||
#else
|
||||
#define DBG(x...)
|
||||
#endif
|
||||
|
||||
static const struct snd_soc_dapm_widget rk_dapm_widgets[] = {
|
||||
SND_SOC_DAPM_MIC("Mic Jack", NULL),
|
||||
SND_SOC_DAPM_MIC("Headset Jack", NULL),
|
||||
SND_SOC_DAPM_SPK("Ext Spk", NULL),
|
||||
SND_SOC_DAPM_HP("Headphone Jack", NULL),
|
||||
};
|
||||
|
||||
static const struct snd_soc_dapm_route rk_audio_map[] = {
|
||||
/* Mic Jack --> MIC_IN*/
|
||||
{"Mic Bias", NULL, "Mic Jack"},
|
||||
{"MICP", NULL, "Mic Bias"},
|
||||
{"MICN", NULL, "Mic Bias"},
|
||||
|
||||
/* HP MIC */
|
||||
{"Mic Bias", NULL, "Headset Jack"},
|
||||
|
||||
{"Ext Spk", NULL, "HPOUTR"},
|
||||
{"Ext Spk", NULL, "HPOUTL"},
|
||||
|
||||
{"Headphone Jack", NULL, "HPOUTR"},
|
||||
{"Headphone Jack", NULL, "HPOUTL"},
|
||||
};
|
||||
|
||||
static const struct snd_kcontrol_new rk_controls[] = {
|
||||
SOC_DAPM_PIN_SWITCH("Mic Jack"),
|
||||
SOC_DAPM_PIN_SWITCH("Headset Jack"),
|
||||
SOC_DAPM_PIN_SWITCH("Ext Spk"),
|
||||
SOC_DAPM_PIN_SWITCH("Headphone Jack"),
|
||||
};
|
||||
|
||||
static int rk312x_init(struct snd_soc_pcm_runtime *rtd)
|
||||
{
|
||||
struct snd_soc_codec *codec = rtd->codec;
|
||||
struct snd_soc_dapm_context *dapm = &codec->dapm;
|
||||
|
||||
DBG("Enter::%s----%d\n", __func__, __LINE__);
|
||||
|
||||
mutex_lock(&dapm->card->dapm_mutex);
|
||||
|
||||
snd_soc_dapm_enable_pin(dapm, "Mic Jack");
|
||||
snd_soc_dapm_enable_pin(dapm, "Headset Jack");
|
||||
snd_soc_dapm_enable_pin(dapm, "Ext Spk");
|
||||
snd_soc_dapm_enable_pin(dapm, "Headphone Jack");
|
||||
|
||||
mutex_unlock(&dapm->card->dapm_mutex);
|
||||
|
||||
snd_soc_dapm_sync(dapm);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk_hifi_hw_params(struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params)
|
||||
{
|
||||
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
||||
struct snd_soc_dai *codec_dai = rtd->codec_dai;
|
||||
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
|
||||
unsigned int pll_out = 0, dai_fmt = rtd->dai_link->dai_fmt;
|
||||
int ret;
|
||||
|
||||
DBG("Enter::%s----%d\n", __func__, __LINE__);
|
||||
|
||||
/* set codec DAI configuration */
|
||||
ret = snd_soc_dai_set_fmt(codec_dai, dai_fmt);
|
||||
if (ret < 0) {
|
||||
DBG("%s():failed to set the format for codec side\n",
|
||||
__func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* set cpu DAI configuration */
|
||||
ret = snd_soc_dai_set_fmt(cpu_dai, dai_fmt);
|
||||
if (ret < 0) {
|
||||
DBG("%s():failed to set the format for cpu side\n",
|
||||
__func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
switch (params_rate(params)) {
|
||||
case 8000:
|
||||
case 16000:
|
||||
case 24000:
|
||||
case 32000:
|
||||
case 48000:
|
||||
pll_out = 12288000;
|
||||
break;
|
||||
case 11025:
|
||||
case 22050:
|
||||
case 44100:
|
||||
pll_out = 11289600;
|
||||
break;
|
||||
default:
|
||||
DBG("Enter:%s, %d, Error rate=%d\n",
|
||||
__func__, __LINE__, params_rate(params));
|
||||
return -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
DBG("Enter:%s, %d, rate=%d\n",
|
||||
__func__, __LINE__, params_rate(params));
|
||||
|
||||
/*Set the system clk for codec*/
|
||||
ret = snd_soc_dai_set_sysclk(codec_dai, 0, pll_out, SND_SOC_CLOCK_IN);
|
||||
if (ret < 0) {
|
||||
DBG("rk_hifi_hw_params:failed to set the sysclk for codec\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
snd_soc_dai_set_sysclk(cpu_dai, 0, pll_out, 0);
|
||||
snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_BCLK,
|
||||
(pll_out/4)/params_rate(params)-1);
|
||||
snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_MCLK, 3);
|
||||
DBG("Enter:%s, %d, pll_out/4/params_rate(params) = %d \n",
|
||||
__func__, __LINE__, (pll_out/4)/params_rate(params));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk_voice_hw_params(struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params)
|
||||
{
|
||||
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
||||
struct snd_soc_dai *codec_dai = rtd->codec_dai;
|
||||
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
|
||||
unsigned int pll_out = 0, dai_fmt = rtd->dai_link->dai_fmt;
|
||||
int ret;
|
||||
|
||||
DBG("Enter::%s----%d\n", __func__, __LINE__);
|
||||
|
||||
/* set codec DAI configuration */
|
||||
ret = snd_soc_dai_set_fmt(codec_dai, dai_fmt);
|
||||
if (ret < 0) {
|
||||
DBG("%s():failed to set the format for codec side\n",
|
||||
__func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* set codec DAI configuration */
|
||||
ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A |
|
||||
SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBS_CFS);
|
||||
|
||||
switch (params_rate(params)) {
|
||||
case 8000:
|
||||
case 16000:
|
||||
case 24000:
|
||||
case 32000:
|
||||
case 48000:
|
||||
pll_out = 12288000;
|
||||
break;
|
||||
case 11025:
|
||||
case 22050:
|
||||
case 44100:
|
||||
pll_out = 11289600;
|
||||
break;
|
||||
default:
|
||||
DBG("Enter:%s, %d, Error rate=%d\n",
|
||||
__func__, __LINE__,
|
||||
params_rate(params));
|
||||
return -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
/*Set the system clk for codec*/
|
||||
ret = snd_soc_dai_set_sysclk(codec_dai, 0, pll_out, SND_SOC_CLOCK_IN);
|
||||
|
||||
if (ret < 0) {
|
||||
DBG("rk_voice_hw_params:failed to set codec side\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = snd_soc_dai_set_sysclk(cpu_dai, 0, pll_out, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct snd_soc_ops rk312x_hifi_ops = {
|
||||
.hw_params = rk_hifi_hw_params,
|
||||
};
|
||||
|
||||
static struct snd_soc_ops rk312x_voice_ops = {
|
||||
.hw_params = rk_voice_hw_params,
|
||||
};
|
||||
|
||||
static struct snd_soc_dai_link rk_dai[] = {
|
||||
{
|
||||
.name = "RK312X I2S1",
|
||||
.stream_name = "RK312X PCM",
|
||||
.codec_dai_name = "rk312x-hifi",
|
||||
.init = rk312x_init,
|
||||
.ops = &rk312x_hifi_ops,
|
||||
},
|
||||
{
|
||||
.name = "RK312X I2S2",
|
||||
.stream_name = "RK312X PCM",
|
||||
.codec_dai_name = "rk312x-voice",
|
||||
.ops = &rk312x_voice_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct snd_soc_card rockchip_rk312x_snd_card = {
|
||||
.name = "RK_RK312X",
|
||||
.dai_link = rk_dai,
|
||||
.num_links = 2,
|
||||
.controls = rk_controls,
|
||||
.num_controls = ARRAY_SIZE(rk_controls),
|
||||
.dapm_widgets = rk_dapm_widgets,
|
||||
.num_dapm_widgets = ARRAY_SIZE(rk_dapm_widgets),
|
||||
.dapm_routes = rk_audio_map,
|
||||
.num_dapm_routes = ARRAY_SIZE(rk_audio_map),
|
||||
};
|
||||
|
||||
static int rockchip_rk312x_audio_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
struct snd_soc_card *card = &rockchip_rk312x_snd_card;
|
||||
|
||||
card->dev = &pdev->dev;
|
||||
ret = rockchip_of_get_sound_card_info(card);
|
||||
if (ret) {
|
||||
DBG("%s() get sound card info failed:%d\n", __func__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = snd_soc_register_card(card);
|
||||
if (ret)
|
||||
DBG("%s() register card failed:%d\n", __func__, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rockchip_rk312x_audio_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct snd_soc_card *card = platform_get_drvdata(pdev);
|
||||
|
||||
snd_soc_unregister_card(card);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static const struct of_device_id rockchip_rk312x_of_match[] = {
|
||||
{ .compatible = "audio-rk312x", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rockchip_rk312x_of_match);
|
||||
#endif /* CONFIG_OF */
|
||||
|
||||
static struct platform_driver rockchip_rk312x_audio_driver = {
|
||||
.driver = {
|
||||
.name = "audio-rk312x",
|
||||
.owner = THIS_MODULE,
|
||||
.pm = &snd_soc_pm_ops,
|
||||
.of_match_table = of_match_ptr(rockchip_rk312x_of_match),
|
||||
},
|
||||
.probe = rockchip_rk312x_audio_probe,
|
||||
.remove = rockchip_rk312x_audio_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(rockchip_rk312x_audio_driver);
|
||||
|
||||
/* Module information */
|
||||
MODULE_AUTHOR("rockchip");
|
||||
MODULE_DESCRIPTION("ROCKCHIP i2s ASoC Interface");
|
||||
MODULE_LICENSE("GPL");
|
||||
15
sound/soc/rockchip/rk_spdif.c
Normal file → Executable file
15
sound/soc/rockchip/rk_spdif.c
Normal file → Executable file
@@ -43,7 +43,7 @@
|
||||
#include "rk_pcm.h"
|
||||
|
||||
#undef DEBUG_SPDIF
|
||||
#define DEBUG_SPDIF 0
|
||||
#define DEBUG_SPDIF 1
|
||||
|
||||
#if DEBUG_SPDIF
|
||||
#define RK_SPDIF_DBG(x...) pr_info("rk_spdif:"x)
|
||||
@@ -140,6 +140,7 @@ struct rockchip_spdif_info {
|
||||
spinlock_t lock;/*lock parmeter setting.*/
|
||||
void __iomem *regs;
|
||||
unsigned long clk_rate;
|
||||
struct clk *hclk;
|
||||
struct clk *clk;
|
||||
struct snd_dmaengine_dai_dma_data dma_playback;
|
||||
};
|
||||
@@ -453,6 +454,14 @@ static int spdif_probe(struct platform_device *pdev)
|
||||
goto err_;
|
||||
}
|
||||
|
||||
/* get spdif clock and init. */
|
||||
spdif->hclk = devm_clk_get(&pdev->dev, "spdif_hclk");
|
||||
if (IS_ERR(spdif->hclk)) {
|
||||
dev_err(&pdev->dev, "Can't retrieve spdif hclock\n");
|
||||
spdif->hclk = NULL;
|
||||
}
|
||||
clk_prepare_enable(spdif->hclk);
|
||||
|
||||
/* get spdif clock and init. */
|
||||
spdif->clk = devm_clk_get(&pdev->dev, "spdif_mclk");
|
||||
if (IS_ERR(spdif->clk)) {
|
||||
@@ -507,7 +516,7 @@ static int spdif_remove(struct platform_device *pdev)
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static const struct of_device_id exynos_spdif_match[] = {
|
||||
{ .compatible = "rockchip-spdif"},
|
||||
{ .compatible = "rk312x-spdif"},
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, exynos_spdif_match);
|
||||
@@ -517,7 +526,7 @@ static struct platform_driver rockchip_spdif_driver = {
|
||||
.probe = spdif_probe,
|
||||
.remove = spdif_remove,
|
||||
.driver = {
|
||||
.name = "rockchip-spdif",
|
||||
.name = "rk312x-spdif",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(exynos_spdif_match),
|
||||
},
|
||||
|
||||
Reference in New Issue
Block a user