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drm/rockchip: vop2: filter unsupported mode when can't get correct dclk

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For rk3576 and rk3588, vop dclk can be from pll or hdmi phy[except hdmi
2.1(dclk bigger than 597M), the HDMI work at FRL mode], when dclk is
from pll, dclk_parent is equal to dclk, we need clk_round_rate() for dclk_parent to
check whether can support this mode.

1. GPLL/CPLL/VPLL
       dclk_parent
           dclk

2. xin24m
       clk_hdmiphy_pixel0
           dclk

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I4541d41c3fda5b8ff989e19e8dbf686b15e81216
This commit is contained in:
Sandy Huang
2024-03-30 16:40:17 +08:00
parent 2ce0e75bee
commit aebca4f07f
1 changed files with 2 additions and 1 deletions
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3
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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@@ -7244,7 +7244,8 @@ vop2_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
else if (vop2->version == VOP_VERSION_RK3588)
request_clock = request_clock >> 2;
}
clock = rockchip_drm_dclk_round_rate(vop2->version, vp->dclk,
clock = rockchip_drm_dclk_round_rate(vop2->version,
vp->dclk_parent ? vp->dclk_parent : vp->dclk,
request_clock * 1000) / 1000;
}