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media: rockchip: vicap support rv1106

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Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I1a8f4a8a7e80494eef9991a7551762bc4c6267f6
This commit is contained in:
Zefa Chen
2022-01-24 20:24:30 +08:00
committed by Tao Huang
parent 1f622163d8
commit af227dbe4a
5 changed files with 450 additions and 71 deletions
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259
drivers/media/platform/rockchip/cif/capture.c
View File

@@ -772,6 +772,31 @@ static enum cif_reg_index get_reg_index_of_id_ctrl0(int channel_id)
return index;
}
static enum cif_reg_index get_reg_index_of_lvds_id_ctrl0(int channel_id)
{
enum cif_reg_index index;
switch (channel_id) {
case 0:
index = CIF_REG_LVDS_ID0_CTRL0;
break;
case 1:
index = CIF_REG_LVDS_ID1_CTRL0;
break;
case 2:
index = CIF_REG_LVDS_ID2_CTRL0;
break;
case 3:
index = CIF_REG_LVDS_ID3_CTRL0;
break;
default:
index = CIF_REG_LVDS_ID0_CTRL0;
break;
}
return index;
}
static enum cif_reg_index get_reg_index_of_id_ctrl1(int channel_id)
{
enum cif_reg_index index;
@@ -1977,7 +2002,7 @@ static unsigned char get_csi_fmt_val(const struct cif_input_fmt *cif_fmt_in,
} else if (cif_fmt_in->csi_fmt_val == CSI_WRDDR_TYPE_RGB888) {
csi_fmt_val = CSI_WRDDR_TYPE_RAW8;
} else {
csi_fmt_val = cif_fmt_in->csi_fmt_val;
csi_fmt_val = cif_fmt_in->csi_fmt_val;
}
return csi_fmt_val;
}
@@ -2043,7 +2068,7 @@ static int rkcif_csi_channel_init(struct rkcif_stream *stream,
* and the width is double Because the real input fmt is
* yuyv
*/
fourcc = stream->cif_fmt_out->fourcc;
fourcc = stream->cif_fmt_out->fourcc;
if (fourcc == V4L2_PIX_FMT_YUYV || fourcc == V4L2_PIX_FMT_YVYU ||
fourcc == V4L2_PIX_FMT_UYVY || fourcc == V4L2_PIX_FMT_VYUY) {
channel->fmt_val = CSI_WRDDR_TYPE_RAW8;
@@ -2131,9 +2156,9 @@ static int rkcif_csi_channel_set(struct rkcif_stream *stream,
CIF_MIPI_LVDS_SW_HURRY_ENABLE |
CIF_MIPI_LVDS_SW_WATER_LINE_25 |
CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE;
if (mbus_type == V4L2_MBUS_CSI2_DPHY) {
if (mbus_type == V4L2_MBUS_CSI2_DPHY) {
val &= ~CIF_MIPI_LVDS_SW_SEL_LVDS;
} else if (mbus_type == V4L2_MBUS_CCP2) {
} else if (mbus_type == V4L2_MBUS_CCP2) {
if (channel->fmt_val == CSI_WRDDR_TYPE_RAW12)
val |= CIF_MIPI_LVDS_SW_LVDS_WIDTH_12BITS;
else if (channel->fmt_val == CSI_WRDDR_TYPE_RAW10)
@@ -2168,7 +2193,7 @@ static int rkcif_csi_channel_set(struct rkcif_stream *stream,
RKCIF_YUV_ADDR_STATE_INIT,
channel->id);
if (mbus_type == V4L2_MBUS_CSI2_DPHY) {
if (mbus_type == V4L2_MBUS_CSI2_DPHY) {
//need always enable crop
val = CSI_ENABLE_CAPTURE | channel->fmt_val |
channel->cmd_mode_en << 4 | CSI_ENABLE_CROP |
@@ -2180,7 +2205,7 @@ static int rkcif_csi_channel_set(struct rkcif_stream *stream,
if (stream->cifdev->chip_id >= CHIP_RK3568_CIF)
val |= stream->cif_fmt_in->csi_yuv_order;
} else if (mbus_type == V4L2_MBUS_CCP2) {
} else if (mbus_type == V4L2_MBUS_CCP2) {
rkcif_csi_set_lvds_sav_eav(stream, channel);
val = LVDS_ENABLE_CAPTURE | LVDS_MODE(channel->lvds_cfg.mode) |
LVDS_MAIN_LANE(0) | LVDS_FID(0) |
@@ -2294,6 +2319,90 @@ static int rkcif_csi_get_output_type_mask(struct rkcif_stream *stream)
return mask;
}
static int rkcif_lvds_get_output_type_mask(struct rkcif_stream *stream)
{
unsigned int mask;
const struct cif_output_fmt *fmt = stream->cif_fmt_out;
int wr_type_offset = 0;
int yuvout_offset = 0;
if (stream->cifdev->chip_id == CHIP_RV1106_CIF) {
wr_type_offset = 17;
yuvout_offset = 9;
}
switch (fmt->fourcc) {
case V4L2_PIX_FMT_NV16:
mask = (CSI_WRDDR_TYPE_YUV422SP_RK3588 << wr_type_offset) |
(CSI_YUV_OUTPUT_ORDER_UYVY << yuvout_offset);
break;
case V4L2_PIX_FMT_NV61:
mask = (CSI_WRDDR_TYPE_YUV422SP_RK3588 << wr_type_offset) |
(CSI_YUV_OUTPUT_ORDER_VYUY << yuvout_offset);
break;
case V4L2_PIX_FMT_NV12:
mask = (CSI_WRDDR_TYPE_YUV420SP_RK3588 << wr_type_offset) |
(CSI_YUV_OUTPUT_ORDER_UYVY << yuvout_offset);
break;
case V4L2_PIX_FMT_NV21:
mask = (CSI_WRDDR_TYPE_YUV420SP_RK3588 << wr_type_offset) |
(CSI_YUV_OUTPUT_ORDER_VYUY << yuvout_offset);
break;
case V4L2_PIX_FMT_YUYV:
mask = (CSI_WRDDR_TYPE_YUV_PACKET << wr_type_offset) |
(CSI_YUV_OUTPUT_ORDER_YUYV << yuvout_offset);
break;
case V4L2_PIX_FMT_YVYU:
mask = (CSI_WRDDR_TYPE_YUV_PACKET << wr_type_offset) |
(CSI_YUV_OUTPUT_ORDER_YVYU << yuvout_offset);
break;
case V4L2_PIX_FMT_UYVY:
mask = (CSI_WRDDR_TYPE_YUV_PACKET << wr_type_offset) |
(CSI_YUV_OUTPUT_ORDER_UYVY << yuvout_offset);
break;
case V4L2_PIX_FMT_VYUY:
mask = (CSI_WRDDR_TYPE_YUV_PACKET << wr_type_offset) |
(CSI_YUV_OUTPUT_ORDER_VYUY << yuvout_offset);
break;
case V4L2_PIX_FMT_RGB24:
case V4L2_PIX_FMT_RGB565:
case V4L2_PIX_FMT_BGR666:
mask = CSI_WRDDR_TYPE_RAW_COMPACT << wr_type_offset;
break;
case V4L2_PIX_FMT_SRGGB8:
case V4L2_PIX_FMT_SGRBG8:
case V4L2_PIX_FMT_SGBRG8:
case V4L2_PIX_FMT_SBGGR8:
case V4L2_PIX_FMT_SRGGB10:
case V4L2_PIX_FMT_SGRBG10:
case V4L2_PIX_FMT_SGBRG10:
case V4L2_PIX_FMT_SBGGR10:
case V4L2_PIX_FMT_SRGGB12:
case V4L2_PIX_FMT_SGRBG12:
case V4L2_PIX_FMT_SGBRG12:
case V4L2_PIX_FMT_SBGGR12:
case V4L2_PIX_FMT_GREY:
case V4L2_PIX_FMT_Y10:
case V4L2_PIX_FMT_Y12:
if (stream->is_compact)
mask = CSI_WRDDR_TYPE_RAW_COMPACT << wr_type_offset;
else
mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT << wr_type_offset;
break;
case V4L2_PIX_FMT_SBGGR16:
case V4L2_PIX_FMT_SGBRG16:
case V4L2_PIX_FMT_SGRBG16:
case V4L2_PIX_FMT_SRGGB16:
case V4L2_PIX_FMT_Y16:
mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT << wr_type_offset;
break;
default:
mask = CSI_WRDDR_TYPE_RAW_COMPACT << wr_type_offset;
break;
}
return mask;
}
/*config reg for rk3588*/
static int rkcif_csi_channel_set_v1(struct rkcif_stream *stream,
struct csi_channel_info *channel,
@@ -2344,6 +2453,11 @@ static int rkcif_csi_channel_set_v1(struct rkcif_stream *stream,
CIF_MIPI_LVDS_SW_HURRY_ENABLE |
CIF_MIPI_LVDS_SW_WATER_LINE_25 |
CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE;
if (mbus_type == V4L2_MBUS_CSI2_DPHY ||
mbus_type == V4L2_MBUS_CSI2_CPHY)
val &= ~CIF_MIPI_LVDS_SW_SEL_LVDS_RV1106;
else
val |= CIF_MIPI_LVDS_SW_SEL_LVDS_RV1106;
rkcif_write_register(dev, CIF_REG_MIPI_LVDS_CTRL, val);
rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
@@ -2358,8 +2472,13 @@ static int rkcif_csi_channel_set_v1(struct rkcif_stream *stream,
if (channel->crop_en)
rkcif_write_register(dev, get_reg_index_of_id_crop_start(channel->id),
channel->crop_st_y << 16 | channel->crop_st_x);
if (stream->dma_en)
dma_en = CSI_DMA_ENABLE;
if (stream->dma_en) {
if (mbus_type == V4L2_MBUS_CSI2_DPHY ||
mbus_type == V4L2_MBUS_CSI2_CPHY)
dma_en = CSI_DMA_ENABLE;
else
dma_en = LVDS_DMAEN_RV1106;
}
if (stream->dma_en & RKCIF_DMAEN_BY_VICAP)
rkcif_assign_new_buffer_pingpong(stream,
RKCIF_YUV_ADDR_STATE_INIT,
@@ -2368,8 +2487,8 @@ static int rkcif_csi_channel_set_v1(struct rkcif_stream *stream,
rkcif_assign_new_buffer_pingpong_toisp(stream,
RKCIF_YUV_ADDR_STATE_INIT,
channel->id);
if (mbus_type == V4L2_MBUS_CSI2_DPHY ||
mbus_type == V4L2_MBUS_CSI2_CPHY) {
if (mbus_type == V4L2_MBUS_CSI2_DPHY ||
mbus_type == V4L2_MBUS_CSI2_CPHY) {
if (stream->cifdev->hdr.esp.mode == HDR_LINE_CNT ||
stream->cifdev->hdr.esp.mode == HDR_ID_CODE)
@@ -2401,22 +2520,23 @@ static int rkcif_csi_channel_set_v1(struct rkcif_stream *stream,
val |= CSI_HIGH_ALIGN_RK3588;
else
val &= ~CSI_HIGH_ALIGN_RK3588;
} else if (mbus_type == V4L2_MBUS_CCP2) {
//not used
rkcif_write_register(dev, get_reg_index_of_id_ctrl0(channel->id), val);
rkcif_write_register(dev, CIF_REG_MIPI_EFFECT_CODE_ID0, 0x02410251);
rkcif_write_register(dev, CIF_REG_MIPI_EFFECT_CODE_ID1, 0x02420252);
} else if (mbus_type == V4L2_MBUS_CCP2) {
rkcif_csi_set_lvds_sav_eav(stream, channel);
val = LVDS_ENABLE_CAPTURE | LVDS_MODE(channel->lvds_cfg.mode) |
LVDS_MAIN_LANE(0) | LVDS_FID(0) |
LVDS_LANES_ENABLED(dev->active_sensor->lanes);
if (stream->is_compact)
val |= LVDS_COMPACT;
else
val &= ~LVDS_COMPACT;
val = LVDS_ENABLE_CAPTURE_RV1106 | LVDS_MODE_RV1106(channel->lvds_cfg.mode) |
LVDS_MAIN_LANE_RV1106(0) | LVDS_FID_RV1106(0) |
LVDS_LANES_ENABLED_RV1106(dev->active_sensor->lanes) |
(channel->csi_fmt_val << 18) |
rkcif_lvds_get_output_type_mask(stream) |
(stream->cif_fmt_in->csi_yuv_order << 9) |
dma_en;
if (stream->cifdev->hdr.hdr_mode == HDR_X3)
val |= BIT(12);
rkcif_write_register(dev, get_reg_index_of_lvds_id_ctrl0(channel->id), val);
}
rkcif_write_register(dev, get_reg_index_of_id_ctrl0(channel->id), val);
rkcif_write_register(dev, CIF_REG_MIPI_EFFECT_CODE_ID0, 0x02410251);
rkcif_write_register(dev, CIF_REG_MIPI_EFFECT_CODE_ID1, 0x02420252);
stream->cifdev->id_use_cnt++;
return 0;
}
@@ -2869,7 +2989,7 @@ static int rkcif_create_dummy_buf(struct rkcif_stream *stream)
* and the width is double Because the real input fmt is
* yuyv
*/
fourcc = stream->cif_fmt_out->fourcc;
fourcc = stream->cif_fmt_out->fourcc;
if (fourcc == V4L2_PIX_FMT_YUYV || fourcc == V4L2_PIX_FMT_YVYU ||
fourcc == V4L2_PIX_FMT_UYVY || fourcc == V4L2_PIX_FMT_VYUY)
dummy_buf->size *= 2;
@@ -3681,10 +3801,8 @@ static int rkcif_stream_start(struct rkcif_stream *stream, unsigned int mode)
sensor_info = dev->active_sensor;
mbus = &sensor_info->mbus;
if ((mode & RKCIF_STREAM_MODE_CAPTURE) == RKCIF_STREAM_MODE_CAPTURE) {
dma_en = DVP_DMA_EN;
if ((mode & RKCIF_STREAM_MODE_CAPTURE) == RKCIF_STREAM_MODE_CAPTURE)
stream->dma_en = RKCIF_DMAEN_BY_VICAP;
}
if (sensor_info->sd && mbus->type == V4L2_MBUS_BT656) {
int ret;
@@ -3863,7 +3981,7 @@ static int rkcif_stream_start(struct rkcif_stream *stream, unsigned int mode)
rkcif_write_register_or(dev, CIF_REG_DVP_INTEN, 0x033ffff);//0x3c3ffff
}
if (dma_en) {
if (stream->dma_en) {
if (dev->chip_id < CHIP_RK1808_CIF)
rkcif_assign_new_buffer_oneframe(stream,
RKCIF_YUV_ADDR_STATE_INIT);
@@ -3892,10 +4010,8 @@ static int rkcif_stream_start(struct rkcif_stream *stream, unsigned int mode)
dev->workmode = RKCIF_WORKMODE_PINGPONG;
}
if (dev->chip_id < CHIP_RK3588_CIF)
rkcif_write_register(dev, CIF_REG_DVP_CTRL,
AXI_BURST_16 | workmode | ENABLE_CAPTURE);
else
if (dev->chip_id == CHIP_RK3588_CIF) {
dma_en = DVP_DMA_EN;
rkcif_write_register(dev, CIF_REG_DVP_CTRL,
DVP_SW_WATER_LINE_25
| dma_en
@@ -3905,6 +4021,22 @@ static int rkcif_stream_start(struct rkcif_stream *stream, unsigned int mode)
| DVP_SW_PRESS_VALUE(3)
| DVP_SW_HURRY_VALUE(3)
| ENABLE_CAPTURE);
} else if (dev->chip_id == CHIP_RV1106_CIF) {
dma_en = DVP_SW_DMA_EN(stream->id);
rkcif_write_register(dev, CIF_REG_DVP_CTRL,
DVP_SW_WATER_LINE_25
| DVP_PRESS_EN
| DVP_HURRY_EN
| DVP_SW_WATER_LINE_25
| DVP_SW_PRESS_VALUE(3)
| DVP_SW_HURRY_VALUE(3)
| DVP_SW_CAP_EN(stream->id)
| dma_en
| ENABLE_CAPTURE);
} else {
rkcif_write_register(dev, CIF_REG_DVP_CTRL,
AXI_BURST_16 | workmode | ENABLE_CAPTURE);
}
atomic_set(&sof_sd->frm_sync_seq, 0);
stream->state = RKCIF_STATE_STREAMING;
@@ -4480,11 +4612,7 @@ static int rkcif_fh_open(struct file *filp)
* Because CRU would reset iommu too, so there's not chance
* to reset cif once we hold buffers after buf queued
*/
if (cifdev->chip_id == CHIP_RK1808_CIF ||
cifdev->chip_id == CHIP_RV1126_CIF ||
cifdev->chip_id == CHIP_RV1126_CIF_LITE ||
cifdev->chip_id == CHIP_RK3568_CIF ||
cifdev->chip_id == CHIP_RK3588_CIF) {
if (cifdev->chip_id >= CHIP_RK1808_CIF) {
mutex_lock(&cifdev->stream_lock);
if (!atomic_read(&cifdev->fh_cnt))
rkcif_soft_reset(cifdev, true);
@@ -7055,29 +7183,47 @@ void rkcif_enable_dma_capture(struct rkcif_stream *stream)
}
stream->dma_en |= stream->to_en_dma;
val = rkcif_read_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id));
if (stream->to_en_dma == RKCIF_DMAEN_BY_VICAP) {
rkcif_assign_new_buffer_pingpong(stream,
RKCIF_YUV_ADDR_STATE_INIT,
stream->id);
rkcif_write_register(cif_dev, get_reg_index_of_frm0_y_vlw(stream->id),
channel->virtual_width);
if (!stream->is_compact)
val |= CSI_WRDDR_TYPE_RAW_UNCOMPACT;
else
val &= ~CSI_WRDDR_TYPE_RAW_UNCOMPACT;
} else if (stream->to_en_dma == RKCIF_DMAEN_BY_ISP) {
rkcif_assign_new_buffer_pingpong_toisp(stream,
RKCIF_YUV_ADDR_STATE_INIT,
stream->id);
}
if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
mbus_cfg->type == V4L2_MBUS_CCP2) {
if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
mbus_cfg->type == V4L2_MBUS_CSI2_CPHY)
val |= CSI_DMA_ENABLE;
mbus_cfg->type == V4L2_MBUS_CSI2_CPHY) {
val = rkcif_read_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id));
if (!stream->is_compact)
val |= CSI_WRDDR_TYPE_RAW_UNCOMPACT;
else
val &= ~CSI_WRDDR_TYPE_RAW_UNCOMPACT;
val |= CSI_DMA_ENABLE;
rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id), val);
} else if (mbus_cfg->type == V4L2_MBUS_CCP2) {
val = rkcif_read_register(cif_dev, get_reg_index_of_lvds_id_ctrl0(stream->id));
if (!stream->is_compact)
val |= CSI_WRDDR_TYPE_RAW_UNCOMPACT << 17;
else
val &= ~(CSI_WRDDR_TYPE_RAW_UNCOMPACT << 17);
val |= LVDS_DMAEN_RV1106;
rkcif_write_register(cif_dev, get_reg_index_of_lvds_id_ctrl0(stream->id), val);
} else {
val = rkcif_read_register(cif_dev, CIF_REG_DVP_FOR);
if (!stream->is_compact)
val |= CSI_WRDDR_TYPE_RAW_UNCOMPACT << 11;
else
val &= ~(CSI_WRDDR_TYPE_RAW_UNCOMPACT << 11);
rkcif_write_register(cif_dev, CIF_REG_DVP_FOR, val);
val = rkcif_read_register(cif_dev, CIF_REG_DVP_CTRL);
if (cif_dev->chip_id == CHIP_RK3588_CIF)
val |= DVP_DMA_EN;
else if (cif_dev->chip_id == CHIP_RV1106_CIF)
val |= DVP_SW_DMA_EN(stream->id);
rkcif_write_register(cif_dev, CIF_REG_DVP_CTRL, val);
}
stream->to_en_dma = 0;
@@ -7096,14 +7242,21 @@ static void rkcif_stop_dma_capture(struct rkcif_stream *stream)
}
if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
mbus_cfg->type == V4L2_MBUS_CCP2) {
mbus_cfg->type == V4L2_MBUS_CSI2_CPHY) {
val = rkcif_read_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id));
if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
mbus_cfg->type == V4L2_MBUS_CSI2_CPHY)
val &= ~CSI_DMA_ENABLE;
val &= ~CSI_DMA_ENABLE;
rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id), val);
} else if (mbus_cfg->type == V4L2_MBUS_CCP2) {
val = rkcif_read_register(cif_dev, get_reg_index_of_lvds_id_ctrl0(stream->id));
val &= ~LVDS_DMAEN_RV1106;
rkcif_write_register(cif_dev, get_reg_index_of_lvds_id_ctrl0(stream->id), val);
} else {
val = rkcif_read_register(cif_dev, CIF_REG_DVP_CTRL);
if (cif_dev->chip_id == CHIP_RK3588_CIF)
val &= ~DVP_DMA_EN;
else if (cif_dev->chip_id == CHIP_RV1106_CIF)
val &= ~(DVP_SW_DMA_EN(stream->id));
rkcif_write_register(cif_dev, CIF_REG_DVP_CTRL, val);
}
stream->to_stop_dma = 0;
}

48
drivers/media/platform/rockchip/cif/dev.c
View File

@@ -541,10 +541,13 @@ void rkcif_write_register(struct rkcif_device *dev,
int csi_offset = 0;
if (dev->inf_id == RKCIF_MIPI_LVDS &&
dev->chip_id == CHIP_RK3588_CIF &&
index >= CIF_REG_MIPI_LVDS_ID0_CTRL0 &&
index <= CIF_REG_MIPI_ON_PAD)
csi_offset = dev->csi_host_idx * 0x100;
index <= CIF_REG_MIPI_ON_PAD) {
if (dev->chip_id == CHIP_RK3588_CIF)
csi_offset = dev->csi_host_idx * 0x100;
else if (dev->chip_id == CHIP_RV1106_CIF)
csi_offset = dev->csi_host_idx * 0x200;
}
if (index < CIF_REG_INDEX_MAX) {
if (index == CIF_REG_DVP_CTRL ||
(index != CIF_REG_DVP_CTRL && reg->offset != 0x0))
@@ -565,10 +568,13 @@ void rkcif_write_register_or(struct rkcif_device *dev,
int csi_offset = 0;
if (dev->inf_id == RKCIF_MIPI_LVDS &&
dev->chip_id == CHIP_RK3588_CIF &&
index >= CIF_REG_MIPI_LVDS_ID0_CTRL0 &&
index <= CIF_REG_MIPI_ON_PAD)
csi_offset = dev->csi_host_idx * 0x100;
index <= CIF_REG_MIPI_ON_PAD) {
if (dev->chip_id == CHIP_RK3588_CIF)
csi_offset = dev->csi_host_idx * 0x100;
else if (dev->chip_id == CHIP_RV1106_CIF)
csi_offset = dev->csi_host_idx * 0x200;
}
if (index < CIF_REG_INDEX_MAX) {
if (index == CIF_REG_DVP_CTRL ||
@@ -593,10 +599,13 @@ void rkcif_write_register_and(struct rkcif_device *dev,
int csi_offset = 0;
if (dev->inf_id == RKCIF_MIPI_LVDS &&
dev->chip_id == CHIP_RK3588_CIF &&
index >= CIF_REG_MIPI_LVDS_ID0_CTRL0 &&
index <= CIF_REG_MIPI_ON_PAD)
csi_offset = dev->csi_host_idx * 0x100;
index <= CIF_REG_MIPI_ON_PAD) {
if (dev->chip_id == CHIP_RK3588_CIF)
csi_offset = dev->csi_host_idx * 0x100;
else if (dev->chip_id == CHIP_RV1106_CIF)
csi_offset = dev->csi_host_idx * 0x200;
}
if (index < CIF_REG_INDEX_MAX) {
if (index == CIF_REG_DVP_CTRL ||
@@ -621,10 +630,13 @@ unsigned int rkcif_read_register(struct rkcif_device *dev,
int csi_offset = 0;
if (dev->inf_id == RKCIF_MIPI_LVDS &&
dev->chip_id == CHIP_RK3588_CIF &&
index >= CIF_REG_MIPI_LVDS_ID0_CTRL0 &&
index <= CIF_REG_MIPI_ON_PAD)
csi_offset = dev->csi_host_idx * 0x100;
index <= CIF_REG_MIPI_ON_PAD) {
if (dev->chip_id == CHIP_RK3588_CIF)
csi_offset = dev->csi_host_idx * 0x100;
else if (dev->chip_id == CHIP_RV1106_CIF)
csi_offset = dev->csi_host_idx * 0x200;
}
if (index < CIF_REG_INDEX_MAX) {
if (index == CIF_REG_DVP_CTRL ||
@@ -1083,7 +1095,8 @@ static int rkcif_create_link(struct rkcif_device *dev,
break;
}
}
if (dev->chip_id == CHIP_RK3588_CIF) {
if (dev->chip_id == CHIP_RK3588_CIF ||
dev->chip_id == CHIP_RV1106_CIF) {
for (id = 0; id < stream_num; id++) {
source_entity = &linked_sensor.sd->entity;
sink_entity = &dev->scale_vdev[id].vnode.vdev.entity;
@@ -1392,7 +1405,8 @@ static int rkcif_register_platform_subdevs(struct rkcif_device *cif_dev)
return -EINVAL;
}
if (cif_dev->chip_id == CHIP_RK3588_CIF) {
if (cif_dev->chip_id == CHIP_RK3588_CIF ||
cif_dev->chip_id == CHIP_RV1106_CIF) {
ret = rkcif_register_scale_vdevs(cif_dev, RKCIF_MAX_SCALE_CH, true);
if (ret < 0) {
@@ -1410,7 +1424,8 @@ static int rkcif_register_platform_subdevs(struct rkcif_device *cif_dev)
return 0;
err_unreg_stream_vdev:
rkcif_unregister_stream_vdevs(cif_dev, stream_num);
if (cif_dev->chip_id == CHIP_RK3588_CIF)
if (cif_dev->chip_id == CHIP_RK3588_CIF ||
cif_dev->chip_id == CHIP_RV1106_CIF)
rkcif_unregister_scale_vdevs(cif_dev, RKCIF_MAX_SCALE_CH);
return ret;
@@ -1650,7 +1665,8 @@ int rkcif_plat_init(struct rkcif_device *cif_dev, struct device_node *node, int
rkcif_stream_init(cif_dev, RKCIF_STREAM_MIPI_ID3);
}
if (cif_dev->chip_id == CHIP_RK3588_CIF) {
if (cif_dev->chip_id == CHIP_RK3588_CIF ||
cif_dev->chip_id == CHIP_RV1106_CIF) {
rkcif_init_scale_vdev(cif_dev, RKCIF_SCALE_CH0);
rkcif_init_scale_vdev(cif_dev, RKCIF_SCALE_CH1);
rkcif_init_scale_vdev(cif_dev, RKCIF_SCALE_CH2);

153
drivers/media/platform/rockchip/cif/hw.c
View File

@@ -723,6 +723,142 @@ static const struct cif_reg rk3588_cif_regs[] = {
[CIF_REG_GRF_CIFIO_CON] = CIF_REG(CIF_GRF_SOC_CON2),
};
static const char * const rv1106_cif_clks[] = {
"aclk_cif",
"hclk_cif",
"dclk_cif",
"pclk_cif",
"i0clk_cif",
"i1clk_cif",
"rx0clk_cif",
"rx1clk_cif",
"isp0clk_cif",
};
static const char * const rv1106_cif_rsts[] = {
"rst_cif_a",
"rst_cif_h",
"rst_cif_d",
"rst_cif_p",
"rst_cif_i0",
"rst_cif_i1",
"rst_cif_rx0",
"rst_cif_rx1",
"rst_cif_isp0",
};
static const struct cif_reg rv1106_cif_regs[] = {
[CIF_REG_DVP_CTRL] = CIF_REG(DVP_CTRL),
[CIF_REG_DVP_INTEN] = CIF_REG(DVP_INTEN),
[CIF_REG_DVP_INTSTAT] = CIF_REG(DVP_INTSTAT),
[CIF_REG_DVP_FOR] = CIF_REG(DVP_FOR),
[CIF_REG_DVP_SAV_EAV] = CIF_REG(DVP_SAV_EAV),
[CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(DVP_FRM0_ADDR_Y_ID0),
[CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(DVP_FRM0_ADDR_UV_ID0),
[CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(DVP_FRM1_ADDR_Y_ID0),
[CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(DVP_FRM1_ADDR_UV_ID0),
[CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(DVP_VIR_LINE_WIDTH),
[CIF_REG_DVP_SET_SIZE] = CIF_REG(DVP_CROP_SIZE),
[CIF_REG_DVP_CROP] = CIF_REG(DVP_CROP),
[CIF_REG_DVP_LINE_INT_NUM] = CIF_REG(DVP_LINE_INT_NUM_01),
[CIF_REG_DVP_LINE_CNT] = CIF_REG(DVP_LINE_CNT_01),
[CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CSI_MIPI0_ID0_CTRL0),
[CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CSI_MIPI0_ID0_CTRL1),
[CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CSI_MIPI0_ID1_CTRL0),
[CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CSI_MIPI0_ID1_CTRL1),
[CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CSI_MIPI0_ID2_CTRL0),
[CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CSI_MIPI0_ID2_CTRL1),
[CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CSI_MIPI0_ID3_CTRL0),
[CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CSI_MIPI0_ID3_CTRL1),
[CIF_REG_MIPI_LVDS_CTRL] = CIF_REG(CSI_MIPI0_CTRL),
[CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID0),
[CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID0),
[CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID0),
[CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID0),
[CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CSI_MIPI0_VLW_ID0),
[CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID1),
[CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID1),
[CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID1),
[CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID1),
[CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CSI_MIPI0_VLW_ID1),
[CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID2),
[CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID2),
[CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID2),
[CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID2),
[CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CSI_MIPI0_VLW_ID2),
[CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID3),
[CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID3),
[CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID3),
[CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID3),
[CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CSI_MIPI0_VLW_ID3),
[CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CSI_MIPI0_INTEN),
[CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CSI_MIPI0_INTSTAT),
[CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID0_1),
[CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID2_3),
[CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CSI_MIPI0_LINE_CNT_ID0_1),
[CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CSI_MIPI0_LINE_CNT_ID2_3),
[CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CSI_MIPI0_ID0_CROP_START),
[CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CSI_MIPI0_ID1_CROP_START),
[CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CSI_MIPI0_ID2_CROP_START),
[CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CSI_MIPI0_ID3_CROP_START),
[CIF_REG_MIPI_FRAME_NUM_VC0] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC0),
[CIF_REG_MIPI_FRAME_NUM_VC1] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC1),
[CIF_REG_MIPI_FRAME_NUM_VC2] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC2),
[CIF_REG_MIPI_FRAME_NUM_VC3] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC3),
[CIF_REG_MIPI_EFFECT_CODE_ID0] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID0),
[CIF_REG_MIPI_EFFECT_CODE_ID1] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID1),
[CIF_REG_MIPI_EFFECT_CODE_ID2] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID2),
[CIF_REG_MIPI_EFFECT_CODE_ID3] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID3),
[CIF_REG_MIPI_ON_PAD] = CIF_REG(CSI_MIPI0_ON_PAD),
[CIF_REG_LVDS_ID0_CTRL0] = CIF_REG(CIF_LVDS0_ID0_CTRL0),
[CIF_REG_LVDS_ID1_CTRL0] = CIF_REG(CIF_LVDS0_ID1_CTRL0),
[CIF_REG_LVDS_ID2_CTRL0] = CIF_REG(CIF_LVDS0_ID2_CTRL0),
[CIF_REG_LVDS_ID3_CTRL0] = CIF_REG(CIF_LVDS0_ID3_CTRL0),
[CIF_REG_LVDS_SAV_EAV_ACT0_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID0_RV1106),
[CIF_REG_LVDS_SAV_EAV_BLK0_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID0_RV1106),
[CIF_REG_LVDS_SAV_EAV_ACT1_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID0_RV1106),
[CIF_REG_LVDS_SAV_EAV_BLK1_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID0_RV1106),
[CIF_REG_LVDS_SAV_EAV_ACT0_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID1_RV1106),
[CIF_REG_LVDS_SAV_EAV_BLK0_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID1_RV1106),
[CIF_REG_LVDS_SAV_EAV_ACT1_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID1_RV1106),
[CIF_REG_LVDS_SAV_EAV_BLK1_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID1_RV1106),
[CIF_REG_LVDS_SAV_EAV_ACT0_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID2_RV1106),
[CIF_REG_LVDS_SAV_EAV_BLK0_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID2_RV1106),
[CIF_REG_LVDS_SAV_EAV_ACT1_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID2_RV1106),
[CIF_REG_LVDS_SAV_EAV_BLK1_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID2_RV1106),
[CIF_REG_LVDS_SAV_EAV_ACT0_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID3_RV1106),
[CIF_REG_LVDS_SAV_EAV_BLK0_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID3_RV1106),
[CIF_REG_LVDS_SAV_EAV_ACT1_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID3_RV1106),
[CIF_REG_LVDS_SAV_EAV_BLK1_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID3_RV1106),
[CIF_REG_GLB_CTRL] = CIF_REG(GLB_CTRL),
[CIF_REG_GLB_INTEN] = CIF_REG(GLB_INTEN),
[CIF_REG_GLB_INTST] = CIF_REG(GLB_INTST),
[CIF_REG_SCL_CH_CTRL] = CIF_REG(SCL_CH_CTRL),
[CIF_REG_SCL_CTRL] = CIF_REG(SCL_CTRL),
[CIF_REG_SCL_FRM0_ADDR_CH0] = CIF_REG(SCL_FRM0_ADDR_CH0),
[CIF_REG_SCL_FRM1_ADDR_CH0] = CIF_REG(SCL_FRM1_ADDR_CH0),
[CIF_REG_SCL_VLW_CH0] = CIF_REG(SCL_VLW_CH0),
[CIF_REG_SCL_FRM0_ADDR_CH1] = CIF_REG(SCL_FRM0_ADDR_CH1),
[CIF_REG_SCL_FRM1_ADDR_CH1] = CIF_REG(SCL_FRM1_ADDR_CH1),
[CIF_REG_SCL_VLW_CH1] = CIF_REG(SCL_VLW_CH1),
[CIF_REG_SCL_FRM0_ADDR_CH2] = CIF_REG(SCL_FRM0_ADDR_CH2),
[CIF_REG_SCL_FRM1_ADDR_CH2] = CIF_REG(SCL_FRM1_ADDR_CH2),
[CIF_REG_SCL_VLW_CH2] = CIF_REG(SCL_VLW_CH2),
[CIF_REG_SCL_FRM0_ADDR_CH3] = CIF_REG(SCL_FRM0_ADDR_CH3),
[CIF_REG_SCL_FRM1_ADDR_CH3] = CIF_REG(SCL_FRM1_ADDR_CH3),
[CIF_REG_SCL_VLW_CH3] = CIF_REG(SCL_VLW_CH3),
[CIF_REG_SCL_BLC_CH0] = CIF_REG(SCL_BLC_CH0),
[CIF_REG_SCL_BLC_CH1] = CIF_REG(SCL_BLC_CH1),
[CIF_REG_SCL_BLC_CH2] = CIF_REG(SCL_BLC_CH2),
[CIF_REG_SCL_BLC_CH3] = CIF_REG(SCL_BLC_CH3),
[CIF_REG_TOISP0_CTRL] = CIF_REG(TOISP0_CH_CTRL),
[CIF_REG_TOISP0_SIZE] = CIF_REG(TOISP0_CROP_SIZE),
[CIF_REG_TOISP0_CROP] = CIF_REG(TOISP0_CROP),
};
static const struct rkcif_hw_match_data px30_cif_match_data = {
.chip_id = CHIP_PX30_CIF,
.clks = px30_cif_clks,
@@ -813,6 +949,15 @@ static const struct rkcif_hw_match_data rk3588_cif_match_data = {
.cif_regs = rk3588_cif_regs,
};
static const struct rkcif_hw_match_data rv1106_cif_match_data = {
.chip_id = CHIP_RV1106_CIF,
.clks = rv1106_cif_clks,
.clks_num = ARRAY_SIZE(rv1106_cif_clks),
.rsts = rv1106_cif_rsts,
.rsts_num = ARRAY_SIZE(rv1106_cif_rsts),
.cif_regs = rv1106_cif_regs,
};
static const struct of_device_id rkcif_plat_of_match[] = {
{
.compatible = "rockchip,px30-cif",
@@ -854,6 +999,10 @@ static const struct of_device_id rkcif_plat_of_match[] = {
.compatible = "rockchip,rv1126-cif-lite",
.data = &rv1126_cif_lite_match_data,
},
{
.compatible = "rockchip,rv1106-cif",
.data = &rv1106_cif_match_data,
},
{},
};
@@ -864,12 +1013,12 @@ static irqreturn_t rkcif_irq_handler(int irq, void *ctx)
unsigned int intstat_glb = 0;
int i;
if (cif_hw->chip_id == CHIP_RK3588_CIF)
if (cif_hw->chip_id >= CHIP_RK3588_CIF)
intstat_glb = rkcif_irq_global(cif_hw->cif_dev[0]);
for (i = 0; i < cif_hw->dev_num; i++) {
if (cif_hw->cif_dev[i]->isr_hdl) {
cif_hw->cif_dev[i]->isr_hdl(irq, cif_hw->cif_dev[i]);
if (cif_hw->chip_id == CHIP_RK3588_CIF && intstat_glb)
if (cif_hw->chip_id >= CHIP_RK3588_CIF && intstat_glb)
rkcif_irq_handle_toisp(cif_hw->cif_dev[i], intstat_glb);
}
}

1
drivers/media/platform/rockchip/cif/hw.h
View File

@@ -80,6 +80,7 @@ enum rkcif_chip_id {
CHIP_RV1126_CIF_LITE,
CHIP_RK3568_CIF,
CHIP_RK3588_CIF,
CHIP_RV1106_CIF,
};
struct rkcif_hw_match_data {

60
drivers/media/platform/rockchip/cif/regs.h
View File

@@ -141,6 +141,10 @@ enum cif_reg_index {
CIF_REG_MIPI_EFFECT_CODE_ID1,
CIF_REG_MIPI_EFFECT_CODE_ID2,
CIF_REG_MIPI_EFFECT_CODE_ID3,
CIF_REG_LVDS_ID0_CTRL0,
CIF_REG_LVDS_ID1_CTRL0,
CIF_REG_LVDS_ID2_CTRL0,
CIF_REG_LVDS_ID3_CTRL0,
CIF_REG_MIPI_ON_PAD,
CIF_REG_Y_STAT_CONTROL,
@@ -416,6 +420,28 @@ enum cif_reg_index {
#define CSI_MIPI0_EFFECT_CODE_ID3 0x1B8
#define CSI_MIPI0_ON_PAD 0x1BC
/* RV1106 CONTROL Registers Offset */
#define CIF_LVDS0_ID0_CTRL0 0x1D0
#define CIF_LVDS0_ID1_CTRL0 0x1D4
#define CIF_LVDS0_ID2_CTRL0 0x1D8
#define CIF_LVDS0_ID3_CTRL0 0x1DC
#define CIF_LVDS_SAV_EAV_ACT0_ID0_RV1106 0x1E0
#define CIF_LVDS_SAV_EAV_BLK0_ID0_RV1106 0x1E4
#define CIF_LVDS_SAV_EAV_ACT1_ID0_RV1106 0x1E8
#define CIF_LVDS_SAV_EAV_BLK1_ID0_RV1106 0x1EC
#define CIF_LVDS_SAV_EAV_ACT0_ID1_RV1106 0x1F0
#define CIF_LVDS_SAV_EAV_BLK0_ID1_RV1106 0x1F4
#define CIF_LVDS_SAV_EAV_ACT1_ID1_RV1106 0x1F8
#define CIF_LVDS_SAV_EAV_BLK1_ID1_RV1106 0x1FC
#define CIF_LVDS_SAV_EAV_ACT0_ID2_RV1106 0x200
#define CIF_LVDS_SAV_EAV_BLK0_ID2_RV1106 0x204
#define CIF_LVDS_SAV_EAV_ACT1_ID2_RV1106 0x208
#define CIF_LVDS_SAV_EAV_BLK1_ID2_RV1106 0x20C
#define CIF_LVDS_SAV_EAV_ACT0_ID3_RV1106 0x210
#define CIF_LVDS_SAV_EAV_BLK0_ID3_RV1106 0x214
#define CIF_LVDS_SAV_EAV_ACT1_ID3_RV1106 0x218
#define CIF_LVDS_SAV_EAV_BLK1_ID3_RV1106 0x21C
/* RK3588 CONTROL Registers Offset */
#define GLB_CTRL 0X000
#define GLB_INTEN 0X004
@@ -510,6 +536,8 @@ enum cif_reg_index {
#define DVP_SW_PRESS_VALUE(val) (((val) & 0x7) << 13)
#define DVP_SW_HURRY_VALUE(val) (((val) & 0x7) << 9)
#define DVP_SW_CAP_EN(ID) (2 << ID)
#define DVP_SW_DMA_EN(ID) (0x100000 << ID)
#define DVP_DMA_END_INTEN(id) \
({ \
@@ -801,6 +829,37 @@ enum cif_reg_index {
#define LVDS_HDR_FRAME_X3 (0x1 << 28)
#define LVDS_COMPACT (0x1 << 29)
#define LVDS_ENABLE_CAPTURE_RV1106 (0x1 << 0)
#define LVDS_MODE_RV1106(mode) (((mode) & 0x7) << 1)
#define LVDS_LANES_ENABLED_RV1106(lanes) \
({ \
unsigned int mask; \
switch (lanes) { \
case 1: \
mask = 0x1 << 4; \
break; \
case 2: \
mask = 0x3 << 4; \
break; \
case 3: \
mask = 0x7 << 4; \
break; \
case 4: \
mask = 0xf << 4; \
break; \
default: \
mask = 0x1 << 4; \
break; \
} \
mask; \
})
#define LVDS_MAIN_LANE_RV1106(index) (((index) & 0x3) << 8)
#define LVDS_FID_RV1106(id) (((id) & 0x3) << 10)
#define LVDS_HDR_FRAME_X2_RV1106 (0x0 << 12)
#define LVDS_HDR_FRAME_X3_RV1106 (0x1 << 12)
#define LVDS_DMAEN_RV1106 (0x1 << 15)
/* CIF_CSI_INTEN */
#define CSI_FRAME1_START_INTEN(id) (0x1 << ((id) * 2 + 1))
#define CSI_FRAME0_END_INTEN(id) (0x1 << ((id) * 2 + 8))
@@ -904,6 +963,7 @@ enum cif_reg_index {
#define CIF_MIPI_LVDS_SW_LVDS_WIDTH_10BITS (0x1 << 9)
#define CIF_MIPI_LVDS_SW_LVDS_WIDTH_12BITS (0x2 << 9)
#define CIF_MIPI_LVDS_SW_SEL_LVDS (0x1 << 8)
#define CIF_MIPI_LVDS_SW_SEL_LVDS_RV1106 (0x1 << 3)
#define CIF_MIPI_LVDS_SW_HURRY_VALUE(val) (((val) & 0x3) << 5)
#define CIF_MIPI_LVDS_SW_HURRY_VALUE_RK3588(val) (((val) & 0x7) << 5)
#define CIF_MIPI_LVDS_SW_HURRY_ENABLE (0x1 << 4)