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arm64: dts: rockchip: rk3576 evb1 add tp2815 ahd2csi config

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Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: Ifd714fc4aba9842b0301910d8c183e4ab66619de
This commit is contained in:
Wang Panzhenzhuan
2024-01-30 02:54:53 +00:00
committed by Tao Huang
parent e63c8a3e23
commit af52d997f6
2 changed files with 226 additions and 0 deletions
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1
arch/arm64/boot/dts/rockchip/Makefile
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@@ -236,6 +236,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-super-frame-dsi0-co
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2lvds0-lp4x-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-tp2815-ahd2csi.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-test1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-test1-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-test2-v10.dtb

225
arch/arm64/boot/dts/rockchip/rk3576-evb1-v10-tp2815-ahd2csi.dts Normal file
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@@ -0,0 +1,225 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include "rk3576-evb1.dtsi"
#include "rk3576-android.dtsi"
/ {
model = "Rockchip RK3576 EVB1 V10 Board + Rockchip TP2815 AHD to MIPI Extboard";
compatible = "rockchip,rk3576-evb1-v10", "rockchip,rk3576";
};
&csi2_dphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_dphy0_in_tp2815: endpoint@1 {
reg = <1>;
remote-endpoint = <&tp2815_out0>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi1_csi2_input>;
};
};
};
};
&csi2_dphy3 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_dphy3_in_tp2815: endpoint@1 {
reg = <1>;
remote-endpoint = <&tp2815_out1>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy3_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi3_csi2_input>;
};
};
};
};
&csi2_dphy0_hw {
status = "okay";
};
&csi2_dphy1_hw {
status = "okay";
};
&i2c5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c5m3_xfer>;
tp2815: tp2815@44 {
compatible = "techpoint,tp2815";
status = "okay";
reg = <0x44>;
clocks = <&cru CLK_MIPI_CAMERAOUT_M1>;
clock-names = "xvclk";
power-domains = <&power RK3576_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&cam_clk1m0_clk1>;
avdd-supply = <&vcc_mipicsi0>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
port {
tp2815_out0: endpoint {
remote-endpoint = <&mipi_dphy0_in_tp2815>;
data-lanes = <1 2 3 4>;
};
};
};
tp2815b: tp2815b@45 {
compatible = "techpoint,tp2815";
status = "okay";
reg = <0x45>;
clocks = <&cru CLK_MIPI_CAMERAOUT_M1>;
clock-names = "xvclk";
power-domains = <&power RK3576_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&cam_clk1m0_clk1>;
avdd-supply = <&vcc_mipicsi0>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
port {
tp2815_out1: endpoint {
remote-endpoint = <&mipi_dphy3_in_tp2815>;
data-lanes = <1 2 3 4>;
};
};
};
};
&mipi1_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi1_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy0_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi1_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in1>;
};
};
};
};
&mipi3_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi3_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy3_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi3_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in3>;
};
};
};
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds1 {
status = "okay";
port {
cif_mipi_in1: endpoint {
remote-endpoint = <&mipi1_csi2_output>;
};
};
};
&rkcif_mipi_lvds3 {
status = "okay";
port {
cif_mipi_in3: endpoint {
remote-endpoint = <&mipi3_csi2_output>;
};
};
};
&rkcif_mmu {
status = "okay";
};