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vpu: udpate vpu mem_pd control for g12b

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PD#165090: vpu: udpate vpu mem_pd control for g12b

Change-Id: I7ac907d8b00e2ef0884082c3a56afc6b66dd00d5
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
This commit is contained in:
Evoke Zhang
2018-06-04 14:10:14 +08:00
committed by Yixun Lan
parent b5a9acd89f
commit afb59c6c3b
4 changed files with 52 additions and 2 deletions
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4
drivers/amlogic/media/common/vpu/vpu.c
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@@ -1329,10 +1329,10 @@ static struct vpu_data_s vpu_data_g12a = {
.mem_pd_reg2_valid = 1,
.mem_pd_table_cnt =
sizeof(vpu_mem_pd_g12a) / sizeof(struct vpu_ctrl_s),
sizeof(vpu_mem_pd_g12b) / sizeof(struct vpu_ctrl_s),
.clk_gate_table_cnt =
sizeof(vpu_clk_gate_g12a) / sizeof(struct vpu_ctrl_s),
.mem_pd_table = vpu_mem_pd_g12a,
.mem_pd_table = vpu_mem_pd_g12b,
.clk_gate_table = vpu_clk_gate_g12a,
.power_on = vpu_power_on_txlx,

46
drivers/amlogic/media/common/vpu/vpu_ctrl.h
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@@ -280,6 +280,52 @@ static struct vpu_ctrl_s vpu_mem_pd_g12a[] = {
{VPU_MOD_MAX, VPU_REG_END, 0, 0},
};
static struct vpu_ctrl_s vpu_mem_pd_g12b[] = {
/* vpu module, reg, bit, len */
{VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0, 2},
{VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 2, 2},
{VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 4, 2},
{VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 6, 2},
{VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 8, 2},
{VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 10, 2},
{VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 12, 2},
{VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 14, 2},
{VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 16, 2},
{VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 18, 2},
{VPU_VIU_SRSCL, HHI_VPU_MEM_PD_REG0, 20, 2},
{VPU_AFBC_DEC1, HHI_VPU_MEM_PD_REG0, 22, 2},
{VPU_VIU_DI_SCALE, HHI_VPU_MEM_PD_REG0, 24, 2},
{VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 26, 2},
{VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 28, 2},
{VPU_SHARP, HHI_VPU_MEM_PD_REG0, 30, 2},
{VPU_VIU2_OSD1, HHI_VPU_MEM_PD_REG1, 0, 2},
{VPU_VIU2_OFIFO, HHI_VPU_MEM_PD_REG1, 2, 2},
{VPU_VKSTONE, HHI_VPU_MEM_PD_REG1, 4, 2},
{VPU_DOLBY_CORE3, HHI_VPU_MEM_PD_REG1, 6, 2},
{VPU_DOLBY0, HHI_VPU_MEM_PD_REG1, 8, 2},
{VPU_DOLBY1A, HHI_VPU_MEM_PD_REG1, 10, 2},
{VPU_DOLBY1B, HHI_VPU_MEM_PD_REG1, 12, 2},
{VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 14, 2},
{VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 16, 2},
{VPU_VD2_SCALE, HHI_VPU_MEM_PD_REG1, 18, 2},
{VPU_VENCP, HHI_VPU_MEM_PD_REG1, 20, 2},
{VPU_VENCL, HHI_VPU_MEM_PD_REG1, 22, 2},
{VPU_VENCI, HHI_VPU_MEM_PD_REG1, 24, 2},
{VPU_VD2_OSD2_SCALE, HHI_VPU_MEM_PD_REG1, 30, 2},
{VPU_VIU_WM, HHI_VPU_MEM_PD_REG2, 0, 2},
{VPU_VIU_OSD3, HHI_VPU_MEM_PD_REG2, 4, 2},
{VPU_VIU_OSD4, HHI_VPU_MEM_PD_REG2, 6, 2},
{VPU_MAIL_AFBCD, HHI_VPU_MEM_PD_REG2, 8, 2},
{VPU_VD1_SCALE, HHI_VPU_MEM_PD_REG2, 10, 2},
{VPU_OSD_BLD34, HHI_VPU_MEM_PD_REG2, 12, 2},
{VPU_PRIME_DOLBY_RAM, HHI_VPU_MEM_PD_REG2, 14, 2},
{VPU_VD2_OFIFO, HHI_VPU_MEM_PD_REG2, 16, 2},
{VPU_LUT3D, HHI_VPU_MEM_PD_REG2, 20, 2},
{VPU_VIU2_OSD_ROT, HHI_VPU_MEM_PD_REG2, 22, 2},
{VPU_RDMA, HHI_VPU_MEM_PD_REG2, 30, 2},
{VPU_MOD_MAX, VPU_REG_END, 0, 0},
};
/* ******************************************************* */
/* VPU clock gate table */
/* ******************************************************* */

2
drivers/amlogic/media/common/vpu/vpu_module.h
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@@ -73,6 +73,8 @@ static char *vpu_mod_table[] = {
"osd_bld34",
"prime_dolby_ram",
"vd2_ofifo",
"lut3d",
"viu2_osd_rotation",
"rdma",
"vpu_mod_max",

2
include/linux/amlogic/media/vpu/vpu.h
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@@ -73,6 +73,8 @@ enum vpu_mod_e {
VPU_OSD_BLD34, /* reg2[13:12] //G12A */
VPU_PRIME_DOLBY_RAM, /* reg2[15:14] //G12A */
VPU_VD2_OFIFO, /* reg2[17:16] //G12A */
VPU_LUT3D, /* reg2[21:20] //G12B */
VPU_VIU2_OSD_ROT, /* reg2[23:22] //G12B */
VPU_RDMA, /* reg2[31:30] //G12A */
VPU_MOD_MAX,