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mtd: spi-nor: spansion: Consider reserved bits in CFR5 register
commit3f592a869fupstream. CFR5[6] is reserved bit and must be always 1. Set it to comply with flash requirements. While fixing SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_{EN, DS} definition, stop using magic numbers and describe the missing bit fields in CFR5 register. This is useful for both readability and future possible addition of Octal STR mode support. Fixes:c3266af101("mtd: spi-nor: spansion: add support for Cypress Semper flash") Cc: stable@vger.kernel.org Reported-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Pratyush Yadav <ptyadav@amazon.de> Tested-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/linux-mtd/20230110164703.83413-1-tudor.ambarus@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Greg Kroah-Hartman
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@@ -15,8 +15,13 @@
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#define SPINOR_REG_CYPRESS_CFR3V 0x00800004
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#define SPINOR_REG_CYPRESS_CFR3V_PGSZ BIT(4) /* Page size. */
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#define SPINOR_REG_CYPRESS_CFR5V 0x00800006
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#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN 0x3
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#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS 0
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#define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6)
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#define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1)
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#define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0)
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#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN \
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(SPINOR_REG_CYPRESS_CFR5_BIT6 | SPINOR_REG_CYPRESS_CFR5_DDR | \
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SPINOR_REG_CYPRESS_CFR5_OPI)
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#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS SPINOR_REG_CYPRESS_CFR5_BIT6
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#define SPINOR_OP_CYPRESS_RD_FAST 0xee
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/**
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