shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-06 10:58:48 +09:00
Code Issues Packages Projects Releases Wiki Activity

dt-bindings: pinctrl: update uart/mmc bindings for MT7986 SoC

Browse Source 
[ Upstream commit c115e7f51e ]

Fix mmc and uart pins after uart splitting.

Some pinmux pins of the mt7986 pinctrl driver is composed of multiple
pinctrl groups, the original binding only allows one pinctrl group
per dts node, this patch sets "maxItems" for these groups and add new
examples to the binding documentation.

Fixes: 65916a1ca9 ("dt-bindings: pinctrl: update bindings for MT7986 SoC")
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221106080114.7426-3-linux@fw-web.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Frank Wunderlich
2022-11-06 09:01:09 +01:00
committed by Greg Kroah-Hartman
parent 9e203e4373
commit afe3309ded
1 changed files with 41 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

46
Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml
View File

@@ -87,6 +87,8 @@ patternProperties:
"wifi_led" "led" 1, 2
"i2c" "i2c" 3, 4
"uart1_0" "uart" 7, 8, 9, 10
"uart1_rx_tx" "uart" 42, 43
"uart1_cts_rts" "uart" 44, 45
"pcie_clk" "pcie" 9
"pcie_wake" "pcie" 10
"spi1_0" "spi" 11, 12, 13, 14
@@ -98,9 +100,11 @@ patternProperties:
"emmc_45" "emmc" 22, 23, 24, 25, 26, 27, 28, 29, 30,
31, 32
"spi1_1" "spi" 23, 24, 25, 26
"uart1_2" "uart" 29, 30, 31, 32
"uart1_2_rx_tx" "uart" 29, 30
"uart1_2_cts_rts" "uart" 31, 32
"uart1_1" "uart" 23, 24, 25, 26
"uart2_0" "uart" 29, 30, 31, 32
"uart2_0_rx_tx" "uart" 29, 30
"uart2_0_cts_rts" "uart" 31, 32
"spi0" "spi" 33, 34, 35, 36
"spi0_wp_hold" "spi" 37, 38
"uart1_3_rx_tx" "uart" 35, 36
@@ -157,7 +161,7 @@ patternProperties:
then:
properties:
groups:
enum: [emmc, emmc_rst]
enum: [emmc_45, emmc_51]
- if:
properties:
function:
@@ -221,8 +225,12 @@ patternProperties:
then:
properties:
groups:
enum: [uart1_0, uart1_1, uart1_2, uart1_3_rx_tx,
uart1_3_cts_rts, uart2_0, uart2_1, uart0, uart1, uart2]
items:
enum: [uart1_0, uart1_rx_tx, uart1_cts_rts, uart1_1,
uart1_2_rx_tx, uart1_2_cts_rts, uart1_3_rx_tx,
uart1_3_cts_rts, uart2_0_rx_tx, uart2_0_cts_rts,
uart2_1, uart0, uart1, uart2]
maxItems: 2
- if:
properties:
function:
@@ -356,6 +364,27 @@ examples:
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
pcie_pins: pcie-pins {
mux {
function = "pcie";
groups = "pcie_clk", "pcie_wake", "pcie_pereset";
};
};
pwm_pins: pwm-pins {
mux {
function = "pwm";
groups = "pwm0", "pwm1_0";
};
};
spi0_pins: spi0-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
};
uart1_pins: uart1-pins {
mux {
function = "uart";
@@ -363,6 +392,13 @@ examples:
};
};
uart1_3_pins: uart1-3-pins {
mux {
function = "uart";
groups = "uart1_3_rx_tx", "uart1_3_cts_rts";
};
};
uart2_pins: uart2-pins {
mux {
function = "uart";