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rk312x dts: add fb/screen/lcdc/lvds dt node

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This commit is contained in:
zwl
2014-07-29 11:30:00 +08:00
parent f178341434
commit b017600ce3
4 changed files with 89 additions and 0 deletions
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13
arch/arm/boot/dts/rk3126-fpga.dts
View File

@@ -18,4 +18,17 @@
fiq-debugger {
status = "okay";
};
&fb {
rockchip,disp-mode = <ONE_DUAL>;
};
&rk_screen {
display-timings = <&disp_timings>;
};
&lcdc {
status = "okay";
};
};

22
arch/arm/boot/dts/rk3126-sdk.dts
View File

@@ -71,6 +71,28 @@
};
};
&fb {
rockchip,disp-mode = <ONE_DUAL>;
rockchip,uboot-logo-on = <0>;
};
&rk_screen {
//display-timings = <&disp_timings>;
};
&lcdc {
status = "okay";
power_ctr: power_ctr {
rockchip,debug = <0>;
lcd_en: lcd_en {
rockchip,power_type = <GPIO>;
gpios = <&gpio1 GPIO_B3 GPIO_ACTIVE_HIGH>;
rockchip,delay = <10>;
};
};
};
/include/ "rk818.dtsi"
&rk818 {
gpios =<&gpio1 GPIO_B1 GPIO_ACTIVE_HIGH>,<&gpio1 GPIO_A1 GPIO_ACTIVE_LOW>;

22
arch/arm/boot/dts/rk312x-pinctrl.dtsi
View File

@@ -792,6 +792,28 @@
};
gpio2_lcdc0 {
lcdc0_lcdc:lcdc0-lcdc {
rockchip,pins =
<LCDC0_DCLK>,
<LCDC0_DEN>,
<LCDC0_HSYNC>,
<LCDC0_VSYNC>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
};
lcdc0_gpio:lcdc0-gpio {
rockchip,pins =
<FUNC_TO_GPIO(LCDC0_DCLK)>,
<FUNC_TO_GPIO(LCDC0_DEN)>,
<FUNC_TO_GPIO(LCDC0_HSYNC)>,
<FUNC_TO_GPIO(LCDC0_VSYNC)>;
rockchip,pull = <VALUE_PULL_DISABLE>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
};
};
//to add

32
arch/arm/boot/dts/rk312x.dtsi
View File

@@ -2,6 +2,7 @@
#include <dt-bindings/suspend/rockchip-pm.h>
#include <dt-bindings/sensor-dev.h>
#include <dt-bindings/clock/rk_system_status.h>
#include <dt-bindings/rkfb/rk_fb.h>
#include "skeleton.dtsi"
#include "rk312x-clocks.dtsi"
@@ -19,6 +20,7 @@
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
lcdc = &lcdc;
// spi0 = &spi0;
};
@@ -539,6 +541,36 @@
status = "disabled";
};
fb: fb{
compatible = "rockchip,rk-fb";
rockchip,disp-mode = <ONE_DUAL>;
};
rk_screen: rk_screen{
compatible = "rockchip,screen";
};
lvds: lvds@20038000 {
compatible = "rockchip,rk31xx-lvds";
reg = <0x20038000 0x4000>;
clocks = <&clk_gates5 0>;
clock-names = "pclk_lvds";
};
lcdc: lcdc@1010e000 {
compatible = "rockchip,rk312x-lcdc";
rockchip,prop = <PRMRY>;
reg = <0x1010e000 0x2000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&lcdc0_lcdc>;
pinctrl-1 = <&lcdc0_gpio>;
clocks = <&clk_gates6 0>, <&dclk_lcdc0>, <&clk_gates6 1>, <&sclk_lcdc0>;
clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk";
rockchip,iommu-enabled = <1>;
status = "disabled";
};
vpu: vpu_service@10104000 {
compatible = "vpu_service";
reg = <0x10104000 0x800>;