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Merge commit '62e90871a6b7e899edb894d3dd3fc7ea0c1983de'

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* commit '62e90871a6b7e899edb894d3dd3fc7ea0c1983de': (22 commits)
  media: rockchip: isp: fix isp32 mp buf cfg
  drm/rockchip: lvds: register sub dev at rockchip lvds driver
  arm64: configs: add rk3308_rkpartybox.config
  media: i2c: add sc831ai sensor driver
  drm/rockchip: lvds: register sub dev at rockchip lvds driver
  drm/rockchip: rgb: register sub dev at rockchip rgb driver
  soc: rockchip: power-domain: Update gate mask for rk3562
  arm64: dts: rockchip: rk3588-vehicle-evb: add spi codec reset gpio
  drm/rockchip: vop2: clearly point out the plane unsupported format modifier
  arm64: dts: rockchip: rk3588-vehicle-evb: fix image reverse mipi_csi node
  arm64: dts: rockchip: rk3562-evb: fix image reverse mipi_csi node
  video: rockchip: vehicle: fix bugs of cif get csi_fmt_val
  ARM: rockchip: rv1106: sleep: use rtc as 32k source
  ARM: rockchip: rv1106_pm: improve the accuracy of recovering hptimer
  soc: rockchip: pm_config: initialize sleep_config to 0
  rtc: rockchip: support rtc suspend bypass
  Mali: midgard: Add support for static power consumption calculation
  arm64: dts: rockchip: rk3399: Add dynamic-power-coefficient property for gpu
  debugfs: cma: fix bitmap_hex
  clk: rockchip: add new pll type pll_rk3588_ddr
  ...

Change-Id: Ifbdbd329da8ab96ccb107662358ff1d9fc490cb8
This commit is contained in:
Tao Huang
2024-01-31 21:17:53 +08:00
parent 00b6e30e85 62e90871a6
commit b0b65f0c85
28 changed files with 2282 additions and 90 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
arch/arm/mach-rockchip/rockchip_hptimer.c
View File

@@ -92,18 +92,23 @@ static int rk_hptimer_wait_begin_end_valid(void __iomem *base, u64 wait_us)
}
}
static u64 rk_hptimer_get_soft_adjust_delt_cnt(void __iomem *base)
static u64 rk_hptimer_get_soft_adjust_delt_cnt(void __iomem *base, u32 hf, u32 lf)
{
u64 begin, end, delt;
u32 tmp;
if (rk_hptimer_wait_begin_end_valid(base, HPTIMER_WAIT_MAX_US))
return 0;
/* (T32_24END - T24_32BEGIN + 2) * (T24 - T32) / T32 + 2.5 * T24/T32 + 2 */
begin = (u64)readl_relaxed(base + TIMER_HP_T24_32BEGIN0) |
(u64)readl_relaxed(base + TIMER_HP_T24_32BEGIN1) << 32;
end = (u64)readl_relaxed(base + TIMER_HP_T32_24END0) |
(u64)readl_relaxed(base + TIMER_HP_T32_24END1) << 32;
delt = (end - begin) * T24M_GCD / T32K_GCD;
delt = (end - begin + 2) * (hf - lf);
delt = div_u64(delt, lf);
tmp = (2 * hf + hf / 2) / lf;
delt = delt + tmp + 2;
writel_relaxed(0x3, base + TIMER_HP_BEGIN_END_VALID);
@@ -167,18 +172,18 @@ int rk_hptimer_wait_mode(void __iomem *base, enum rk_hptimer_mode_t mode)
return 0;
}
void rk_hptimer_do_soft_adjust(void __iomem *base)
void rk_hptimer_do_soft_adjust(void __iomem *base, u32 hf, u32 lf)
{
u64 delt = rk_hptimer_get_soft_adjust_delt_cnt(base);
u64 delt = rk_hptimer_get_soft_adjust_delt_cnt(base, hf, lf);
rk_hptimer_soft_adjust_req(base, delt);
rk_hptimer_wait_mode(base, RK_HPTIMER_SOFT_ADJUST_MODE);
}
void rk_hptimer_do_soft_adjust_no_wait(void __iomem *base)
void rk_hptimer_do_soft_adjust_no_wait(void __iomem *base, u32 hf, u32 lf)
{
u64 delt = rk_hptimer_get_soft_adjust_delt_cnt(base);
u64 delt = rk_hptimer_get_soft_adjust_delt_cnt(base, hf, lf);
rk_hptimer_soft_adjust_req(base, delt);
}

4
arch/arm/mach-rockchip/rockchip_hptimer.h
View File

@@ -16,7 +16,7 @@ int rk_hptimer_is_enabled(void __iomem *base);
int rk_hptimer_get_mode(void __iomem *base);
u64 rk_hptimer_get_count(void __iomem *base);
int rk_hptimer_wait_mode(void __iomem *base, enum rk_hptimer_mode_t mode);
void rk_hptimer_do_soft_adjust(void __iomem *base);
void rk_hptimer_do_soft_adjust_no_wait(void __iomem *base);
void rk_hptimer_do_soft_adjust(void __iomem *base, u32 hf, u32 lf);
void rk_hptimer_do_soft_adjust_no_wait(void __iomem *base, u32 hf, u32 lf);
void rk_hptimer_mode_init(void __iomem *base, enum rk_hptimer_mode_t mode);
#endif

44
arch/arm/mach-rockchip/rv1106_pm.c
View File

@@ -55,6 +55,7 @@ struct rv1106_sleep_ddr_data {
u32 gpio0a_iomux_l, gpio0a_iomux_h, gpio0a0_pull;
u32 gpio0_ddr_l, gpio0_ddr_h;
u32 pmu_wkup_int_st, gpio0_int_st;
u32 sleep_clk_freq_hz;
};
static struct rv1106_sleep_ddr_data ddr_data;
@@ -602,28 +603,27 @@ static void clock_resume(void)
vocru_base + RV1106_VOCRU_GATE_CON(i));
}
static void pvtm_32k_config(int flag)
static void pvtm_32k_config(void)
{
int value;
int pvtm_freq_khz, pvtm_div;
int sleep_clk_freq_khz;
u64 value, pvtm_freq_hz;
int pvtm_div;
u32 pvtm_div_freq_hz;
ddr_data.pmucru_sel_con7 =
readl_relaxed(pmucru_base + RV1106_PMUCRU_CLKSEL_CON(7));
if (flag) {
writel_relaxed(BITS_WITH_WMASK(0x1, 0x1, 6), vigrf_base + 0x0);
writel_relaxed(BITS_WITH_WMASK(0x4, 0xf, 0), ioc_base[0] + 0);
writel_relaxed(BITS_WITH_WMASK(0x1, 0x1, 15),
if (slp_cfg->mode_config & RKPM_SLP_32K_EXT) {
writel_relaxed(BITS_WITH_WMASK(0x3, 0x3, 14),
pmugrf_base + RV1106_PMUGRF_SOC_CON(1));
writel_relaxed(BITS_WITH_WMASK(0x1, 0x3, 0),
pmucru_base + RV1106_PMUCRU_CLKSEL_CON(7));
ddr_data.sleep_clk_freq_hz = 32768;
} else {
writel_relaxed(BITS_WITH_WMASK(0, 0x3, 0),
pmupvtm_base + RV1106_PVTM_CON(2));
writel_relaxed(RV1106_PVTM_CALC_CNT,
pmupvtm_base + RV1106_PVTM_CON(1));
writel_relaxed(BITS_WITH_WMASK(0, 0x3, PVTM_START),
writel_relaxed(BITS_WITH_WMASK(0, 0x1, PVTM_START),
pmupvtm_base + RV1106_PVTM_CON(0));
dsb();
@@ -648,8 +648,11 @@ static void pvtm_32k_config(int flag)
;
value = (readl_relaxed(pmupvtm_base + RV1106_PVTM_STATUS(1)));
pvtm_freq_khz = (value * 24000 + RV1106_PVTM_CALC_CNT / 2) / RV1106_PVTM_CALC_CNT;
pvtm_div = (pvtm_freq_khz + 16) / 32 - 1;
pvtm_freq_hz = (value * 24000000 + RV1106_PVTM_CALC_CNT / 2);
pvtm_freq_hz = div_u64(pvtm_freq_hz, RV1106_PVTM_CALC_CNT);
pvtm_div = ((u32)pvtm_freq_hz + RV1106_PVTM_TARGET_FREQ / 2) /
RV1106_PVTM_TARGET_FREQ - 1;
if (pvtm_div > 0xfff)
pvtm_div = 0xfff;
@@ -660,12 +663,19 @@ static void pvtm_32k_config(int flag)
writel_relaxed(BITS_WITH_WMASK(0x2, 0x3, 0),
pmucru_base + RV1106_PMUCRU_CLKSEL_CON(7));
sleep_clk_freq_khz = pvtm_freq_khz / (pvtm_div + 1);
pvtm_div_freq_hz = (u32)pvtm_freq_hz / (pvtm_div + 1);
ddr_data.sleep_clk_freq_hz = pvtm_div_freq_hz;
rkpm_printstr("pvtm real_freq (khz):");
rkpm_printhex(sleep_clk_freq_khz);
rkpm_printstr("pvtm freq (hz):");
rkpm_printdec(pvtm_freq_hz);
rkpm_printch('-');
rkpm_printdec(pvtm_div_freq_hz);
rkpm_printch('\n');
}
rkpm_printstr("sleep freq (hz):");
rkpm_printdec(ddr_data.sleep_clk_freq_hz);
rkpm_printch('\n');
}
static void pvtm_32k_config_restore(void)
@@ -674,7 +684,9 @@ static void pvtm_32k_config_restore(void)
pmucru_base + RV1106_PMUCRU_CLKSEL_CON(7));
if (rk_hptimer_get_mode(hptimer_base) == RK_HPTIMER_SOFT_ADJUST_MODE)
rk_hptimer_do_soft_adjust_no_wait(hptimer_base);
rk_hptimer_do_soft_adjust_no_wait(hptimer_base,
24000000,
ddr_data.sleep_clk_freq_hz);
}
static void ddr_sleep_config(void)
@@ -874,7 +886,7 @@ static void soc_sleep_config(void)
rkpm_printch('a');
pvtm_32k_config(0);
pvtm_32k_config();
rkpm_printch('b');
ddr_sleep_config();

3
arch/arm/mach-rockchip/rv1106_pm.h
View File

@@ -129,7 +129,8 @@
#define RV1106_PVTM_INTSTS 0x74
#define RV1106_PVTM_STATUS(i) (0x80 + (i) * 4)
#define RV1106_PVTM_CALC_CNT 0x200
#define RV1106_PVTM_CALC_CNT 24000
#define RV1106_PVTM_TARGET_FREQ 32768
/* gpio */
#define RV1106_GPIO_SWPORT_DR_L 0x0000

3
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View File

@@ -2353,10 +2353,11 @@
downdifferential = <10>;
status = "disabled";
dynamic-power-coefficient = <733>;
gpu_power_model: power_model {
compatible = "arm,mali-simple-power-model";
static-coefficient = <411000>;
dynamic-coefficient = <733>;
ts = <32000 4700 (-80) 2>;
thermal-zone = "gpu-thermal";
};

4
arch/arm64/boot/dts/rockchip/rk3562-evb2-image-reverse.dtsi
View File

@@ -102,7 +102,7 @@
"srst_csihost_p";
csihost-idx = <0>;
rockchip,csi2-dphy = <&csi2_dphy0_hw>;
rockchip,csi2 = <&mipi0_csi2>;
rockchip,csi2 = <&mipi0_csi2_hw>;
};
csi2_dphy3 {
status = "disabled";
@@ -118,7 +118,7 @@
"srst_csihost_p";
csihost-idx = <2>;
rockchip,csi2-dphy = <&csi2_dphy1_hw>;
rockchip,csi2 = <&mipi2_csi2>;
rockchip,csi2 = <&mipi2_csi2_hw>;
};
};

8
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-image-reverse.dtsi
View File

@@ -90,7 +90,7 @@
reset-names = "srst_csihost_p",
"srst_csihost_vicap";
csihost-idx = <0>;
rockchip,csi2 = <&mipi0_csi2>;
rockchip,csi2 = <&mipi0_csi2_hw>;
phys = <&mipi_dcphy0>;
phy-names = "dcphy";
};
@@ -109,7 +109,7 @@
reset-names = "srst_csihost_p",
"srst_csihost_vicap";
csihost-idx = <1>;
rockchip,csi2 = <&mipi1_csi2>;
rockchip,csi2 = <&mipi1_csi2_hw>;
phys = <&mipi_dcphy1>;
phy-names = "dcphy";
};
@@ -132,7 +132,7 @@
csihost-idx = <2>;
rockchip,dphy-grf = <&mipidphy0_grf>;
rockchip,csi2-dphy = <&csi2_dphy0_hw>;
rockchip,csi2 = <&mipi2_csi2>;
rockchip,csi2 = <&mipi2_csi2_hw>;
};
/* only rk3588 */
csi2_dphy3 {
@@ -154,7 +154,7 @@
csihost-idx = <4>;
rockchip,dphy-grf = <&mipidphy1_grf>;
rockchip,csi2-dphy = <&csi2_dphy1_hw>;
rockchip,csi2 = <&mipi4_csi2>;
rockchip,csi2 = <&mipi4_csi2_hw>;
};
rkcif_dvp {
status = "disabled";

3
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dtsi
View File

@@ -274,7 +274,7 @@
rk3308 {
rk3308_reset: rk3308-reset {
rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
@@ -331,6 +331,7 @@
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&rk3308_reset>;
reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};

3
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dtsi
View File

@@ -287,7 +287,7 @@
rk3308 {
rk3308_reset: rk3308-reset {
rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
@@ -344,6 +344,7 @@
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&rk3308_reset>;
reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};

227
arch/arm64/configs/rk3308_rkpartybox.config Normal file
View File

@@ -0,0 +1,227 @@
CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
CONFIG_FAT_DEFAULT_UTF8=y
CONFIG_FAT_FS=y
CONFIG_FUSE_FS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_936=y
CONFIG_NLS_CODEPAGE_950=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
CONFIG_NTFS_FS=y
CONFIG_NTFS_RW=y
CONFIG_PHY_ROCKCHIP_USB=y
CONFIG_SCSI=y
CONFIG_USB=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_VFAT_FS=y
# CONFIG_APPLE_MFI_FASTCHARGE is not set
# CONFIG_AR5523 is not set
# CONFIG_AT76C50X_USB is not set
# CONFIG_ATH9K_HTC is not set
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_SCSI_REQUEST=y
# CONFIG_BT_HCIBCM203X is not set
# CONFIG_BT_HCIBFUSB is not set
# CONFIG_BT_HCIBPA10X is not set
# CONFIG_BT_HCIBTUSB is not set
# CONFIG_CARL9170 is not set
# CONFIG_CHR_DEV_SCH is not set
# CONFIG_CHR_DEV_SG is not set
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CUSE is not set
# CONFIG_DRM_GM12U320 is not set
# CONFIG_DRM_UDL is not set
CONFIG_DVB_RTL2832_SDR=m
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
CONFIG_FRAME_VECTOR=y
CONFIG_FS_POSIX_ACL=y
# CONFIG_HID_ACCUTOUCH is not set
# CONFIG_HID_APPLEIR is not set
# CONFIG_HID_ASUS is not set
# CONFIG_HID_BETOP_FF is not set
# CONFIG_HID_BIGBEN_FF is not set
# CONFIG_HID_CHICONY is not set
# CONFIG_HID_CORSAIR is not set
# CONFIG_HID_CREATIVE_SB0540 is not set
# CONFIG_HID_ELAN is not set
# CONFIG_HID_ELO is not set
# CONFIG_HID_GT683R is not set
# CONFIG_HID_HOLTEK is not set
# CONFIG_HID_LOGITECH is not set
# CONFIG_HID_MCP2221 is not set
# CONFIG_HID_NTRIG is not set
# CONFIG_HID_PENMOUNT is not set
# CONFIG_HID_PID is not set
# CONFIG_HID_PRODIKEYS is not set
# CONFIG_HID_RETRODE is not set
# CONFIG_HID_ROCCAT is not set
# CONFIG_HID_SAMSUNG is not set
# CONFIG_HID_SONY is not set
# CONFIG_HID_U2FZERO is not set
# CONFIG_HID_UCLOGIC is not set
# CONFIG_HID_WACOM is not set
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TINY_USB is not set
# CONFIG_INPUT_IMS_PCU is not set
# CONFIG_ISCSI_BOOT_SYSFS is not set
# CONFIG_ISCSI_TCP is not set
# CONFIG_LTE_GDM724X is not set
# CONFIG_MDIO_MVUSB is not set
# CONFIG_MEDIA_USB_SUPPORT is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MISC_RTSX_USB is not set
# CONFIG_MMC_USHC is not set
# CONFIG_MMC_VUB300 is not set
# CONFIG_MT7601U is not set
# CONFIG_MT7663U is not set
# CONFIG_MT76x0U is not set
# CONFIG_MT76x2U is not set
# CONFIG_PRISM2_USB is not set
# CONFIG_R8188EU is not set
# CONFIG_R8712U is not set
# CONFIG_RADIO_SHARK is not set
# CONFIG_RADIO_SHARK2 is not set
# CONFIG_RTL8187 is not set
# CONFIG_RTL8192CU is not set
# CONFIG_RTL8XXXU is not set
CONFIG_RTL_CARDS=y
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_DH is not set
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_LOGGING is not set
CONFIG_SCSI_LOWLEVEL=y
CONFIG_SCSI_PROC_FS=y
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# CONFIG_SCSI_UFSHCD is not set
# CONFIG_SCSI_VIRTIO is not set
CONFIG_SG_POOL=y
# CONFIG_SND_BCD2000 is not set
CONFIG_SND_USB=y
# CONFIG_SND_USB_6FIRE is not set
# CONFIG_SND_USB_AUDIO is not set
# CONFIG_SND_USB_CAIAQ is not set
# CONFIG_SND_USB_HIFACE is not set
# CONFIG_SND_USB_POD is not set
# CONFIG_SND_USB_PODHD is not set
# CONFIG_SND_USB_TONEPORT is not set
# CONFIG_SND_USB_UA101 is not set
# CONFIG_SND_USB_VARIAX is not set
# CONFIG_USBIP_CORE is not set
# CONFIG_USBPCWATCHDOG is not set
# CONFIG_USB_ACM is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
# CONFIG_USB_APPLEDISPLAY is not set
CONFIG_USB_AUTOSUSPEND_DELAY=2
# CONFIG_USB_C67X00_HCD is not set
# CONFIG_USB_CATC is not set
# CONFIG_USB_CHAOSKEY is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_DSBR is not set
# CONFIG_USB_DUMMY_HCD is not set
# CONFIG_USB_DWC2_DUAL_ROLE is not set
# CONFIG_USB_DWC2_HOST is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_EHCI_FSL is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
CONFIG_USB_EHCI_TT_NEWSCHED=y
# CONFIG_USB_EHSET_TEST_FIXTURE is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EZUSB_FX2 is not set
# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_FOTG210_HCD is not set
# CONFIG_USB_FTDI_ELAN is not set
CONFIG_USB_F_UAC1=y
CONFIG_USB_F_UAC2=y
# CONFIG_USB_HCD_TEST_MODE is not set
CONFIG_USB_HID=y
# CONFIG_USB_HIDDEV is not set
# CONFIG_USB_HSIC_USB3503 is not set
# CONFIG_USB_HSIC_USB4604 is not set
# CONFIG_USB_HSO is not set
# CONFIG_USB_HUB_USB251XB is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_IPHETH is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_KEENE is not set
# CONFIG_USB_LAN78XX is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LINK_LAYER_TEST is not set
# CONFIG_USB_MA901 is not set
# CONFIG_USB_MAX3421_HCD is not set
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USB_MON is not set
# CONFIG_USB_MR800 is not set
CONFIG_USB_NET_DRIVERS=y
# CONFIG_USB_NET_RNDIS_WLAN is not set
# CONFIG_USB_OHCI_HCD is not set
# CONFIG_USB_OTG is not set
# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
# CONFIG_USB_OTG_PRODUCTLIST is not set
# CONFIG_USB_OXU210HP_HCD is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_PRINTER is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_RAREMONO is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_RTL8152 is not set
# CONFIG_USB_SERIAL is not set
# CONFIG_USB_SEVSEG is not set
# CONFIG_USB_SISUSBVGA is not set
# CONFIG_USB_SL811_HCD is not set
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_ALAUDA is not set
# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_ENE_UB6250 is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_KARMA is not set
# CONFIG_USB_STORAGE_ONETOUCH is not set
# CONFIG_USB_STORAGE_REALTEK is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_SDDR55 is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_TMC is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_UAS is not set
# CONFIG_USB_USBNET is not set
CONFIG_USB_U_AUDIO=y
# CONFIG_USB_WDM is not set
# CONFIG_USB_XHCI_HCD is not set
# CONFIG_USB_YUREX is not set
# CONFIG_USB_ZD1201 is not set
CONFIG_VIDEOBUF2_CORE=m
CONFIG_VIDEOBUF2_MEMOPS=m
CONFIG_VIDEOBUF2_V4L2=m
CONFIG_VIDEOBUF2_VMALLOC=m
# CONFIG_VIRTIO_FS is not set
# CONFIG_VT6656 is not set
# CONFIG_ZD1211RW is not set

6
drivers/clk/rockchip/clk-pll.c
View File

@@ -1409,7 +1409,10 @@ static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw,
}
rate64 = rate64 >> cur.s;
return (unsigned long)rate64;
if (pll->type == pll_rk3588_ddr)
return (unsigned long)rate64 * 2;
else
return (unsigned long)rate64;
}
static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
@@ -1845,6 +1848,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
#ifdef CONFIG_ROCKCHIP_PLL_RK3588
case pll_rk3588:
case pll_rk3588_core:
case pll_rk3588_ddr:
if (!pll->rate_table)
init.ops = &rockchip_rk3588_pll_clk_norate_ops;
else

1
drivers/clk/rockchip/clk.h
View File

@@ -452,6 +452,7 @@ enum rockchip_pll_type {
pll_rk3399,
pll_rk3588,
pll_rk3588_core,
pll_rk3588_ddr,
};
#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \

19
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_devfreq.c
View File

@@ -343,6 +343,7 @@ int kbase_devfreq_init(struct kbase_device *kbdev)
unsigned long opp_rate;
unsigned int dyn_power_coeff = 0;
int err;
struct device_node *model_dt_node;
if (!kbdev->clock) {
dev_err(kbdev->dev, "Clock not available for devfreq\n");
@@ -373,10 +374,20 @@ int kbase_devfreq_init(struct kbase_device *kbdev)
&ondemand_data.upthreshold);
of_property_read_u32(np, "downdifferential",
&ondemand_data.downdifferential);
of_property_read_u32(kbdev->dev->of_node, "dynamic-power-coefficient",
&dyn_power_coeff);
if (dyn_power_coeff)
dp->is_cooling_device = true;
model_dt_node = of_get_compatible_child(np, "arm,mali-simple-power-model");
if (!model_dt_node) {
err = of_property_read_u32(np, "dynamic-power-coefficient",
&dyn_power_coeff);
if (err) {
dev_err(kbdev->dev, "Couldn't find proper 'dynamic-power-coefficient' in DT\n");
goto devfreq_add_dev_failed;
} else {
dp->is_cooling_device = true;
}
} else {
of_node_put(model_dt_node);
}
kbdev->devfreq = devfreq_add_device(kbdev->dev, dp,
"simple_ondemand", &ondemand_data);

2
drivers/gpu/arm/midgard/ipa/mali_kbase_ipa.c
View File

@@ -584,6 +584,8 @@ struct devfreq_cooling_power kbase_ipa_power_model_ops = {
#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0)
.get_static_power = &kbase_get_static_power,
.get_dynamic_power = &kbase_get_dynamic_power,
#else
.get_real_power = kbase_get_real_power,
#endif
};
KBASE_EXPORT_TEST_API(kbase_ipa_power_model_ops);

6
drivers/gpu/arm/midgard/ipa/mali_kbase_ipa_simple.c
View File

@@ -145,9 +145,9 @@ static int add_params(struct kbase_ipa_model *model)
if (err)
goto end;
err = kbase_ipa_model_add_param_s32(model, "dynamic-coefficient",
&model_data->dynamic_coefficient,
1, true);
err = of_property_read_u32_array(model->kbdev->dev->of_node,
"dynamic-power-coefficient",
&model_data->dynamic_coefficient, 1);
if (err)
goto end;

25
drivers/gpu/arm/midgard/mali_kbase_mem_linux.c
View File

@@ -2364,6 +2364,23 @@ void kbase_vunmap(struct kbase_context *kctx, struct kbase_vmap_struct *map)
}
KBASE_EXPORT_TEST_API(kbase_vunmap);
static void kbasep_add_mm_counter(struct mm_struct *mm, int member, long value)
{
#if (KERNEL_VERSION(6, 2, 0) <= LINUX_VERSION_CODE)
/* To avoid the build breakage due to the type change in rss_stat,
* we inline here the equivalent of 'add_mm_counter()' from linux kernel V6.2.
*/
percpu_counter_add(&mm->rss_stat[member], value);
#elif (KERNEL_VERSION(5, 5, 0) <= LINUX_VERSION_CODE)
/* To avoid the build breakage due to an unexported kernel symbol 'mm_trace_rss_stat',
* we inline here the equivalent of 'add_mm_counter()' from linux kernel V5.5.
*/
atomic_long_add(value, &mm->rss_stat.count[member]);
#else
add_mm_counter(mm, member, value);
#endif
}
void kbasep_os_process_page_usage_update(struct kbase_context *kctx, int pages)
{
struct mm_struct *mm;
@@ -2373,10 +2390,10 @@ void kbasep_os_process_page_usage_update(struct kbase_context *kctx, int pages)
if (mm) {
atomic_add(pages, &kctx->nonmapped_pages);
#ifdef SPLIT_RSS_COUNTING
add_mm_counter(mm, MM_FILEPAGES, pages);
kbasep_add_mm_counter(mm, MM_FILEPAGES, pages);
#else
spin_lock(&mm->page_table_lock);
add_mm_counter(mm, MM_FILEPAGES, pages);
kbasep_add_mm_counter(mm, MM_FILEPAGES, pages);
spin_unlock(&mm->page_table_lock);
#endif
}
@@ -2401,10 +2418,10 @@ static void kbasep_os_process_page_usage_drain(struct kbase_context *kctx)
pages = atomic_xchg(&kctx->nonmapped_pages, 0);
#ifdef SPLIT_RSS_COUNTING
add_mm_counter(mm, MM_FILEPAGES, -pages);
kbasep_add_mm_counter(mm, MM_FILEPAGES, -pages);
#else
spin_lock(&mm->page_table_lock);
add_mm_counter(mm, MM_FILEPAGES, -pages);
kbasep_add_mm_counter(mm, MM_FILEPAGES, -pages);
spin_unlock(&mm->page_table_lock);
#endif
}

5
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -2273,7 +2273,7 @@ static bool rockchip_vop2_mod_supported(struct drm_plane *plane, u32 format, u64
return true;
if (!rockchip_afbc(plane, modifier) && !rockchip_tiled(plane, modifier)) {
DRM_ERROR("Unsupported format modifier 0x%llx\n", modifier);
DRM_ERROR("%s unsupported format modifier 0x%llx\n", plane->name, modifier);
return false;
}
@@ -6327,7 +6327,8 @@ static void vop2_dump_connector_on_crtc(struct drm_crtc *crtc, struct seq_file *
drm_connector_list_iter_begin(crtc->dev, &conn_iter);
drm_for_each_connector_iter(connector, &conn_iter) {
if (crtc->state->connector_mask & drm_connector_mask(connector))
DEBUG_PRINT(" Connector: %s\n", connector->name);
DEBUG_PRINT(" Connector:%s\tEncoder: %s\n",
connector->name, connector->encoder->name);
}
drm_connector_list_iter_end(&conn_iter);

27
drivers/gpu/drm/rockchip/rockchip_lvds.c
View File

@@ -693,7 +693,8 @@ static int rockchip_lvds_bind(struct device *dev, struct device *master,
struct rockchip_lvds *lvds = dev_get_drvdata(dev);
struct drm_device *drm_dev = data;
struct drm_encoder *encoder = &lvds->encoder;
struct drm_connector *connector = &lvds->connector;
struct drm_connector *connector = NULL;
struct rockchip_drm_private *private = drm_dev->dev_private;
int ret;
/*
@@ -721,8 +722,7 @@ static int rockchip_lvds_bind(struct device *dev, struct device *master,
drm_encoder_helper_add(encoder, &rockchip_lvds_encoder_helper_funcs);
if (lvds->panel) {
struct rockchip_drm_private *private = drm_dev->dev_private;
connector = &lvds->connector;
ret = drm_connector_init(drm_dev, connector,
&rockchip_lvds_connector_funcs,
DRM_MODE_CONNECTOR_LVDS);
@@ -750,19 +750,28 @@ static int rockchip_lvds_bind(struct device *dev, struct device *master,
"failed to attach encoder: %d\n", ret);
goto err_free_connector;
}
lvds->sub_dev.connector = &lvds->connector;
lvds->sub_dev.of_node = lvds->dev->of_node;
lvds->sub_dev.loader_protect = rockchip_lvds_encoder_loader_protect;
rockchip_drm_register_sub_dev(&lvds->sub_dev);
drm_object_attach_property(&connector->base, private->connector_id_prop, 0);
} else {
struct list_head *connector_list;
ret = drm_bridge_attach(encoder, lvds->bridge, NULL, 0);
if (ret) {
DRM_DEV_ERROR(lvds->dev,
"failed to attach bridge: %d\n", ret);
goto err_free_encoder;
}
connector_list = &lvds->bridge->dev->mode_config.connector_list;
list_for_each_entry(connector, connector_list, head)
if (drm_connector_has_possible_encoder(connector, &lvds->encoder))
break;
}
if (connector) {
lvds->sub_dev.connector = connector;
lvds->sub_dev.of_node = lvds->dev->of_node;
lvds->sub_dev.loader_protect = rockchip_lvds_encoder_loader_protect;
drm_object_attach_property(&connector->base, private->connector_id_prop, lvds->id);
rockchip_drm_register_sub_dev(&lvds->sub_dev);
}
return 0;

25
drivers/gpu/drm/rockchip/rockchip_rgb.c
View File

@@ -823,7 +823,8 @@ static int rockchip_rgb_bind(struct device *dev, struct device *master,
struct rockchip_rgb *rgb = dev_get_drvdata(dev);
struct drm_device *drm_dev = data;
struct drm_encoder *encoder = &rgb->encoder;
struct drm_connector *connector;
struct drm_connector *connector = NULL;
struct rockchip_drm_private *private = drm_dev->dev_private;
int ret;
if (rgb->np_mcu_panel) {
@@ -875,8 +876,6 @@ static int rockchip_rgb_bind(struct device *dev, struct device *master,
drm_encoder_helper_add(encoder, &rockchip_rgb_encoder_helper_funcs);
if (rgb->panel) {
struct rockchip_drm_private *private = drm_dev->dev_private;
connector = &rgb->connector;
connector->interlace_allowed = true;
ret = drm_connector_init(drm_dev, connector,
@@ -898,12 +897,9 @@ static int rockchip_rgb_bind(struct device *dev, struct device *master,
"failed to attach encoder: %d\n", ret);
goto err_free_connector;
}
rgb->sub_dev.connector = &rgb->connector;
rgb->sub_dev.of_node = rgb->dev->of_node;
rgb->sub_dev.loader_protect = rockchip_rgb_encoder_loader_protect;
drm_object_attach_property(&connector->base, private->connector_id_prop, 0);
rockchip_drm_register_sub_dev(&rgb->sub_dev);
} else {
struct list_head *connector_list;
rgb->bridge->encoder = encoder;
ret = drm_bridge_attach(encoder, rgb->bridge, NULL, 0);
if (ret) {
@@ -911,6 +907,19 @@ static int rockchip_rgb_bind(struct device *dev, struct device *master,
"failed to attach bridge: %d\n", ret);
goto err_free_encoder;
}
connector_list = &rgb->bridge->dev->mode_config.connector_list;
list_for_each_entry(connector, connector_list, head)
if (drm_connector_has_possible_encoder(connector, &rgb->encoder))
break;
}
if (connector) {
rgb->sub_dev.connector = connector;
rgb->sub_dev.of_node = rgb->dev->of_node;
rgb->sub_dev.loader_protect = rockchip_rgb_encoder_loader_protect;
drm_object_attach_property(&connector->base, private->connector_id_prop, rgb->id);
rockchip_drm_register_sub_dev(&rgb->sub_dev);
}
return 0;

10
drivers/media/i2c/Kconfig
View File

@@ -1972,6 +1972,16 @@ config VIDEO_SC830AI
This is a Video4Linux2 sensor driver for the SmartSens
SC830AI camera.
config VIDEO_SC831AI
tristate "SmartSens SC831AI sensor support"
depends on I2C && VIDEO_DEV
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
select V4L2_FWNODE
help
This is a Video4Linux2 sensor driver for the SmartSens
SC831AI camera.
config VIDEO_SC850SL
tristate "SmartSens SC850SL sensor support"
depends on I2C && VIDEO_DEV

1
drivers/media/i2c/Makefile
View File

@@ -246,6 +246,7 @@ obj-$(CONFIG_VIDEO_SC501AI) += sc501ai.o
obj-$(CONFIG_VIDEO_SC530AI) += sc530ai.o
obj-$(CONFIG_VIDEO_SC5336) += sc5336.o
obj-$(CONFIG_VIDEO_SC830AI) += sc830ai.o
obj-$(CONFIG_VIDEO_SC831AI) += sc831ai.o
obj-$(CONFIG_VIDEO_SC850SL) += sc850sl.o
obj-$(CONFIG_VIDEO_SENSOR_ADAPTER) += sensor_adapter.o
obj-$(CONFIG_VIDEO_SGM3784) += sgm3784.o

1863
drivers/media/i2c/sc831ai.c Normal file
View File

File diff suppressed because it is too large Load Diff

2
drivers/media/platform/rockchip/isp/capture_v32.c
View File

@@ -752,7 +752,7 @@ static int mp_config_mi(struct rkisp_stream *stream)
mi_frame_end_int_enable(stream);
/* set up first buffer */
if (dev->cap_dev.wrap_line && stream->dummy_buf.mem_priv)
if (!dev->cap_dev.wrap_line || stream->dummy_buf.mem_priv)
mi_frame_end(stream, FRAME_INIT);
rkisp_unite_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);

18
drivers/rtc/rtc-rockchip.c
View File

@@ -86,6 +86,7 @@
#define RTC_VREF_INIT 0x40
#define CLK_32K_ENABLE BIT(5)
#define D2A_POR_REG_SEL1 BIT(4)
#define D2A_POR_REG_SEL0 BIT(1)
@@ -124,6 +125,7 @@ struct rockchip_rtc {
unsigned int flag;
unsigned int mode;
struct delayed_work trim_work;
bool suspend_bypass;
};
static unsigned int rockchip_rtc_write(struct regmap *map,
@@ -590,6 +592,9 @@ static int rockchip_rtc_suspend(struct device *dev)
struct platform_device *pdev = to_platform_device(dev);
struct rockchip_rtc *rtc = dev_get_drvdata(&pdev->dev);
if (rtc->suspend_bypass)
return 0;
if (device_may_wakeup(dev))
enable_irq_wake(rtc->irq);
@@ -619,6 +624,9 @@ static int rockchip_rtc_resume(struct device *dev)
struct rockchip_rtc *rtc = dev_get_drvdata(&pdev->dev);
int ret;
if (rtc->suspend_bypass)
return 0;
if (device_may_wakeup(dev))
disable_irq_wake(rtc->irq);
@@ -717,8 +725,10 @@ static int rockchip_rtc_probe(struct platform_device *pdev)
"Failed to add clk disable action.");
ret = rockchip_rtc_update_bits(rtc->regmap, RTC_VPTAT_TRIM,
D2A_POR_REG_SEL1,
D2A_POR_REG_SEL1);
D2A_POR_REG_SEL1 |
CLK_32K_ENABLE,
D2A_POR_REG_SEL1 |
CLK_32K_ENABLE);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"Failed to write RTC_VPTAT_TRIM\n");
@@ -788,6 +798,10 @@ static int rockchip_rtc_probe(struct platform_device *pdev)
"Failed to request alarm IRQ %d\n",
rtc->irq);
/* If rtc 32k used as time for deep sleep, the rtc suspend func bypass do nothing. */
rtc->suspend_bypass = device_property_read_bool(&pdev->dev,
"rockchip,rtc-suspend-bypass");
INIT_DELAYED_WORK(&rtc->trim_work, rockchip_rtc_compensation_delay_work);
rockchip_rtc_trim_start(rtc);

31
drivers/soc/rockchip/pm_domains.c
View File

@@ -188,7 +188,7 @@ static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd)
.keepon_startup = keepon, \
}
#define DOMAIN_M_C_SD(_name, pwr, status, req, idle, ack, clk, mem, wakeup, keepon) \
#define DOMAIN_M_G_SD(_name, pwr, status, req, idle, ack, g_mask, mem, wakeup, keepon) \
{ \
.name = _name, \
.pwr_w_mask = (pwr) << 16, \
@@ -198,8 +198,8 @@ static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd)
.req_mask = (req), \
.idle_mask = (idle), \
.ack_mask = (ack), \
.clk_ungate_mask = (clk), \
.clk_ungate_w_mask = (clk) << 16, \
.clk_ungate_mask = (g_mask), \
.clk_ungate_w_mask = (g_mask) << 16, \
.mem_num = (mem), \
.active_wakeup = wakeup, \
.keepon_startup = keepon, \
@@ -289,11 +289,11 @@ static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd)
#define DOMAIN_RK3528(pwr, req, always, wakeup) \
DOMAIN_M_A(pwr, pwr, req, req, req, always, wakeup, false)
#define DOMAIN_RK3562(name, pwr, req, mem, wakeup) \
DOMAIN_M_C_SD(name, pwr, pwr, req, req, req, req, mem, wakeup, false)
#define DOMAIN_RK3562(name, pwr, req, g_mask, mem, wakeup) \
DOMAIN_M_G_SD(name, pwr, pwr, req, req, req, g_mask, mem, wakeup, false)
#define DOMAIN_RK3562_PROTECT(name, pwr, req, mem, wakeup) \
DOMAIN_M_C_SD(name, pwr, pwr, req, req, req, req, mem, wakeup, true)
#define DOMAIN_RK3562_PROTECT(name, pwr, req, g_mask, mem, wakeup) \
DOMAIN_M_G_SD(name, pwr, pwr, req, req, req, g_mask, mem, wakeup, true)
#define DOMAIN_RK3568(name, pwr, req, wakeup) \
DOMAIN_M(name, pwr, pwr, req, req, req, wakeup, false)
@@ -1894,14 +1894,15 @@ static const struct rockchip_domain_info rk3528_pm_domains[] = {
};
static const struct rockchip_domain_info rk3562_pm_domains[] = {
[RK3562_PD_GPU] = DOMAIN_RK3562("gpu", BIT(0), BIT(1), 0, false),
[RK3562_PD_NPU] = DOMAIN_RK3562("npu", BIT(1), BIT(2), 0, false),
[RK3562_PD_VDPU] = DOMAIN_RK3562("vdpu", BIT(2), BIT(6), 0, false),
[RK3562_PD_VEPU] = DOMAIN_RK3562("vepu", BIT(3), BIT(7), 0, false),
[RK3562_PD_RGA] = DOMAIN_RK3562("rga", BIT(4), BIT(5), 0, false),
[RK3562_PD_VI] = DOMAIN_RK3562("vi", BIT(5), BIT(3), 0, false),
[RK3562_PD_VO] = DOMAIN_RK3562_PROTECT("vo", BIT(6), BIT(4), 16, false),
[RK3562_PD_PHP] = DOMAIN_RK3562("php", BIT(7), BIT(8), 0, false),
/* name pwr req g_mask mem wakeup */
[RK3562_PD_GPU] = DOMAIN_RK3562("gpu", BIT(0), BIT(1), BIT(1), 0, false),
[RK3562_PD_NPU] = DOMAIN_RK3562("npu", BIT(1), BIT(2), BIT(2), 0, false),
[RK3562_PD_VDPU] = DOMAIN_RK3562("vdpu", BIT(2), BIT(6), BIT(6), 0, false),
[RK3562_PD_VEPU] = DOMAIN_RK3562("vepu", BIT(3), BIT(7), BIT(7) | BIT(3), 0, false),
[RK3562_PD_RGA] = DOMAIN_RK3562("rga", BIT(4), BIT(5), BIT(5) | BIT(4), 0, false),
[RK3562_PD_VI] = DOMAIN_RK3562("vi", BIT(5), BIT(3), BIT(3), 0, false),
[RK3562_PD_VO] = DOMAIN_RK3562_PROTECT("vo", BIT(6), BIT(4), BIT(4), 16, false),
[RK3562_PD_PHP] = DOMAIN_RK3562("php", BIT(7), BIT(8), BIT(8), 0, false),
};
static const struct rockchip_domain_info rk3568_pm_domains[] = {

3
drivers/soc/rockchip/rockchip_pm_config.c
View File

@@ -441,7 +441,8 @@ static int pm_config_probe(struct platform_device *pdev)
sleep_config =
devm_kmalloc_array(&pdev->dev, RK_PM_STATE_MAX,
sizeof(*sleep_config), GFP_KERNEL);
sizeof(*sleep_config),
GFP_KERNEL | __GFP_ZERO);
if (!sleep_config)
return -ENOMEM;

10
drivers/video/rockchip/vehicle/vehicle_cif.c
View File

@@ -2747,9 +2747,8 @@ static int vehicle_cif_csi_channel_init(struct vehicle_cif *cif,
return -EINVAL;
}
}
// channel->fmt_val = fmt->csi_fmt_val;
/* set cif input format yuv422*/
channel->fmt_val = CSI_WRDDR_TYPE_YUV422;
channel->fmt_val = fmt->csi_fmt_val;
VEHICLE_INFO("%s, LINE=%d, channel->fmt_val = 0x%x, fmt->csi_fmt_val= 0x%x",
__func__, __LINE__, channel->fmt_val, fmt->csi_fmt_val);
/*
@@ -3225,6 +3224,7 @@ static int vehicle_cif_csi2_s_stream(struct vehicle_cif *cif,
} else {
val |= infmt->csi_yuv_order;
}
rkcif_write_reg(cif, get_reg_index_of_id_ctrl0(channel->id), val);
cif->state = RKCIF_STATE_STREAMING;
} else {
@@ -3266,7 +3266,7 @@ static int vehicle_cif_csi2_s_stream_v1(struct vehicle_cif *cif,
channel = &cif->channels[0];
if (enable) {
val = CSI_ENABLE_CAPTURE | CSI_DMA_ENABLE | channel->fmt_val |
val = CSI_ENABLE_CAPTURE | CSI_DMA_ENABLE |
channel->cmd_mode_en << 26 | CSI_ENABLE_CROP_V1 |
channel->id << 8 | channel->data_type << 10;
@@ -3275,7 +3275,7 @@ static int vehicle_cif_csi2_s_stream_v1(struct vehicle_cif *cif,
VEHICLE_INFO("Input fmt is invalid, use default!\n");
val |= CSI_YUV_INPUT_ORDER_UYVY;
} else {
val |= infmt->csi_yuv_order;
val |= infmt->csi_yuv_order | infmt->csi_fmt_val;
}
if (cfg->output_format == CIF_OUTPUT_FORMAT_420) {

2
mm/cma_debug_bitmap_hex.c
View File

@@ -96,7 +96,7 @@ static int cma_debugfs_add_one(struct cma *cma, struct dentry *root_dentry)
struct dentry *tmp;
char name[16];
scnprintf(name, sizeof(name), "cma-%s", cma->name);
scnprintf(name, sizeof(name), "%s", cma->name);
tmp = debugfs_lookup(name, root_dentry);
if (!tmp)