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https://github.com/hardkernel/linux.git
synced 2026-06-05 18:41:58 +09:00
arm64: dts: qcom: sm6375: Add QUPs and corresponding SPI/I2C hosts
Add necessary nodes to support various QUP configurations. Note that: - QUP3/4/5 and 11 are straight up missing - There may be more QUPs physically on the SoC that work perfectly fine, but Qualcomm decided not to expose them on the downstream kernel - Many are missing pinctrls, as there are both missing pin funcs in the TLMM driver and missing configuration settings (though they are possible to guesstimate quite easily) Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115152727.9736-6-konrad.dybcio@linaro.org
This commit is contained in:
Konrad Dybcio
committed by
Bjorn Andersson
Bjorn Andersson
parent
704edf03c0
commit
b0dfe3c9d6
@@ -5,6 +5,7 @@
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/clock/qcom,sm6375-gcc.h>
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#include <dt-bindings/dma/qcom-gpi.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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@@ -317,6 +318,25 @@
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};
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};
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qup_opp_table: opp-table-qup {
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compatible = "operating-points-v2";
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opp-75000000 {
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opp-hz = /bits/ 64 <75000000>;
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required-opps = <&rpmpd_opp_low_svs>;
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};
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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required-opps = <&rpmpd_opp_svs>;
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};
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opp-128000000 {
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opp-hz = /bits/ 64 <128000000>;
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required-opps = <&rpmpd_opp_nom>;
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};
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};
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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@@ -630,6 +650,125 @@
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status = "disabled";
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};
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qupv3_id_0: geniqup@4ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x0 0x04ac0000 0x0 0x2000>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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iommus = <&apps_smmu 0x3 0x0>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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i2c0: i2c@4a80000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x04a80000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c0_default>;
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dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
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<&gpi_dma0 1 0 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi0: spi@4a80000 {
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compatible = "qcom,geni-spi";
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reg = <0x0 0x04a80000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_spi0_default>;
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power-domains = <&rpmpd SM6375_VDDCX>;
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operating-points-v2 = <&qup_opp_table>;
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dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
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<&gpi_dma0 1 0 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@4a84000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x04a84000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
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interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c1_default>;
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dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
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<&gpi_dma0 1 1 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@4a84000 {
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compatible = "qcom,geni-spi";
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reg = <0x0 0x04a84000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
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interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&rpmpd SM6375_VDDCX>;
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operating-points-v2 = <&qup_opp_table>;
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dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
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<&gpi_dma0 1 1 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@4a88000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x04a88000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c2_default>;
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dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
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<&gpi_dma0 1 2 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi2: spi@4a88000 {
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compatible = "qcom,geni-spi";
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reg = <0x0 0x04a88000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&rpmpd SM6375_VDDCX>;
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operating-points-v2 = <&qup_opp_table>;
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dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
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<&gpi_dma0 1 2 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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/*
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* As per GCC, QUP3/4/5/11 also exist, but are not even defined downstream.
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* There is a comment in the included DTSI of another SoC saying that they
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* are not "bolled out" (probably meaning not routed to solder balls)
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* TLMM driver however, suggests there are as many as 15 QUPs in total!
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* Most of which don't even have pin configurations for.. Sad stuff!
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*/
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};
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gpi_dma1: dma-controller@4c00000 {
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compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma";
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reg = <0 0x04c00000 0 0x60000>;
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@@ -650,6 +789,173 @@
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status = "disabled";
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};
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qupv3_id_1: geniqup@4cc0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x0 0x04cc0000 0x0 0x2000>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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iommus = <&apps_smmu 0xc3 0x0>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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i2c6: i2c@4c80000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x04c80000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
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interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
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<&gpi_dma1 1 0 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi6: spi@4c80000 {
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compatible = "qcom,geni-spi";
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reg = <0x0 0x04c80000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
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interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&rpmpd SM6375_VDDCX>;
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operating-points-v2 = <&qup_opp_table>;
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dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
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<&gpi_dma1 1 0 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c7: i2c@4c84000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x04c84000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
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interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
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<&gpi_dma1 1 1 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi7: spi@4c84000 {
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compatible = "qcom,geni-spi";
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reg = <0x0 0x04c84000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
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interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&rpmpd SM6375_VDDCX>;
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operating-points-v2 = <&qup_opp_table>;
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dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
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<&gpi_dma1 1 1 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c8: i2c@4c88000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x04c88000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
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interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c8_default>;
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dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
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<&gpi_dma1 1 2 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi8: spi@4c88000 {
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compatible = "qcom,geni-spi";
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reg = <0x0 0x04c88000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
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interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&rpmpd SM6375_VDDCX>;
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operating-points-v2 = <&qup_opp_table>;
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dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
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<&gpi_dma1 1 2 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c9: i2c@4c8c000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x04c8c000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
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interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
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<&gpi_dma1 1 3 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi9: spi@4c8c000 {
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compatible = "qcom,geni-spi";
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reg = <0x0 0x04c8c000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
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interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&rpmpd SM6375_VDDCX>;
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operating-points-v2 = <&qup_opp_table>;
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dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
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<&gpi_dma1 1 3 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c10: i2c@4c90000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x04c90000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
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interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c10_default>;
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dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
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<&gpi_dma1 1 4 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi10: spi@4c90000 {
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compatible = "qcom,geni-spi";
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reg = <0x0 0x04c90000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
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interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&rpmpd SM6375_VDDCX>;
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operating-points-v2 = <&qup_opp_table>;
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dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
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<&gpi_dma1 1 4 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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usb_1: usb@4ef8800 {
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compatible = "qcom,sm6375-dwc3", "qcom,dwc3";
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reg = <0 0x04ef8800 0 0x400>;
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