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Merge "hdmi_tx: kill pwm touch's here" into odroidc-3.10.y-android

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Dongjin Kim
2015-01-15 02:17:15 +09:00
committed by Gerrit Code Review
parent a0f1166baa 5536610d37
commit b0ffba7477
1 changed files with 0 additions and 29 deletions
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29
arch/arm/mach-meson8b/hdmi_tx_hw/hdmi_tx_cec_hw.c
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@@ -18,9 +18,7 @@
static DEFINE_MUTEX(cec_mutex);
void cec_arbit_bit_time_set(unsigned bit_set, unsigned time_set, unsigned flag);
unsigned int cec_int_disable_flag = 0;
extern int cec_msg_dbg_en;
void cec_disable_irq(void)
{
@@ -36,32 +34,6 @@ void cec_enable_irq(void)
hdmi_print(INF, CEC "enable:int mask:0x%x\n", aml_read_reg32(P_AO_CEC_INTR_MASKN));
}
void gpiox_10_pin_mux_mask(void){
//GPIOX_10 pin mux masked expect PWM_E
aml_set_reg32_bits(P_PERIPHS_PIN_MUX_3, 0x0, 22, 1); //0x202f bit[22]: XTAL_32K_OUT
aml_set_reg32_bits(P_PERIPHS_PIN_MUX_3, 0x0, 8, 1); //0x202f bit[ 8]: Tsin_D0_B
aml_set_reg32_bits(P_PERIPHS_PIN_MUX_4, 0x0, 23, 1); //0x2030 bit[23]: SPI_MOSI
aml_set_reg32_bits(P_PERIPHS_PIN_MUX_6, 0x0, 17, 1); //0x2032 bit[17]: UART_CTS_B
aml_set_reg32_bits(P_PERIPHS_PIN_MUX_7, 0x0, 31, 1); //0x2033 bit[31]: PWM_VS
aml_set_reg32_bits(P_PERIPHS_PIN_MUX_9, 0x1, 19, 1); //0x2035 bit[19]: PWM_E
}
void pwm_e_config(void){
//PWM E config
aml_set_reg32_bits(P_PWM_PWM_E, 0x25ff, 16, 16); //0x21b0 bit[31:16]: PWM_E_HIGH counter
aml_set_reg32_bits(P_PWM_PWM_E, 0x25fe, 0, 16); //0x21b0 bit[15: 0]: PWM_E_LOW counter
aml_set_reg32_bits(P_PWM_MISC_REG_EF, 0x1, 15, 1); //0x21b2 bit[15] : PWM_E_CLK_EN
aml_set_reg32_bits(P_PWM_MISC_REG_EF, 0x0, 8, 7); //0x21b2 bit[14: 8]: PWM_E_CLK_DIV
aml_set_reg32_bits(P_PWM_MISC_REG_EF, 0x2, 4, 2); //0x21b2 bit[5 : 4]: PWM_E_CLK_SEL :0x2 sleect fclk_div4:637.5M
aml_set_reg32_bits(P_PWM_MISC_REG_EF, 0x1, 0, 1); //0x21b2 bit[0] : PWM_E_EN
}
void pwm_out_rtc_32k(void){
gpiox_10_pin_mux_mask(); //enable PWM_E pin mux
pwm_e_config(); //PWM E config
hdmi_print(INF, CEC "Set PWM_E out put RTC 32K!\n");
}
void cec_hw_reset(void)
{
//unsigned long data32;
@@ -321,7 +293,6 @@ void cec_polling_online_dev(int log_addr, int *bool)
void ao_cec_init(void)
{
unsigned long data32;
pwm_out_rtc_32k(); //enable RTC 32k
// Assert SW reset AO_CEC
data32 = 0;
data32 |= 0 << 1; // [2:1] cntl_clk: 0=Disable clk (Power-off mode); 1=Enable gated clock (Normal mode); 2=Enable free-run clk (Debug mode).