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ASoC: rockchip: refactor i2s driver.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This commit is contained in:
Sugar Zhang
897
sound/soc/rockchip/rk30_i2s.c
Executable file → Normal file
897
sound/soc/rockchip/rk30_i2s.c
Executable file → Normal file
File diff suppressed because it is too large
Load Diff
@@ -1,255 +1,226 @@
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/*
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* rockchip-iis.h - ALSA IIS interface for the Rockchip rk28 SoC
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* Rockchip I2S ALSA SoC Digital Audio Interface(DAI) driver
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*
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* Driver for rockchip iis audio
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* Copyright (C) 2015 Fuzhou Rockchip Electronics Co., Ltd
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/version.h>
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#ifndef _ROCKCHIP_IIS_H
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#define _ROCKCHIP_IIS_H
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#ifndef __RK_I2S_H__
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#define __RK_I2S_H__
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//I2S_TXCR
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/*
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* TXCR
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* transmit operation control register
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*/
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#define I2S_TXCR_RCNT_SHIFT 17
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#define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT)
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#define I2S_TXCR_CSR_SHIFT 15
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#define I2S_TXCR_CSR(x) (x << I2S_TXCR_CSR_SHIFT)
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#define I2S_TXCR_CHN_2 (0 << I2S_TXCR_CSR_SHIFT)
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#define I2S_TXCR_CHN_4 (1 << I2S_TXCR_CSR_SHIFT)
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#define I2S_TXCR_CHN_6 (2 << I2S_TXCR_CSR_SHIFT)
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#define I2S_TXCR_CHN_8 (3 << I2S_TXCR_CSR_SHIFT)
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#define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT)
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#define I2S_TXCR_HWT BIT(14)
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#define I2S_TXCR_SJM_SHIFT 12
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#define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT)
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#define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT)
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#define I2S_TXCR_FBM_SHIFT 11
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#define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT)
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#define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT)
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#define I2S_TXCR_IBM_SHIFT 9
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#define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT)
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#define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT)
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#define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT)
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#define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT)
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#define I2S_TXCR_PBM_SHIFT 7
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#define I2S_TXCR_PBM_MODE(x) (x << I2S_TXCR_PBM_SHIFT)
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#define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT)
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#define I2S_TXCR_TFS_SHIFT 5
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#define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT)
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#define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT)
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#define I2S_TXCR_VDW_SHIFT 0
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#define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT)
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#define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT)
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#define PCM_2DATA (0<<18)
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#define PCM_4DATA (1<<18)
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#define PCM_6DATA (2<<18)
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#define PCM_8DATA (3<<18)
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/*
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* RXCR
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* receive operation control register
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*/
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#define I2S_RXCR_HWT BIT(14)
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#define I2S_RXCR_SJM_SHIFT 12
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#define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT)
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#define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT)
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#define I2S_RXCR_FBM_SHIFT 11
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#define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT)
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#define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT)
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#define I2S_RXCR_IBM_SHIFT 9
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#define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT)
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#define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT)
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#define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT)
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#define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT)
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#define I2S_RXCR_PBM_SHIFT 7
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#define I2S_RXCR_PBM_MODE(x) (x << I2S_RXCR_PBM_SHIFT)
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#define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT)
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#define I2S_RXCR_TFS_SHIFT 5
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#define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT)
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#define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT)
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#define I2S_RXCR_VDW_SHIFT 0
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#define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT)
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#define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT)
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#define CHANNEL_1_EN (0<<15)
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#define CHANNEL_2_EN (1<<15)
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#define CHANNEL_3_EN (2<<15)
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#define CHANNLE_4_EN (3<<15)
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#define TX_MODE_MASTER (0<<13)
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#define TX_MODE_SLAVE (1<<13)
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#define RESET_TX (1<<17)
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#define RESET_RX (1<<16)
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#define I2S_DMA_REQ1_DISABLE (1<<6)
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#define I2S_DMA_REQ1_ENABLE (0)
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#define I2S_DMA_REQ2_DISABLE (1<<5)
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#define I2S_DMA_REQ2_ENABLE (0)
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#define I2S_DMA_REQ1_TX_ENABLE (0)
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#define I2S_DMA_REQ1_RX_ENABLE (1<<4)
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#define I2S_DMA_REQ2_TX_ENABLE (0)
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#define I2S_DMA_REQ2_RX_ENABLE (1<<3)
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#define TX_START (1<<1)
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#define RX_START (1)
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/*
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* CKR
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* clock generation register
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*/
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#define I2S_CKR_MSS_SHIFT 27
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#define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT)
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#define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT)
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#define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT)
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#define I2S_CKR_CKP_SHIFT 26
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#define I2S_CKR_CKP_NEG (0 << I2S_CKR_CKP_SHIFT)
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#define I2S_CKR_CKP_POS (1 << I2S_CKR_CKP_SHIFT)
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#define I2S_CKR_RLP_SHIFT 25
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#define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT)
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#define I2S_CKR_RLP_OPPSITE (1 << I2S_CKR_RLP_SHIFT)
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#define I2S_CKR_TLP_SHIFT 24
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#define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT)
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#define I2S_CKR_TLP_OPPSITE (1 << I2S_CKR_TLP_SHIFT)
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#define I2S_CKR_MDIV_SHIFT 16
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#define I2S_CKR_MDIV(x) ((x) << I2S_CKR_MDIV_SHIFT)
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#define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT)
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#define I2S_CKR_RSD_SHIFT 8
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#define I2S_CKR_RSD(x) ((x) << I2S_CKR_RSD_SHIFT)
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#define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT)
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#define I2S_CKR_TSD_SHIFT 0
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#define I2S_CKR_TSD(x) ((x) << I2S_CKR_TSD_SHIFT)
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#define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT)
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/*
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* FIFOLR
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* FIFO level register
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*/
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#define I2S_FIFOLR_RFL_SHIFT 24
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#define I2S_FIFOLR_RFL_MASK (0x3f << I2S_FIFOLR_RFL_SHIFT)
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#define I2S_FIFOLR_TFL3_SHIFT 18
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#define I2S_FIFOLR_TFL3_MASK (0x3f << I2S_FIFOLR_TFL3_SHIFT)
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#define I2S_FIFOLR_TFL2_SHIFT 12
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#define I2S_FIFOLR_TFL2_MASK (0x3f << I2S_FIFOLR_TFL2_SHIFT)
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#define I2S_FIFOLR_TFL1_SHIFT 6
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#define I2S_FIFOLR_TFL1_MASK (0x3f << I2S_FIFOLR_TFL1_SHIFT)
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#define I2S_FIFOLR_TFL0_SHIFT 0
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#define I2S_FIFOLR_TFL0_MASK (0x3f << I2S_FIFOLR_TFL0_SHIFT)
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/*
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* DMACR
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* DMA control register
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*/
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#define I2S_DMACR_RDE_SHIFT 24
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#define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT)
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#define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT)
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#define I2S_DMACR_RDE_MASK (1 << I2S_DMACR_RDE_SHIFT)
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#define I2S_DMACR_RDL_SHIFT 16
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#define I2S_DMACR_RDL(x) ((x - 1) << I2S_DMACR_RDL_SHIFT)
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#define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT)
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#define I2S_DMACR_TDE_SHIFT 8
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#define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT)
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#define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT)
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#define I2S_DMACR_TDE_MASK (1 << I2S_DMACR_TDE_SHIFT)
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#define I2S_DMACR_TDL_SHIFT 0
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#define I2S_DMACR_TDL(x) ((x) << I2S_DMACR_TDL_SHIFT)
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#define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT)
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//I2S_TXCTL I2S_RXCTL
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#define CLEAR_RXFIFO (1<<24)
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#define TRAN_DEVICES0 (0)
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#define TRAN_DEVICES1 (1<<18)
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#define TRAN_DEVICES2 (2<<18)
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#define TRAN_DEVICES3 (3<<18)
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#define OVERSAMPLING_RATE_32FS (0)
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#define OVERSAMPLING_RATE_64FS (1<<16)
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#define OVERSAMPLING_RATE_128FS (2<<16)
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#define SCK_RATE2 (0x02<<8)
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#define SCK_RATE4 (0x04<<8)
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#define SCK_RATE8 (0x08<<8)
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#define SAMPLE_DATA_8bit (0)
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#define SAMPLE_DATA_16bit (1<<4)
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#define SAMPLE_DATA_MASK (3<<4)
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#define MONO_MODE (1<<3)
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#define STEREO_MODE (0)
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#define I2S_MODE (0)
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#define LEFT_JUSTIFIED (1<<1)
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#define RIGHT_JUSTIFIED (2<<1)
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#define IISMOD_SDF_MASK (3<<1)
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#define MASTER_MODE (1)
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#define SLAVE_MODE (0)
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/*
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* INTCR
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* interrupt control register
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*/
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#define I2S_INTCR_RFT_SHIFT 20
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#define I2S_INTCR_RFT(x) ((x - 1) << I2S_INTCR_RFT_SHIFT)
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#define I2S_INTCR_RXOIC BIT(18)
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#define I2S_INTCR_RXOIE_SHIFT 17
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#define I2S_INTCR_RXOIE_DISABLE (0 << I2S_INTCR_RXOIE_SHIFT)
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#define I2S_INTCR_RXOIE_ENABLE (1 << I2S_INTCR_RXOIE_SHIFT)
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#define I2S_INTCR_RXFIE_SHIFT 16
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#define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTCR_RXFIE_SHIFT)
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#define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTCR_RXFIE_SHIFT)
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#define I2S_INTCR_TFT_SHIFT 4
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#define I2S_INTCR_TFT(x) ((x - 1) << I2S_INTCR_TFT_SHIFT)
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#define I2S_INTCR_TFT_MASK (0x1f << I2S_INTCR_TFT_SHIFT)
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#define I2S_INTCR_TXUIC BIT(2)
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#define I2S_INTCR_TXUIE_SHIFT 1
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#define I2S_INTCR_TXUIE_DISABLE (0 << I2S_INTCR_TXUIE_SHIFT)
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#define I2S_INTCR_TXUIE_ENABLE (1 << I2S_INTCR_TXUIE_SHIFT)
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//I2S_FIFOSTS
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#define TX_HALF_FULL (1<<18)
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#define RX_HALF_FULL (1<<16)
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/*
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* INTSR
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* interrupt status register
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*/
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#define I2S_INTSR_RXOI_SHIFT 17
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#define I2S_INTSR_RXOI_INA (0 << I2S_INTSR_RXOI_SHIFT)
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#define I2S_INTSR_RXOI_ACT (1 << I2S_INTSR_RXOI_SHIFT)
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#define I2S_INTSR_RXFI_SHIFT 16
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#define I2S_INTSR_RXFI_INA (0 << I2S_INTSR_RXFI_SHIFT)
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#define I2S_INTSR_RXFI_ACT (1 << I2S_INTSR_RXFI_SHIFT)
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#define I2S_INTSR_TXUI_SHIFT 1
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#define I2S_INTSR_TXUI_INA (0 << I2S_INTSR_TXUI_SHIFT)
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#define I2S_INTSR_TXUI_ACT (1 << I2S_INTSR_TXUI_SHIFT)
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#define I2S_INTSR_TXEI_SHIFT 0
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#define I2S_INTSR_TXEI_INA (0 << I2S_INTSR_TXEI_SHIFT)
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#define I2S_INTSR_TXEI_ACT (1 << I2S_INTSR_TXEI_SHIFT)
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/*
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* XFER
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* Transfer start register
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*/
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#define I2S_XFER_RXS_SHIFT 1
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#define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT)
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#define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT)
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#define I2S_XFER_RXS_MASK (1 << I2S_XFER_RXS_SHIFT)
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#define I2S_XFER_TXS_SHIFT 0
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#define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT)
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#define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT)
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#define I2S_XFER_TXS_MASK (1 << I2S_XFER_TXS_SHIFT)
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/*
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* CLR
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* clear SCLK domain logic register
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*/
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#define I2S_CLR_RXC BIT(1)
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#define I2S_CLR_RXC_MASK BIT(1)
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#define I2S_CLR_TXC BIT(0)
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#define I2S_CLR_TXC_MASK BIT(0)
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/* I2S REGS */
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#define I2S_TXCR (0x0000)
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#define I2S_RXCR (0x0004)
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#define I2S_CKR (0x0008)
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#define I2S_FIFOLR (0x000c)
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#define I2S_DMACR (0x0010)
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#define I2S_INTCR (0x0014)
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#define I2S_INTSR (0x0018)
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#define I2S_XFER (0x001c)
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#define I2S_CLR (0x0020)
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#define I2S_TXDR (0x0024)
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#define I2S_RXDR (0x0028)
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/* Clock dividers */
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#define ROCKCHIP_DIV_MCLK 0
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#define ROCKCHIP_DIV_BCLK 1
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#define ROCKCHIP_DIV_PRESCALER 2
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/* channel */
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#define I2S_CHANNEL_8 8
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#define I2S_CHANNEL_6 6
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#define I2S_CHANNEL_4 4
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#define I2S_CHANNEL_2 2
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/* I2S_TXCR */
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#define I2S_RSTL_SCLK(c) ((c&0x3F)<<26)
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#define I2S_RSTR_SCLK(c) ((c&0x3F)<<20)
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#define I2S_PCM_2DATA (0<<18)
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#define I2S_PCM_4DATA (1<<18)
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#define I2S_PCM_6DATA (2<<18)
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#define I2S_PCM_8DATA (3<<18)
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#define I2S_PCM_DATA_MASK (3<<18)
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#define I2S_CSR_CH2 (0<<15)
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#define I2S_CSR_CH4 (1<<15)
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#define I2S_CRS_CH6 (2<<15)
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#define I2S_CRS_CH8 (3<<15)
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#define I2S_CRS_CH_MASK (3<<15)
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#define I2S_HWT_16BIT (0<<14)
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#define I2S_HWT_32BIT (1<<14)
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#ifdef CONFIG_ARCH_RK29
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#define I2S_MASTER_MODE (0<<13)
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#define I2S_SLAVE_MODE (1<<13)
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#define I2S_MODE_MASK (1<<13)
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#endif
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#define I2S_JUSTIFIED_RIGHT (0<<12)
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#define I2S_JUSTIFIED_LEFT (1<<12)
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#define I2S_FIRST_BIT_MSB (0<<11)
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#define I2S_FIRST_BIT_LSB (1<<11)
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#define I2S_BUS_MODE_NOR (0<<9)
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#define I2S_BUS_MODE_LSJM (1<<9)
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#define I2S_BUS_MODE_RSJM (2<<9)
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#define I2S_BUS_MODE_MASK (3<<9)
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#define I2S_PCM_NO_DELAY (0<<7)
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#define I2S_PCM_DELAY_1MODE (1<<7)
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#define I2S_PCM_DELAY_2MODE (2<<7)
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#define I2S_PCM_DELAY_3MODE (3<<7)
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#define I2S_PCM_DELAY_MASK (3<<7)
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#define I2S_TX_LRCK_OUT_BT_DISABLE (0<<6)
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#define I2S_TX_LRCK_OUT_BT_ENABLE (1<<6)
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|
||||
#define I2S_TX_LRCK_OUT_I2S (0<<5)
|
||||
#define I2S_TX_LRCK_OUT_PCM (1<<5)
|
||||
|
||||
#define I2S_DATA_WIDTH(w) ((w&0x1F)<<0)
|
||||
|
||||
/* */
|
||||
|
||||
|
||||
/* I2S_TXCKR */
|
||||
#ifdef CONFIG_ARCH_RK29
|
||||
#define I2S_TSP_POSEDGE (0<<25)
|
||||
#define I2S_TSP_NEGEDGE (1<<25)
|
||||
#define I2S_TLP_NORMAL (0<<24)
|
||||
#define I2S_TLP_OPPSITE (1<<24)
|
||||
|
||||
#define I2S_MCLK_DIV(x) ((0xFF&x)<<16)
|
||||
#define I2S_MCLK_DIV_MASK ((0xFF)<<16)
|
||||
|
||||
#define I2S_TSD_FIXED (0<<12)
|
||||
#define I2S_TSD_CHANGED (1<<12)
|
||||
|
||||
#define I2S_TX_LRCK_NO_DELAY (0<<10)
|
||||
#define I2S_TX_LRCK_DELAY_ONE (1<<10)
|
||||
#define I2S_TX_LRCK_DELAY_TWO (2<<10)
|
||||
#define I2S_TX_LRCK_DELAY_THREE (3<<10)
|
||||
#define I2S_TX_LRCK_DELAY_MASK (3<<10)
|
||||
|
||||
#define I2S_TX_SCLK_DIV(x) (x&0x3FF)
|
||||
#define I2S_TX_SCLK_DIV_MASK (0x3FF);
|
||||
#else
|
||||
//I2S_CKR
|
||||
#define I2S_MASTER_MODE (0<<27)
|
||||
#define I2S_SLAVE_MODE (1<<27)
|
||||
#define I2S_MODE_MASK (1<<27)
|
||||
|
||||
#define I2S_BCLK_POSEDGE (0<<26)//sclk polarity invert??
|
||||
#define I2S_BCLK_NEGEDGE (1<<26)
|
||||
|
||||
#define I2S_RX_LRCK_POSEDGE (0<<25)//LRCK polarity invert??
|
||||
#define I2S_RX_LRCK_NEGEDGE (1<<25)
|
||||
|
||||
#define I2S_TX_LRCK_POSEDGE (0<<24)
|
||||
#define I2S_TX_LRCK_NEGEDGE (1<<24)
|
||||
|
||||
#define I2S_MCLK_DIV(x) ((0xFF&x)<<16)
|
||||
#define I2S_MCLK_DIV_MASK ((0xFF)<<16)
|
||||
|
||||
#define I2S_RX_SCLK_DIV(x) ((x&0xFF)<<8)
|
||||
#define I2S_RX_SCLK_DIV_MASK ((0xFF)<<8)
|
||||
|
||||
#define I2S_TX_SCLK_DIV(x) (x&0xFF)
|
||||
#define I2S_TX_SCLK_DIV_MASK (0xFF)
|
||||
#endif
|
||||
|
||||
/* I2S_DMACR */
|
||||
#define I2S_RECE_DMA_DISABLE (0<<24)
|
||||
#define I2S_RECE_DMA_ENABLE (1<<24)
|
||||
#define I2S_DMARDL(x) ((x&0x1f)<<16)
|
||||
|
||||
#define I2S_TRAN_DMA_DISABLE (0<<8)
|
||||
#define I2S_TRAN_DMA_ENABLE (1<<8)
|
||||
#define I2S_DMATDL(x) ((x&0x1f)<<0)
|
||||
|
||||
/* I2S_INTCR */
|
||||
#define I2S_RXOV_INT_DISABLE (0<<17)
|
||||
#define I2S_RXOV_INT_ENABLE (1<<17)
|
||||
#define I2S_RXFU_INT_DISABLE (0<<16)
|
||||
#define I2S_RXFU_INT_ENABLE (1<<16)
|
||||
|
||||
#define I2S_TXUND_INT_DISABLE (0<<1)
|
||||
#define I2S_TXUND_INT_ENABLE (1<<1)
|
||||
#define I2S_TXEMP_INT_DISABLE (0<<0)
|
||||
#define I2S_TXEMP_INT_ENABLE (1<<0)
|
||||
|
||||
/* I2S_XFER */
|
||||
#define I2S_RX_TRAN_STOP (0<<1)
|
||||
#define I2S_RX_TRAN_START (1<<1)
|
||||
#define I2S_TX_TRAN_STOP (0<<0)
|
||||
#define I2S_TX_TRAN_START (1<<0)
|
||||
|
||||
//I2S_CLR
|
||||
#define I2S_RX_CLEAR (1<<1)
|
||||
#define I2S_TX_CLEAR 1
|
||||
|
||||
#ifdef CONFIG_ARCH_RK29
|
||||
#define I2S_TXR_BUFF 0x20
|
||||
#define I2S_RXR_BUFF 0x24
|
||||
//I2S Registers
|
||||
typedef volatile struct tagIIS_STRUCT
|
||||
{
|
||||
unsigned int I2S_TXCR;
|
||||
unsigned int I2S_RXCR;
|
||||
unsigned int I2S_TXCKR;
|
||||
unsigned int I2S_RXCKR;
|
||||
unsigned int I2S_FIFOLR;
|
||||
unsigned int I2S_DMACR;
|
||||
unsigned int I2S_INTCR;
|
||||
unsigned int I2S_INTSR;
|
||||
unsigned int I2S_TXDR;
|
||||
unsigned int I2S_RXDR;
|
||||
unsigned int I2S_XFER;
|
||||
unsigned int I2S_TXRST;
|
||||
unsigned int I2S_RXRST;
|
||||
}I2S_REG,*pI2S_REG;
|
||||
#else
|
||||
#define I2S_TXR_BUFF 0x24
|
||||
#define I2S_RXR_BUFF 0x28
|
||||
typedef volatile struct tagIIS_STRUCT
|
||||
{
|
||||
unsigned int I2S_TXCR;//0xF 0
|
||||
unsigned int I2S_RXCR;//0xF 4
|
||||
unsigned int I2S_CKR;//0x3F 8
|
||||
unsigned int I2S_FIFOLR;//c
|
||||
unsigned int I2S_DMACR;//0x001F0110 10
|
||||
unsigned int I2S_INTCR;//0x01F00000 14
|
||||
unsigned int I2S_INTSR;//0x00 18
|
||||
unsigned int I2S_XFER;//0x00000003 1c
|
||||
unsigned int I2S_CLR;//20
|
||||
unsigned int I2S_TXDR;//24
|
||||
unsigned int I2S_RXDR;
|
||||
}I2S_REG,*pI2S_REG;
|
||||
#endif
|
||||
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
|
||||
extern struct snd_soc_dai_driver rk29_i2s_dai[];
|
||||
#else
|
||||
extern struct snd_soc_dai rk29_i2s_dai[];
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SND_SOC_RT5631
|
||||
extern struct delayed_work rt5631_delay_cap; //bard 7-16
|
||||
#endif
|
||||
|
||||
#endif /* _ROCKCHIP_IIS_H */
|
||||
#endif /* __RK_I2S_H__ */
|
||||
|
||||
Reference in New Issue
Block a user