NNA: add NNA support on sm1 [1/1]

PD#SWPL-5380

Problem:
sm1 not support NNA now.

Solution:
add NNA support.

Verify:
sm1_ac200 & sm1_skt

Change-Id: I3de566bbc730ef69f26160ad9f915ac92b4f2e2b
Signed-off-by: Cancan Chang <cancan.chang@amlogic.com>

arch/arm/boot/dts/amlogic/mesonsm1.dtsi

@@ -1097,6 +1097,30 @@
 		};
 	};
 
+	galcore {
+		compatible = "amlogic, galcore";
+		dev_name = "galcore";
+		status = "disabled";
+		clocks = <&clkc CLKID_VNANOQ_AXI_CLK_COMP>,
+			<&clkc CLKID_VNANOQ_CORE_CLK_COMP>;
+		clock-names = "cts_vipnanoq_axi_clk_composite",
+			"cts_vipnanoq_core_clk_composite";
+		interrupts = <0 186 4>;
+		interrupt-names = "galcore";
+		reg = <0xff100000 0x800
+			/*reg base value:0xff100000 */
+			0xff000000 0x400000
+			/*Sram bse value:0xff000000*/
+			0xff63c118 0x0
+			0xff63c11c 0x0
+			/*0xff63c118,0xff63c11c :nanoq mem regs*/
+			0xff8000e8 0x0
+			0xff8000ec 0x0
+			/*0xff8000e8,0xff8000e8 :ao regs*/
+			0xffd01088 0x0
+			/*0xffd01088:reset reg*/
+			>;
+	};
 	aocec: aocec {
 		compatible = "amlogic, aocec-g12a";
 		device_name = "aocec";

arch/arm/boot/dts/amlogic/sm1_s905d3_ac200.dts

@@ -160,6 +160,9 @@
 		};
 	};
 
+	galcore {
+		status = "okay";
+	};
 	gpioleds {
 		compatible = "gpio-leds";
 		status = "okay";

arch/arm/boot/dts/amlogic/sm1_s905d3_skt.dts

@@ -160,6 +160,9 @@
 		};
 	};
 
+	galcore {
+		status = "okay";
+	};
 	gpioleds {
 		compatible = "gpio-leds";
 		status = "okay";

arch/arm64/boot/dts/amlogic/mesonsm1.dtsi

@@ -1097,6 +1097,30 @@
 		};
 	};
 
+	galcore {
+		compatible = "amlogic, galcore";
+		dev_name = "galcore";
+		status = "disabled";
+		clocks = <&clkc CLKID_VNANOQ_AXI_CLK_COMP>,
+			<&clkc CLKID_VNANOQ_CORE_CLK_COMP>;
+		clock-names = "cts_vipnanoq_axi_clk_composite",
+			"cts_vipnanoq_core_clk_composite";
+		interrupts = <0 186 4>;
+		interrupt-names = "galcore";
+		reg = <0x0 0xff100000 0x0 0x800
+			/*reg base value:0xff100000 */
+			0x0 0xff000000 0x0 0x400000
+			/*Sram bse value:0xff000000*/
+			0x0 0xff63c118 0x0 0x0
+			0x0 0xff63c11c 0x0 0x0
+			/*0xff63c118,0xff63c11c :nanoq mem regs*/
+			0x0 0xff8000e8 0x0 0x0
+			0x0 0xff8000ec 0x0 0x0
+			/*0xff8000e8,0xff8000e8 :ao regs*/
+			0x0 0xffd01088 0x0 0x0
+			/*0xffd01088:reset reg*/
+			>;
+	};
 	aocec: aocec {
 		compatible = "amlogic, aocec-g12a";
 		device_name = "aocec";

arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200.dts

@@ -158,6 +158,9 @@
 		};
 	};
 
+	galcore {
+		status = "okay";
+	};
 	gpioleds {
 		compatible = "gpio-leds";
 		status = "okay";

arch/arm64/boot/dts/amlogic/sm1_s905d3_skt.dts

@@ -158,6 +158,9 @@
 		};
 	};
 
+	galcore {
+		status = "okay";
+	};
 	gpioleds {
 		compatible = "gpio-leds";
 		status = "okay";

drivers/amlogic/clk/sm1/sm1.c

@@ -55,6 +55,91 @@ static struct meson_clk_pll sm1_gp1_pll = {
 	},
 };
 
+static const char * const media_parent_names[] = { "xtal",
+	"gp0_pll", "hifi_pll", "fclk_div2p5", "fclk_div3", "fclk_div4",
+	"fclk_div5",  "fclk_div7"};
+
+static struct clk_mux cts_vipnanoq_core_clk_mux = {
+	.reg = (void *)HHI_VIPNANOQ_CLK_CNTL,
+	.mask = 0x7,
+	.shift = 9,
+	.lock = &clk_lock,
+	.hw.init = &(struct clk_init_data){
+		.name = "cts_vipnanoq_core_clk_mux",
+		.ops = &clk_mux_ops,
+		.parent_names = media_parent_names,
+		.num_parents = 8,
+		.flags = CLK_GET_RATE_NOCACHE,
+	},
+};
+
+static struct clk_divider cts_vipnanoq_core_clk_div = {
+	.reg = (void *)HHI_VIPNANOQ_CLK_CNTL,
+	.shift = 0,
+	.width = 7,
+	.lock = &clk_lock,
+	.hw.init = &(struct clk_init_data){
+		.name = "cts_vipnanoq_core_clk_div",
+		.ops = &clk_divider_ops,
+		.parent_names = (const char *[]){ "cts_vipnanoq_core_clk_mux" },
+		.num_parents = 1,
+		.flags = CLK_GET_RATE_NOCACHE,
+	},
+};
+
+static struct clk_gate cts_vipnanoq_core_clk_gate = {
+	.reg = (void *)HHI_VIPNANOQ_CLK_CNTL,
+	.bit_idx = 8,
+	.lock = &clk_lock,
+	.hw.init = &(struct clk_init_data) {
+		.name = "cts_vipnanoq_core_clk_gate",
+		.ops = &clk_gate_ops,
+		.parent_names = (const char *[]){ "cts_vipnanoq_core_clk_div" },
+		.num_parents = 1,
+		.flags = CLK_GET_RATE_NOCACHE,
+	},
+};
+
+static struct clk_mux cts_vipnanoq_axi_clk_mux = {
+	.reg = (void *)HHI_VIPNANOQ_CLK_CNTL,
+	.mask = 0x7,
+	.shift = 25,
+	.lock = &clk_lock,
+	.hw.init = &(struct clk_init_data){
+		.name = "cts_vipnanoq_axi_clk_mux",
+		.ops = &clk_mux_ops,
+		.parent_names = media_parent_names,
+		.num_parents = 8,
+		.flags = CLK_GET_RATE_NOCACHE,
+	},
+};
+
+static struct clk_divider cts_vipnanoq_axi_clk_div = {
+	.reg = (void *)HHI_VIPNANOQ_CLK_CNTL,
+	.shift = 16,
+	.width = 7,
+	.lock = &clk_lock,
+	.hw.init = &(struct clk_init_data){
+		.name = "cts_vipnanoq_axi_clk_div",
+		.ops = &clk_divider_ops,
+		.parent_names = (const char *[]){ "cts_vipnanoq_axi_clk_mux" },
+		.num_parents = 1,
+		.flags = CLK_GET_RATE_NOCACHE,
+	},
+};
+
+static struct clk_gate cts_vipnanoq_axi_clk_gate = {
+	.reg = (void *)HHI_VIPNANOQ_CLK_CNTL,
+	.bit_idx = 24,
+	.lock = &clk_lock,
+	.hw.init = &(struct clk_init_data) {
+		.name = "cts_vipnanoq_axi_clk_gate",
+		.ops = &clk_gate_ops,
+		.parent_names = (const char *[]){ "cts_vipnanoq_axi_clk_div" },
+		.num_parents = 1,
+		.flags = CLK_GET_RATE_NOCACHE,
+	},
+};
 static struct clk_mux sm1_dsu_pre_src_clk_mux0 = {
 	.reg = (void *)HHI_SYS_CPU_CLK_CNTL5,
 	.mask = 0x3,
@@ -276,7 +361,18 @@ static void __init sm1_clkc_init(struct device_node *np)
 		+ (unsigned long)sm1_dsu_pre_clk.reg;
 	sm1_dsu_clk.reg = clk_base
 		+ (unsigned long)sm1_dsu_clk.reg;
-
+	cts_vipnanoq_core_clk_mux.reg = clk_base
+		+ (unsigned long)(cts_vipnanoq_core_clk_mux.reg);
+	cts_vipnanoq_core_clk_gate.reg = clk_base
+		+ (unsigned long)(cts_vipnanoq_core_clk_gate.reg);
+	cts_vipnanoq_core_clk_div.reg = clk_base
+		+ (unsigned long)(cts_vipnanoq_core_clk_div.reg);
+	cts_vipnanoq_axi_clk_mux.reg = clk_base
+		+ (unsigned long)(cts_vipnanoq_axi_clk_mux.reg);
+	cts_vipnanoq_axi_clk_gate.reg = clk_base
+		+ (unsigned long)(cts_vipnanoq_axi_clk_gate.reg);
+	cts_vipnanoq_axi_clk_div.reg = clk_base
+		+ (unsigned long)(cts_vipnanoq_axi_clk_div.reg);
 	/* Populate base address for gates */
 	for (i = 0; i < ARRAY_SIZE(sm1_clk_gates); i++)
 		sm1_clk_gates[i]->reg = clk_base +
@@ -305,7 +401,31 @@ static void __init sm1_clkc_init(struct device_node *np)
 			}
 		}
 	}
+	clks[CLKID_VNANOQ_CORE_CLK_COMP] = clk_register_composite(NULL,
+		"cts_vipnanoq_core_clk_composite",
+		media_parent_names, 8,
+		&cts_vipnanoq_core_clk_mux.hw,
+		&clk_mux_ops,
+		&cts_vipnanoq_core_clk_div.hw,
+		&clk_divider_ops,
+		&cts_vipnanoq_core_clk_gate.hw,
+		&clk_gate_ops, 0);
+	if (IS_ERR(clks[CLKID_VNANOQ_CORE_CLK_COMP]))
+		panic("%s: %d register cts_vipnanoq_core_clk_composite error\n",
+			__func__, __LINE__);
 
+	clks[CLKID_VNANOQ_AXI_CLK_COMP] = clk_register_composite(NULL,
+		"cts_vipnanoq_axi_clk_composite",
+		media_parent_names, 8,
+		&cts_vipnanoq_axi_clk_mux.hw,
+		&clk_mux_ops,
+		&cts_vipnanoq_axi_clk_div.hw,
+		&clk_divider_ops,
+		&cts_vipnanoq_axi_clk_gate.hw,
+		&clk_gate_ops, 0);
+	if (IS_ERR(clks[CLKID_VNANOQ_AXI_CLK_COMP]))
+		panic("%s: %d register cts_vipnanoq_axi_clk_composite error\n",
+			__func__, __LINE__);
 	if (clks[CLKID_CPU_CLK]) {
 		if (!of_property_read_bool(np, "own-dsu-clk"))
 			return;