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ASoC: rockchip: spdif: Simplify the mclk calculation

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This patch simplifies the mclk calculation to 128fs, which
is generally required in some receivers.

Change-Id: I2914ab57453ee5f764885fa8fa9dacd44a67e775
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This commit is contained in:
Sugar Zhang
2018-12-19 11:46:51 +08:00
committed by Tao Huang
parent 3c6e63c35b
commit b255c8e1b2
1 changed files with 7 additions and 26 deletions
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33
sound/soc/rockchip/rockchip_spdif.c
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@@ -101,25 +101,14 @@ static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
{
struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
unsigned int val = SPDIF_CFGR_HALFWORD_ENABLE;
int srate, mclk;
int mclk;
int ret;
srate = params_rate(params);
switch (srate) {
case 32000:
case 48000:
case 96000:
mclk = 96000 * 128; /* 12288000 hz */
break;
case 44100:
mclk = 44100 * 256; /* 11289600 hz */
break;
case 192000:
mclk = 192000 * 128; /* 24576000 hz */
break;
default:
return -EINVAL;
}
/* bmc = 128fs */
mclk = 128 * params_rate(params);
ret = clk_set_rate(spdif->mclk, mclk);
if (ret)
return ret;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
@@ -135,15 +124,7 @@ static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
return -EINVAL;
}
/* Set clock and calculate divider */
ret = clk_set_rate(spdif->mclk, mclk);
if (ret != 0) {
dev_err(spdif->dev, "Failed to set module clock rate: %d\n",
ret);
return ret;
}
val |= SPDIF_CFGR_CLK_DIV(mclk/(srate * 256));
val |= SPDIF_CFGR_CLK_DIV(0);
ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,
SPDIF_CFGR_CLK_DIV_MASK | SPDIF_CFGR_HALFWORD_ENABLE |
SDPIF_CFGR_VDW_MASK,